Sync imx8mm.dtsi with linux-next 20231019.
The motivation for doing this sync was a bug when doing "ums 0 mmc 1"
on imx8mm-evk. It worked well for the first time, but after doing
a CTRL+C and launching the ums again, the command did not work.
Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was
a recent USB power domain reorganization there.
After syncing the imx8mm.dtsi with Linux, the ums command works without
problem after a CTRL+C.
Suggested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Currently, the imx8mp_evk uses the non-DM code to initialize the PMIC.
Convert to DM_PMIC, which is the recommended way to access the PMIC.
While at it, fix multi-line comments style.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add the TPM device found on the GW73xx revision F PCB.
This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add the TPM device found on the GW73xx revision F PCB.
This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add Variscite manufacturer to the IMX8MN_VAR_SOM target menu label as
the majority of targets include the manufacturer as part of their menu
description/label and it helps when looking for a particular
manufacturer/board.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The correct compatible string for i.MX93 variant of DWC EQoS MAC is now
"nxp,imx93-dwmac-eqos".
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Add a common board_interface_eth_init() called by the DWC MAC driver to
setup the MAC <-> PHY interface according to the PHY mode obtained from
DT.
Remove the board-side configuration in the i.MX93 EVK files.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Change boot device logic to also allow environment stored in fat and
in ext4 when booting from SD or eMMC.
As the boot device check for SD and for eMMC was depending on
ENV_IS_IN_MMC being defined, change the ifdef blocks at
env_get_location to use IS_ENABLED instead for all modes, returning
NOWHERE when no valid mode is found.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Move an OEM closing logic to ahab_close() function to be able to use
it directly without calling a u-boot command.
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
The interrupt collector macro name for i.MX23 is MXS_ICOLL_BASE,
this is correct and matches the documentation of both i.MX23 and
i.MX28. Align the i.MX28 macro accordingly. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Sync the devicetree files used in the kernel for the imx8mm-phyboard-polis
with the corresponding devicetree files in U-Boot.
Replaced phycore-imx8mm.dts with kernel dts imx8mm-phyboard-polis-rdk.dts
Synced with kernel 6.5.0-rc1 commit
e752a4f9589c (arm64: dts: freescale: imx8mm-phyboard: Add I2C4 pinmuxing)
Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
Commit 0aea5dda29 ("ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS
operation") did a temporary workaround by addng the usdhc1 fix
inside the -u-boot.dtsi file.
The imx7d-sdb.dts from kernel 6.5-rc1 contains the proper UHS
fix, so sync the devicetree tree and remove the previous fix
from -u-boot.dtsi.
Also, adjust the PMIC node name inside pmic_get() to match
the devicetree update.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Add support for the Polyhex Debix Model A SBC board.
It is an industrial grade single board computer based on
NXP's i.MX 8M Plus.
Currently supported interfaces are:
- Serial console
- Micro SD
- eQOS and FEC Ethernet
imx8mp-debix-model-a.dts is taken from Linux 6.3.
Signed-off-by: Gilles Talis <gilles.talis@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The commit in linux kernel 81186dc16101 ("dt-bindings: zynqmp: add
destination mailbox compatible") make compatible string for child nodes
mandatory that's why add it.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Link: https://lore.kernel.org/r/20231204215620.63334-5-tanmay.shah@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The aliases and chosen nodes are currently indented using spaces.
Fix them to use the standard tab indentation.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.
Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset
Signed-off-by: Fabio Estevam <festevam@denx.de>
USB host interface is not working on some Apalis Toradex carrier
boards with Apalis iMX8 SoM. This is due to USBH_EN pin, which
powers USB peripherals, having a strong pull-down on some boards,
and a weak pull-down on the others. This USBH_EN pin is left
unconfigured, which means it is in its default state at cold boot:
input with a strong pull-up. As a result, carrier boards with a
weak pull-down have this signal high enough to trigger power
delivery to USB peripherals, and opposite - boards with strong
pull-down on USBH_EN have this signal below the threshold needed
to trigger USB power delivery.
This change configures the USBH_EN pin as gpio hog, fixing this
issue for all Apalis carrier boards regardless of pull-down
resistor value.
Also, update apalis-imx8_defconfig via savedefconfig.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
On branch WIP/17Oct2023, the EEPROM can no longer be read:
U-Boot 2023.10-latest (Oct 17 2023 - 15:53:43 -0400)
CPU: Freescale i.MX8MNano Quad rev1.0 at 1200 MHz
Reset cause: POR
Model: Variscite VAR-SOM-MX8MN Symphony evaluation board
var_read_som_eeprom: uclass_get_device_by_of_offset() failed: -19
initcall failed at call 000000004022207c (err=-19)
Convert EEPROM-related properties to bootph-all so that the EEPROM can
also be read outside of SPL.
Fixes: 9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The memory maps for Apple's M2 Pro/Max/Ultra left MMIO space out which
was not used by any driver at the time. The display out exposed as
simple-framebuffer use a power-domain controlled by a device in an
unmapped region.
Add a map covering this region as well as another MMIO region in the
range 0x4'0000'0000 - 0x5'0000'0000. The added regions cover all MMIO
annotated in Apple's device tree in this range.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Eric Curtin <ecurtin@redhat.com>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
The OrangePi Zero 3 is a small development board featuring the Allwinner
H618 SoC, shipping with up to 4GB of DRAM, Gigabit Ethernet, a micro-HDMI
connector and two USB sockets.
The board uses LPDDR4 DRAM and an X-Powers AXP313a PMIC, support for
which was recently added to U-Boot.
Add a defconfig file selecting the right drivers and DRAM options.
Since the .dts file was synced from the Linux kernel repo already, we
just need to add one line to the Makefile to actually build the .dtb.
The DRAM parameters were derived from the values found in the BSP DRAM
drivers on the SPI NOR flash.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Tested-by: Bob McChesney <bob@electricworry.net>
Tested-by: Stephen Graf <stephen.graf@gmail.com>
The current emac setting is not suitable for Orange Pi Zero 3,
move it back to Orange Pi Zero 2 DT. Also update phy mode and
delay values for emac on Orange Pi Zero 3.
With these changes, Ethernet now looks stable.
Fixes: 95c3b0635e ("sunxi: dts: arm64: update devicetree files from Linux-v6.6-rc6")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
As requirement of CR side, QSPI Flash usage via RPC driver shall
be disabled and leaving the control of this module to CR side.
Perform DT modification to disable the RPC SPI.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Do not modify defconfig, modify the DT instead, this way
the RPC SPI can be enabled without recompiling the U-Boot
itself. Update commit message accordingly.]
Use the phandle reference to &rpc node in arch/arm/dts/r8a779g0.dtsi
and remove properties which are already in arch/arm/dts/r8a779g0.dtsi.
No functional change and no resulting DT change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
To quote the author:
The show_board_info() function was adjusted to weak so that it could be
entirely replaced with a board-specific implementation.
The intended way for boards to provide their own information is via a
sysinfo driver. But currently there is no way to show anything other
than the model name.
This series adds support for showing a few more items, in a way that is
easy for boards to extend.
Since there is already a weak checkboard() function, we don't need to
have two levels of weak function here. So this series drops the weak
attribute from show_board_info()
Existing boards will see a slight change in output, in that the model
name will appear first, before any custom output. If that is a problem,
then the solution is to implement a sysinfo driver for the board.
Boards can use a sysinfo driver if a particular model name is needed.
Update this board to use checkboard() directly, rather than having a
weak function laid on top of a weak function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Enable USB PHY nodes on ASUS Transformers, Grouper, Enadevoru
and LG X3. This is not mandatory since driver will use default
values but preferable for new devices.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Since required drivers were merged, we can safely clean up the
board and switch to DM based driver with device tree support.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Since required drivers were merged, we can safely clean up the
board and switch to DM based driver with device tree support.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Since required drivers were merged, we can safely clean up the
board and switch to DM based driver with device tree support.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Since required drivers were merged, we can safely clean up the
board and switch to DM based driver with device tree support.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Call regulators_enable_boot_on on board init to set all regulators
with boot-on property in device tree. If regulator is not used by
any device in the device tree but is essential for the device to
work a regression will occur.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Instead of duplicating the I2C3 node and adding NVEC specific
properties, reuse the I2C3 node, extend it with NVEC specific properties
and drop properties that are not needed by NVEC. This results in a DTB
that is a bit cleaner and avoids accidentally using I2C3 and NVEC which
would have them fight over the same hardware resources.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Modify spi and usb aliases name.
Add dt-binding for usb phy define and fix usb phy reset error.
Add tpm/otpee and host_intf node.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Draco is a family of 3 boards: thuban, rastaban & etamin. Rename all
targets of the family adding the draco- prefix to increase readibility
and simplify future commits about concerning all boards of the family.
The name draco was initially used for the first target. It's deprecated
since a 2nd target was introduced. Unfortunately the draco target was
copied to the thuban target instead to be renamed. Remove it to save
unnecessary maintenance effort.
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
Reduce redundancy in code by using templates to generate the A72 boot
binaries (tispl.bin and u-boot.img) as well as R5 boot binary sysfw.itb
(for legacy boot following devices J721E and AM65x).
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Add templates for FIT images used extensively across K3 boards with most
of the code common. This includes the FIT portions of:
- tispl.bin
- u-boot.img
- sysfw.itb (in case of legacy boot flow)
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Kernel dts import now provides bootph-all and bootph-pre-ram properties
for the properties we have been overriding so far. Drop the same.
While at this enable the DM and TIFS UARTs for programming pinmux
since they are marked reserved by board.dts
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Tested-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Kernel dts import now provides bootph-all and bootph-pre-ram properties
for the properties we have been overriding so far. Drop the same.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Tested-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
k3-am62* SoC dtsi files now provide the following:
bootph-all: dmss secure_proxy_main dmsc k3_pds k3_clks k3_reset
main_pmx0 main_timer0 mcu_pmx0 wkup_conf chipid
bootph-pre-ram: secure_proxy_sa3 main_esm mcu_esm
Drop these from board r5 and u-boot.dtsi files as these are duplicate in
them now.
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Tested-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Sync with kernel v6.7-rc1 and sync up the u-boot dts files accordingly.
Tested-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
BCDMA can be used at SPL for OSPI boot and mem-to-mem DMA
so add "bootph-all" to BCDMA node.
Suggested-by: Nishanth Menon <nm@ti.com>
Fixes: 9a3f2b6798 ("arm: dts: k3-am625-verdin-wifi-dev-u-boot.dtsi: Fix DMA/Ethernet")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Change spl_enable_dcache so it also enable icache on SPL
initialization for the main domain part of the boot flow. This
improves bootloader booting time.
Link: https://lore.kernel.org/all/20231109140958.1093235-1-joao.goncalves@toradex.com/
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Tested-by: Nishanth Menon <nm@ti.com>
main_timer0 is used by u-boot as the tick-timer. Add it to the soc
devices list so it an be enabled via the k3 power controller.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
BeagleBoard.org BeagleBone AI-64 is an open source hardware single
board computer based on the Texas Instruments TDA4VM SoC featuring
dual-core 2.0GHz Arm Cortex-A72 processor, C7x+MMA and 2 C66x
floating-point VLIW DSPs, 3x dual ARM Cortex-R5 co-processors,
2x 6-core Programmable Real-Time Unit and Industrial Communication
SubSystem, PowerVR Rogue 8XE GE8430 3D GPU. The board features 4GB
DDR4, USB3.0 Type-C, 2x USB SS Type-A, miniDisplayPort, 2x 4-lane
CSI, DSI, 16GB eMMC flash, 1G Ethernet, M.2 E-key for WiFi/BT, and
BeagleBone expansion headers.
This board family can be indentified by the BBONEAI-64-B0 in the
at24 eeprom:
[aa 55 33 ee 01 37 00 10 2e 00 42 42 4f 4e 45 41 |.U3..7....BBONEA|]
[49 2d 36 34 2d 42 30 2d 00 00 42 30 30 30 37 38 |I-64-B0-..B00078|]
Baseline of the devicetree is from v6.6-rc1
https://beagleboard.org/ai-64https://git.beagleboard.org/beagleboard/beaglebone-ai-64
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Move the omap3 beagle to the beagle vendor folder representing
BeagleBoard.org platforms.
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Move beagleplay support away from ti/am62x to it's own beagle vendor
folder.
This forms the starting point for new beagle platforms added under it's
own board vendor folder.
As part of this create all the associated files with a bare minimum
beagleplay.c file.
Suggested-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
[trini: Update k3-binman.dtsi to use full path to scheme.yaml now]
Signed-off-by: Tom Rini <trini@konsulko.com>
With the upcoming folder separation, there is no further need to depend
on am625-binman.dtsi. Duplicate the existing definitions to u-boot.dtsi
and r5.dts as appropriate.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Commit 5019170970 ("arch: arm: mach-k3: j721e: add support for UDA
FS") introduced basic UDA FS support, however, we can Take approach
similar to commit 0f1c1e8b36 ("arm: mach-k3: am625: Add support for
UDA FS"). While boot partition support with EMMC boot is useful, it is
constrained by the size of boot hardware partition itself.
In the case of K3 devices, tispl images can contain OP-TEE images that
can substantially vary in size and the u-boot image itself can vary over
time as we enable various features.
So use the CSD information in the case of EMMC_BOOT configuration being
enabled to pick boot partition or UDA FS mode operation to pick.
If EMMC_BOOT is disabled, then depend on filesystem configuration to
pick data from UDA.
Signed-off-by: Nishanth Menon <nm@ti.com>
Enable SOC_K3_J721E_J7200 when board is J7200 EVM - this allows us to
differentiate J7200 platform cleanly in board independent codebase.
Signed-off-by: Nishanth Menon <nm@ti.com>
J7200 shares quite a few characteristics with J721E. However a few sets
are different. Introduce a Kconfig to differentiate the two to allow for
new boards to be introduced in a seamless manner.
Signed-off-by: Nishanth Menon <nm@ti.com>
This file is used to emulate customer keys on TI development board
ecosystems, move it out of board/ directory and into mach-k3. And
change the relative paths to absolute paths in the binman paths.
While at it, drop the reference in verdin-binman file which is
redundant.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Manorit Chawdhry <m-chawdhry@ti.com>
This file is common for all of K3, move it out of board/ directory and
into mach-k3. And change the relative paths to absolute paths in the
binman paths.
While at it, drop the reference in verdin-binman file which is
redundant.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Andrew Davis <afd@ti.com>
SYSFW is only ever loaded by the R5 core, move the code into that
directory. While here also move the related Kconfig symbols.
Signed-off-by: Andrew Davis <afd@ti.com>
The kconfig option SPL means this build supports SPL but not that
this build is SPL, nor that this build is the SPL running on R5.
For options that are for R5 SPL use CPU_V7R.
Signed-off-by: Andrew Davis <afd@ti.com>
This makes it clear these are only to be used by the R5 builds of SPL.
And this will be used to later more cleanly split the two builds.
Signed-off-by: Andrew Davis <afd@ti.com>
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.
To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.
Signed-off-by: Andrew Davis <afd@ti.com>
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.
To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.
Signed-off-by: Andrew Davis <afd@ti.com>
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.
To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.
Signed-off-by: Andrew Davis <afd@ti.com>
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.
To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.
Signed-off-by: Andrew Davis <afd@ti.com>
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.
To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.
Signed-off-by: Andrew Davis <afd@ti.com>
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.
To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.
Signed-off-by: Andrew Davis <afd@ti.com>
This reverts commit 6cdf6b7a34. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
This reverts commit 836b8d4b20. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
This reverts commit c1da6fdb5c. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
This fixes a regression in the eMMC fast boot mode case where the buffer
was missing 464 bytes.
The code figures out how many bytes must at least be fetched to honor
the current read, rounds that up to the ss->pagesize [which is a no-op
in the USB download case because that has ->pagesize==1], fetches that
many bytes, but then recorded the original upper bound as the new end of
the valid data. However, this did not take into account the rounding up
to the ss->pagesize. Fix this by recording the actual bytes downloaded.
Fixes: 4b4472438f ("imx: spl_imx_romapi: avoid tricky use of spl_load_simple_fit() to get full FIT size")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Aligning addresses and sizes causes overhead which is unnecessary when we
are not loading from block devices. Remove bl_len when it is not needed.
For example, on iot2050 we save 144 bytes with this patch (once the rest of
this series is applied):
add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-144 (-144)
Function old new delta
spl_load_simple_fit 920 904 -16
load_simple_fit 496 444 -52
spl_spi_load_image 384 308 -76
Total: Before=87431, After=87287, chg -0.16%
We use panic() instead of BUILD_BUG_ON in spl_set_bl_len because we still
need to be able to compile it for things like mmc_load_image_raw_sector,
even if that function will not be used.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For filesystems, filename serves the same purpose as priv. However,
spl_load_fit_image also uses it to determine whether to use a DMA-aligned
buffer. This is beneficial for FAT, which uses a bounce-buffer if the
destination is not DMA-aligned. However, this is unnecessary now that
filesystems set bl_len to ARCH_DMA_MINALIGN instead. With this done, we can
remove filename entirely.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simplify things a bit for callers of spl_load_info->read by refactoring it
to use units of bytes instead of bl_len. This generally simplifies the
logic, as MMC is the only loader which actually works in sectors. It will
also allow further refactoring to remove the special-case handling of
filename. spl_load_legacy_img already works in units of bytes (oops) so it
doesn't need to be changed.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove NULL assignments to fields in spl_load_info when .load doesn't
reference these fields. This can result in more efficient code. filename
must stay even if it is unused, since load_simple_fit uses it.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Several AT91 boards are quite close to their SPL size limit. For example,
sama5d27_wlsom1_ek_mmc is just 173 bytes short of its limit and doesn't
even fit with older GCCs.
All AT91 processors should have thumb support. Enable SYS_THUMB_BUILD. This
shrinks SPL by around 30%.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add initial support for STM32MP2 SoCs family.
SoCs information are available here :
https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html
Migrate all MP1 related code into stm32mp1/ directory
Create stm32mp2 directory dedicated for STM32MP2 SoCs.
Common code to MP1, MP13 and MP25 is kept into
arch/arm/mach-stm32/mach-stm32mp directory :
- boot_params.c
- bsec
- cmd_stm32key
- cmd_stm32prog
- dram_init.c
- syscon.c
- ecdsa_romapi.c
For STM32MP2, it also :
- adds memory region description needed for ARMv8 MMU.
- enables early data cache before relocation.
During the transition before/after relocation, the MMU, initially setup
at the beginning of DDR, must be setup again at a correct address after
relocation. This is done in enables_caches() by disabling cache, force
arch.tlb_fillptr to NULL which will force the MMU to be setup again but
with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been
updated after relocation in arm_reserve_mmu().
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC,
with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC,
SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Sync device tree with kernel v6.6-rc1.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
When building with AARCH64 defconfig, we got warnings, fix them.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Limit DDR usage under 4GB boundary on STM32MP regardless of
memory size declared in device tree.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
When building with AARCH64 defconfig, we got warnings for debug
message
- format '%x' expects argument of type 'unsigned int',
but argument 3 has type 'size_t' {aka 'long unsigned int'}).
- format '%lx' expects argument of type 'long unsigned int',
but argument 2 has type 'phys_addr_t' {aka 'long long unsigned
int'}
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
In case there is no RAM driver retrieve RAM size from DT as fallback.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This fixes the following compilation error in ARM64:
arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’:
arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function)
59 | mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
| ^~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The sysreset uclass unconditionally provides a definition of the
reset_cpu() function. So does the exynos soc code. Fix the build with
SYSRESET enabled by omitting the function from the soc code in that
case. The code still needs to be kept around for use in SPL.
This commit was inspired by commit 6e19dc84c1 ("sunxi: Avoid duplicate
reset_cpu with SYSRESET enabled").
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arch/arm/include/asm/arch/gpio.h relies on definitions from cpu.h.
Include it explicitly in gpio.h. Otherwise next build error may occur:
In file included from ./arch/arm/include/asm/gpio.h:7,
from include/cros_ec.h:14,
from board/samsung/common/board.c:8:
./arch/arm/include/asm/arch/gpio.h:1357:4:
error: 'EXYNOS4_GPIO_PART1_BASE' undeclared here
(not in a function); did you mean 'EXYNOS4_GPIO_MAX_PORT'?
1357 | { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
| ^~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
samsung_get_base_swreset() is called in soc.c, but corresponding header
with its prototype is not included. Fix this to avoid possible build
errors.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC and new orangepi
zero3 with H618.
The compatibility with T507 is not yet complete, because there
is difference in the phy_init array.
The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
found on the NOR SPI from the Orangepi Zero 3 4GB.
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Tested-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
The original H616 DDR3 ODT configuration code wrote board specific values
into a sequence of paired registers.
For LPDDR3 support we needed to special-case one group of registers,
because for that DRAM type we need to write 0 into the lower register of
each pair. That already made the code less readable.
LPDDR4 support will make things even messier, so let's refactor that
code now: We allow to write different values into the lower and upper
half of each pair. The masking is moved into a macro, and use in each
write statement.
The effect is not as obvious yet, as we don't need the full flexibility at
the moment, but the motivation will become clearer with LPDDR4 support.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Mikhail Kalashnikov <iuncuim@gmail.com>
