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Prepare v2024.01-rc4

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Merge tag 'v2024.01-rc4' into next

Prepare v2024.01-rc4

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# gpg: Signature made Mon 04 Dec 2023 01:47:24 PM EST
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]
This commit is contained in:
Tom Rini 2023-12-04 21:39:57 -05:00
commit d379150621
23 changed files with 171 additions and 102 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
MAINTAINERS
View file

@ -667,11 +667,14 @@ F: drivers/video/sunxi/
F: tools/sunxi*
ARM TEGRA
M: Tom Warren <twarren@nvidia.com>
M: Thierry Reding <treding@nvidia.com>
M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-tegra.git
F: arch/arm/mach-tegra/
F: arch/arm/dts/tegra*
F: arch/arm/include/asm/arch-tegra*/
F: arch/arm/mach-tegra/
F: drivers/*/tegra*
ARM TI
M: Tom Rini <trini@konsulko.com>

2
Makefile
View file

@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*

18
arch/arm/dts/r8a779g0-u-boot.dtsi
View file

@ -7,20 +7,10 @@
#include "r8a779x-u-boot.dtsi"
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a779g0-rpc-if", "renesas,rcar-gen4-rpc-if";
reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 629>;
bank-width = <2>;
num-cs = <1>;
status = "disabled";
};
};
&rpc {
reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
bank-width = <2>;
num-cs = <1>;
};
&extalr_clk {

2
arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
View file

@ -28,7 +28,7 @@
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <40000000>;
status = "okay";
status = "disabled";
spi-flash@0 {
#address-cells = <1>;

3
arch/arm/mach-exynos/include/mach/gpio.h
View file

@ -8,6 +8,9 @@
#define __ASM_ARCH_GPIO_H
#ifndef __ASSEMBLY__
#include <asm/arch/cpu.h>
struct s5p_gpio_bank {
unsigned int con;
unsigned int dat;

3
arch/arm/mach-exynos/soc.c
View file

@ -9,6 +9,7 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/cpu.h>
#ifdef CONFIG_TARGET_ESPRESSO7420
/*
@ -20,12 +21,14 @@ extern void _main(void);
void *secondary_boot_addr = (void *)_main;
#endif /* CONFIG_TARGET_ESPRESSO7420 */
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
#ifdef CONFIG_CPU_V7A
writel(0x1, samsung_get_base_swreset());
#endif
}
#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)

14
board/samsung/axy17lte/Kconfig
View file

@ -1,11 +1,3 @@
config SYS_CONFIG_NAME
string "Board configuration name"
default "exynos78x0-common.h"
help
This option contains information about board configuration name.
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
if TARGET_A5Y17LTE
config SYS_BOARD
default "axy17lte"
@ -16,7 +8,7 @@ config SYS_VENDOR
default "samsung"
config SYS_CONFIG_NAME
default "a5y17lte"
default "exynos78x0-common"
config EXYNOS7880
bool "Exynos 7880 SOC support"
@ -33,7 +25,7 @@ config SYS_VENDOR
default "samsung"
config SYS_CONFIG_NAME
default "a5y17lte"
default "exynos78x0-common"
config EXYNOS7880
bool "Exynos 7880 SOC support"
@ -50,7 +42,7 @@ config SYS_VENDOR
default "samsung"
config SYS_CONFIG_NAME
default "a3y17lte"
default "exynos78x0-common"
config EXYNOS7870
bool "Exynos 7870 SOC support"

7
common/usb_hub.c
View file

@ -395,6 +395,13 @@ int usb_hub_port_connect_change(struct usb_device *dev, int port)
break;
}
/*
* USB 2.0 7.1.7.5: devices must be able to accept a SetAddress()
* request (refer to Section 11.24.2 and Section 9.4 respectively)
* after the reset recovery time 10 ms
*/
mdelay(10);
#if CONFIG_IS_ENABLED(DM_USB)
struct udevice *child;

22
common/usb_storage.c
View file

@ -102,6 +102,7 @@ struct us_data {
trans_reset transport_reset; /* reset routine */
trans_cmnd transport; /* transport routine */
unsigned short max_xfer_blk; /* maximum transfer blocks */
bool cmd12; /* use 12-byte commands (RBC/UFI) */
};
#if !CONFIG_IS_ENABLED(BLK)
@ -359,7 +360,7 @@ static void usb_show_srb(struct scsi_cmd *pccb)
{
int i;
printf("SRB: len %d datalen 0x%lX\n ", pccb->cmdlen, pccb->datalen);
for (i = 0; i < 12; i++)
for (i = 0; i < pccb->cmdlen; i++)
printf("%02X ", pccb->cmd[i]);
printf("\n");
}
@ -898,7 +899,7 @@ do_retry:
psrb->cmd[4] = 18;
psrb->datalen = 18;
psrb->pdata = &srb->sense_buf[0];
psrb->cmdlen = 12;
psrb->cmdlen = us->cmd12 ? 12 : 6;
/* issue the command */
result = usb_stor_CB_comdat(psrb, us);
debug("auto request returned %d\n", result);
@ -999,7 +1000,7 @@ static int usb_inquiry(struct scsi_cmd *srb, struct us_data *ss)
srb->cmd[1] = srb->lun << 5;
srb->cmd[4] = 36;
srb->datalen = 36;
srb->cmdlen = 12;
srb->cmdlen = ss->cmd12 ? 12 : 6;
i = ss->transport(srb, ss);
debug("inquiry returns %d\n", i);
if (i == 0)
@ -1024,7 +1025,7 @@ static int usb_request_sense(struct scsi_cmd *srb, struct us_data *ss)
srb->cmd[4] = 18;
srb->datalen = 18;
srb->pdata = &srb->sense_buf[0];
srb->cmdlen = 12;
srb->cmdlen = ss->cmd12 ? 12 : 6;
ss->transport(srb, ss);
debug("Request Sense returned %02X %02X %02X\n",
srb->sense_buf[2], srb->sense_buf[12],
@ -1042,7 +1043,7 @@ static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss)
srb->cmd[0] = SCSI_TST_U_RDY;
srb->cmd[1] = srb->lun << 5;
srb->datalen = 0;
srb->cmdlen = 12;
srb->cmdlen = ss->cmd12 ? 12 : 6;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) {
ss->flags |= USB_READY;
return 0;
@ -1074,7 +1075,7 @@ static int usb_read_capacity(struct scsi_cmd *srb, struct us_data *ss)
srb->cmd[0] = SCSI_RD_CAPAC;
srb->cmd[1] = srb->lun << 5;
srb->datalen = 8;
srb->cmdlen = 12;
srb->cmdlen = ss->cmd12 ? 12 : 10;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
return 0;
} while (retry--);
@ -1094,7 +1095,7 @@ static int usb_read_10(struct scsi_cmd *srb, struct us_data *ss,
srb->cmd[5] = ((unsigned char) (start)) & 0xff;
srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
srb->cmd[8] = (unsigned char) blocks & 0xff;
srb->cmdlen = 12;
srb->cmdlen = ss->cmd12 ? 12 : 10;
debug("read10: start %lx blocks %x\n", start, blocks);
return ss->transport(srb, ss);
}
@ -1111,7 +1112,7 @@ static int usb_write_10(struct scsi_cmd *srb, struct us_data *ss,
srb->cmd[5] = ((unsigned char) (start)) & 0xff;
srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
srb->cmd[8] = (unsigned char) blocks & 0xff;
srb->cmdlen = 12;
srb->cmdlen = ss->cmd12 ? 12 : 10;
debug("write10: start %lx blocks %x\n", start, blocks);
return ss->transport(srb, ss);
}
@ -1417,6 +1418,11 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,
printf("Sorry, protocol %d not yet supported.\n", ss->subclass);
return 0;
}
/* UFI uses 12-byte commands (like RBC, unlike SCSI) */
if (ss->subclass == US_SC_UFI)
ss->cmd12 = true;
if (ss->ep_int) {
/* we had found an interrupt endpoint, prepare irq pipe
* set up the IRQ pipe and handler

1
configs/a3y17lte_defconfig
View file

@ -1,5 +1,4 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=26000000
CONFIG_ARCH_EXYNOS=y

1
configs/a5y17lte_defconfig
View file

@ -1,5 +1,4 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=26000000
CONFIG_ARCH_EXYNOS=y

1
configs/a7y17lte_defconfig
View file

@ -1,5 +1,4 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=26000000
CONFIG_ARCH_EXYNOS=y

2
doc/develop/release_cycle.rst
View file

@ -70,7 +70,7 @@ For the next scheduled release, release candidates were made on::
* U-Boot v2024.01-rc3 was released on Mon 20 November 2023.
.. * U-Boot v2024.01-rc4 was released on Mon 04 December 2023.
* U-Boot v2024.01-rc4 was released on Mon 04 December 2023.
.. * U-Boot v2024.01-rc5 was released on Mon 18 December 2023.

5
drivers/clk/exynos/clk-pll.h
View file

@ -5,4 +5,9 @@
* Thomas Abraham <thomas.ab@samsung.com>
*/
#ifndef __EXYNOS_CLK_PLL_H
#define __EXYNOS_CLK_PLL_H
unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
#endif /* __EXYNOS_CLK_PLL_H */

79
drivers/serial/serial_s5p.c
View file

@ -7,7 +7,6 @@
* based on drivers/serial/s3c64xx.c
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
@ -21,32 +20,39 @@
#include <serial.h>
#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
enum {
PORT_S5P = 0,
PORT_S5L
};
#define UFCON_FIFO_EN BIT(0)
#define UFCON_RX_FIFO_RESET BIT(1)
#define UMCON_RESET_VAL 0x0
#define ULCON_WORD_8_BIT 0x3
#define UCON_RX_IRQ_OR_POLLING BIT(0)
#define UCON_TX_IRQ_OR_POLLING BIT(2)
#define UCON_RX_ERR_IRQ_EN BIT(6)
#define UCON_TX_IRQ_LEVEL BIT(9)
#define S5L_RX_FIFO_COUNT_SHIFT 0
#define S5L_RX_FIFO_COUNT_MASK (0xf << S5L_RX_FIFO_COUNT_SHIFT)
#define S5L_RX_FIFO_FULL (1 << 8)
#define S5L_RX_FIFO_FULL BIT(8)
#define S5L_TX_FIFO_COUNT_SHIFT 4
#define S5L_TX_FIFO_COUNT_MASK (0xf << S5L_TX_FIFO_COUNT_SHIFT)
#define S5L_TX_FIFO_FULL (1 << 9)
#define S5L_TX_FIFO_FULL BIT(9)
#define S5P_RX_FIFO_COUNT_SHIFT 0
#define S5P_RX_FIFO_COUNT_MASK (0xff << S5P_RX_FIFO_COUNT_SHIFT)
#define S5P_RX_FIFO_FULL (1 << 8)
#define S5P_RX_FIFO_FULL BIT(8)
#define S5P_TX_FIFO_COUNT_SHIFT 16
#define S5P_TX_FIFO_COUNT_MASK (0xff << S5P_TX_FIFO_COUNT_SHIFT)
#define S5P_TX_FIFO_FULL (1 << 24)
#define S5P_TX_FIFO_FULL BIT(24)
/* Information about a serial port */
struct s5p_serial_plat {
struct s5p_uart *reg; /* address of registers in physical memory */
u8 reg_width; /* register width */
u8 port_id; /* uart port number */
struct s5p_uart *reg; /* address of registers in physical memory */
u8 reg_width; /* register width */
u8 port_id; /* uart port number */
u8 rx_fifo_count_shift;
u8 tx_fifo_count_shift;
u32 rx_fifo_count_mask;
@ -59,7 +65,7 @@ struct s5p_serial_plat {
* The coefficient, used to calculate the baudrate on S5P UARTs is
* calculated as
* C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
* however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
* however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
* 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
*/
static const int udivslot[] = {
@ -83,13 +89,15 @@ static const int udivslot[] = {
static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
{
/* enable FIFOs, auto clear Rx FIFO */
writel(0x3, &uart->ufcon);
writel(0, &uart->umcon);
/* 8N1 */
writel(0x3, &uart->ulcon);
/* Enable FIFOs, auto clear Rx FIFO */
writel(UFCON_FIFO_EN | UFCON_RX_FIFO_RESET, &uart->ufcon);
/* No auto flow control, disable nRTS signal */
writel(UMCON_RESET_VAL, &uart->umcon);
/* 8N1, no parity bit */
writel(ULCON_WORD_8_BIT, &uart->ulcon);
/* No interrupts, no DMA, pure polling */
writel(0x245, &uart->ucon);
writel(UCON_RX_IRQ_OR_POLLING | UCON_TX_IRQ_OR_POLLING |
UCON_RX_ERR_IRQ_EN | UCON_TX_IRQ_LEVEL, &uart->ucon);
}
static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, u8 reg_width,
@ -118,7 +126,7 @@ int s5p_serial_setbrg(struct udevice *dev, int baudrate)
#if IS_ENABLED(CONFIG_CLK_EXYNOS) || IS_ENABLED(CONFIG_ARCH_APPLE)
struct clk clk;
u32 ret;
int ret;
ret = clk_get_by_index(dev, 1, &clk);
if (ret < 0)
@ -213,16 +221,13 @@ static int s5p_serial_of_to_plat(struct udevice *dev)
{
struct s5p_serial_plat *plat = dev_get_plat(dev);
const ulong port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
plat->reg = dev_read_addr_ptr(dev);
if (!plat->reg)
return -EINVAL;
plat->reg = (struct s5p_uart *)addr;
plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"id", dev_seq(dev));
plat->port_id = dev_read_u8_default(dev, "id", dev_seq(dev));
if (port_type == PORT_S5L) {
plat->rx_fifo_count_shift = S5L_RX_FIFO_COUNT_SHIFT;
@ -244,10 +249,10 @@ static int s5p_serial_of_to_plat(struct udevice *dev)
}
static const struct dm_serial_ops s5p_serial_ops = {
.putc = s5p_serial_putc,
.pending = s5p_serial_pending,
.getc = s5p_serial_getc,
.setbrg = s5p_serial_setbrg,
.putc = s5p_serial_putc,
.pending = s5p_serial_pending,
.getc = s5p_serial_getc,
.setbrg = s5p_serial_setbrg,
};
static const struct udevice_id s5p_serial_ids[] = {
@ -257,13 +262,13 @@ static const struct udevice_id s5p_serial_ids[] = {
};
U_BOOT_DRIVER(serial_s5p) = {
.name = "serial_s5p",
.id = UCLASS_SERIAL,
.of_match = s5p_serial_ids,
.of_to_plat = s5p_serial_of_to_plat,
.name = "serial_s5p",
.id = UCLASS_SERIAL,
.of_match = s5p_serial_ids,
.of_to_plat = s5p_serial_of_to_plat,
.plat_auto = sizeof(struct s5p_serial_plat),
.probe = s5p_serial_probe,
.ops = &s5p_serial_ops,
.probe = s5p_serial_probe,
.ops = &s5p_serial_ops,
};
#endif
@ -291,10 +296,12 @@ static inline void _debug_uart_putc(int ch)
struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
#if IS_ENABLED(CONFIG_ARCH_APPLE)
while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL);
while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL)
;
writel(ch, &uart->utxh);
#else
while (readl(&uart->ufstat) & S5P_TX_FIFO_FULL);
while (readl(&uart->ufstat) & S5P_TX_FIFO_FULL)
;
writeb(ch, &uart->utxh);
#endif
}

1
drivers/usb/dwc3/dwc3-generic.c
View file

@ -610,6 +610,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "qcom,dwc3" },
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
{ .compatible = "fsl,imx8mq-dwc3" },

2
drivers/usb/host/Kconfig
View file

@ -90,7 +90,7 @@ config USB_XHCI_OMAP
config USB_XHCI_PCI
bool "Support for PCI-based xHCI USB controller"
depends on DM_USB
depends on DM_USB && PCI
default y if X86
help
Enables support for the PCI-based xHCI controller.

72
drivers/usb/host/xhci-ring.c
View file

@ -202,6 +202,7 @@ static dma_addr_t queue_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring,
bool more_trbs_coming, unsigned int *trb_fields)
{
struct xhci_generic_trb *trb;
dma_addr_t addr;
int i;
trb = &ring->enqueue->generic;
@ -211,9 +212,11 @@ static dma_addr_t queue_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring,
xhci_flush_cache((uintptr_t)trb, sizeof(struct xhci_generic_trb));
addr = xhci_trb_virt_to_dma(ring->enq_seg, (union xhci_trb *)trb);
inc_enq(ctrl, ring, more_trbs_coming);
return xhci_trb_virt_to_dma(ring->enq_seg, (union xhci_trb *)trb);
return addr;
}
/**
@ -243,7 +246,8 @@ static int prepare_ring(struct xhci_ctrl *ctrl, struct xhci_ring *ep_ring,
puts("WARN waiting for error on ep to be cleared\n");
return -EINVAL;
case EP_STATE_HALTED:
puts("WARN halted endpoint, queueing URB anyway.\n");
puts("WARN endpoint is halted\n");
return -EINVAL;
case EP_STATE_STOPPED:
case EP_STATE_RUNNING:
debug("EP STATE RUNNING.\n");
@ -466,7 +470,8 @@ union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected)
continue;
type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
if (type == expected)
if (type == expected ||
(expected == TRB_NONE && type != TRB_PORT_STATUS))
return event;
if (type == TRB_PORT_STATUS)
@ -492,8 +497,9 @@ union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected)
if (expected == TRB_TRANSFER)
return NULL;
printf("XHCI timeout on event type %d... cannot recover.\n", expected);
BUG();
printf("XHCI timeout on event type %d...\n", expected);
return NULL;
}
/*
@ -511,6 +517,9 @@ static void reset_ep(struct usb_device *udev, int ep_index)
printf("Resetting EP %d...\n", ep_index);
xhci_queue_command(ctrl, 0, udev->slot_id, ep_index, TRB_RESET_EP);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
if (!event)
return;
field = le32_to_cpu(event->trans_event.flags);
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
xhci_acknowledge_event(ctrl);
@ -519,6 +528,9 @@ static void reset_ep(struct usb_device *udev, int ep_index)
(void *)((uintptr_t)ring->enqueue | ring->cycle_state));
xhci_queue_command(ctrl, addr, udev->slot_id, ep_index, TRB_SET_DEQ);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
if (!event)
return;
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
event->event_cmd.status)) != COMP_SUCCESS);
@ -538,29 +550,49 @@ static void abort_td(struct usb_device *udev, int ep_index)
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
struct xhci_ring *ring = ctrl->devs[udev->slot_id]->eps[ep_index].ring;
union xhci_trb *event;
xhci_comp_code comp;
trb_type type;
u64 addr;
u32 field;
xhci_queue_command(ctrl, 0, udev->slot_id, ep_index, TRB_STOP_RING);
event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
field = le32_to_cpu(event->trans_event.flags);
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
!= COMP_STOP)));
xhci_acknowledge_event(ctrl);
event = xhci_wait_for_event(ctrl, TRB_NONE);
if (!event)
return;
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
event->event_cmd.status)) != COMP_SUCCESS);
type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
if (type == TRB_TRANSFER) {
field = le32_to_cpu(event->trans_event.flags);
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
!= COMP_STOP)));
xhci_acknowledge_event(ctrl);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
if (!event)
return;
type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
} else {
printf("abort_td: Expected a TRB_TRANSFER TRB first\n");
}
comp = GET_COMP_CODE(le32_to_cpu(event->event_cmd.status));
BUG_ON(type != TRB_COMPLETION ||
TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || (comp != COMP_SUCCESS && comp
!= COMP_CTX_STATE));
xhci_acknowledge_event(ctrl);
addr = xhci_trb_virt_to_dma(ring->enq_seg,
(void *)((uintptr_t)ring->enqueue | ring->cycle_state));
xhci_queue_command(ctrl, addr, udev->slot_id, ep_index, TRB_SET_DEQ);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
if (!event)
return;
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
event->event_cmd.status)) != COMP_SUCCESS);
@ -644,6 +676,14 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index);
/*
* If the endpoint was halted due to a prior error, resume it before
* the next transfer. It is the responsibility of the upper layer to
* have dealt with whatever caused the error.
*/
if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == EP_STATE_HALTED)
reset_ep(udev, ep_index);
ring = virt_dev->eps[ep_index].ring;
/*
* How much data is (potentially) left before the 64KB boundary?

9
drivers/usb/host/xhci.c
View file

@ -451,6 +451,9 @@ static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
xhci_queue_command(ctrl, in_ctx->dma, udev->slot_id, 0,
ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
if (!event)
return -ETIMEDOUT;
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id);
@ -647,6 +650,9 @@ static int xhci_address_device(struct usb_device *udev, int root_portnr)
xhci_queue_command(ctrl, virt_dev->in_ctx->dma,
slot_id, 0, TRB_ADDR_DEV);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
if (!event)
return -ETIMEDOUT;
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
@ -722,6 +728,9 @@ static int _xhci_alloc_device(struct usb_device *udev)
xhci_queue_command(ctrl, 0, 0, 0, TRB_ENABLE_SLOT);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
if (!event)
return -ETIMEDOUT;
BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
!= COMP_SUCCESS);

1
drivers/watchdog/s5p_wdt.c
View file

@ -6,6 +6,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/watchdog.h>
#define PRESCALER_VAL 255

3
drivers/watchdog/wdt-uclass.c
View file

@ -7,6 +7,7 @@
#include <common.h>
#include <cyclic.h>
#include <div64.h>
#include <dm.h>
#include <errno.h>
#include <hang.h>
@ -141,7 +142,7 @@ int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
printf("WDT: Started %s with%s servicing %s (%ds timeout)\n",
dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out",
str, priv->timeout);
str, (u32)lldiv(timeout_ms, 1000));
}
return ret;

2
include/usb/xhci.h
View file

@ -901,6 +901,8 @@ union xhci_trb {
/* TRB type IDs */
typedef enum {
/* reserved, used as a software sentinel */
TRB_NONE = 0,
/* bulk, interrupt, isoc scatter/gather, and control data stage */
TRB_NORMAL = 1,
/* setup stage for control transfers */

16
lib/efi_loader/efi_smbios.c
View file

@ -49,25 +49,27 @@ efi_status_t efi_smbios_register(void)
static int install_smbios_table(void)
{
ulong addr;
void *buf;
u64 addr;
efi_status_t ret;
if (!IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE) || IS_ENABLED(CONFIG_X86))
return 0;
/* Align the table to a 4KB boundary to keep EFI happy */
buf = memalign(SZ_4K, TABLE_SIZE);
if (!buf)
addr = SZ_4G;
ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
EFI_RUNTIME_SERVICES_DATA,
efi_size_in_pages(TABLE_SIZE), &addr);
if (ret != EFI_SUCCESS)
return log_msg_ret("mem", -ENOMEM);
addr = map_to_sysmem(buf);
addr = map_to_sysmem((void *)(uintptr_t)addr);
if (!write_smbios_table(addr)) {
log_err("Failed to write SMBIOS table\n");
return log_msg_ret("smbios", -EINVAL);
}
/* Make a note of where we put it */
log_debug("SMBIOS tables written to %lx\n", addr);
log_debug("SMBIOS tables written to %llx\n", addr);
gd->arch.smbios_start = addr;
return 0;