mirror of
https://github.com/AsahiLinux/u-boot
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arm: dts: k3-am68*: Sync with kernel v6.7-rc1
Sync devicetree with kernel v6.7-rc1 Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
This commit is contained in:
Manorit Chawdhry
Tom Rini
parent
7e7d2bfb2c
commit
2fadd62fe6
3 changed files with 265 additions and 1 deletions
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@ -553,3 +553,59 @@
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};
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};
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};
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&serdes_ln_ctrl {
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idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
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<J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
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};
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&serdes_refclk {
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clock-frequency = <100000000>;
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};
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&serdes0 {
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status = "okay";
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serdes0_pcie_link: phy@0 {
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reg = <0>;
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cdns,num-lanes = <2>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_PCIE>;
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resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
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};
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serdes0_usb_link: phy@2 {
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status = "okay";
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reg = <2>;
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cdns,num-lanes = <1>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_USB3>;
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resets = <&serdes_wiz0 3>;
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};
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};
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&pcie1_rc {
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status = "okay";
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reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
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phys = <&serdes0_pcie_link>;
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phy-names = "pcie-phy";
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num-lanes = <2>;
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};
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&usb_serdes_mux {
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idle-states = <0>; /* USB0 to SERDES lane 2 */
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};
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&usbss0 {
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status = "okay";
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pinctrl-0 = <&main_usbss0_pins_default>;
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pinctrl-names = "default";
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ti,vbus-divider;
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};
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&usb0 {
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dr_mode = "host";
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maximum-speed = "super-speed";
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phys = <&serdes0_usb_link>;
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phy-names = "cdns3,usb3-phy";
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};
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@ -25,6 +25,108 @@
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reg = <0x00 0x9e800000 0x00 0x01800000>;
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no-map;
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};
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mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0100000 0x00 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5100000 0x00 0xf00000>;
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no-map;
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};
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c71_0_dma_memory_region: c71-dma-memory@a6000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6000000 0x00 0x100000>;
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no-map;
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};
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c71_0_memory_region: c71-memory@a6100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6100000 0x00 0xf00000>;
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no-map;
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};
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c71_1_dma_memory_region: c71-dma-memory@a7000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7000000 0x00 0x100000>;
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no-map;
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};
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c71_1_memory_region: c71-memory@a7100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7100000 0x00 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: ipc-memories@a8000000 {
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reg = <0x00 0xa8000000 0x00 0x01c00000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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};
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@ -49,3 +151,109 @@
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reg = <0x51>;
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};
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};
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&mailbox0_cluster0 {
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status = "okay";
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster1 {
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status = "okay";
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interrupts = <432>;
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster2 {
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status = "okay";
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interrupts = <428>;
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mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster4 {
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status = "okay";
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interrupts = <420>;
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mbox_c71_0: mbox-c71-0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_c71_1: mbox-c71-1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mcu_r5fss0_core0 {
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mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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};
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&mcu_r5fss0_core1 {
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mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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};
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&main_r5fss0_core0 {
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mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
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memory-region = <&main_r5fss0_core0_dma_memory_region>,
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<&main_r5fss0_core0_memory_region>;
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};
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&main_r5fss0_core1 {
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mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
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memory-region = <&main_r5fss0_core1_dma_memory_region>,
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<&main_r5fss0_core1_memory_region>;
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};
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&main_r5fss1_core0 {
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mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
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memory-region = <&main_r5fss1_core0_dma_memory_region>,
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<&main_r5fss1_core0_memory_region>;
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};
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&main_r5fss1_core1 {
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mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
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memory-region = <&main_r5fss1_core1_dma_memory_region>,
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<&main_r5fss1_core1_memory_region>;
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};
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&c71_0 {
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status = "okay";
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mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
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memory-region = <&c71_0_dma_memory_region>,
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<&c71_0_memory_region>;
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};
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&c71_1 {
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status = "okay";
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mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
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memory-region = <&c71_1_dma_memory_region>,
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<&c71_1_memory_region>;
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};
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@ -111,7 +111,7 @@
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#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
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#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
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#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
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#define J721S2_SERDES0_LANE2_USB_SWAP 0x2
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#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
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#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0
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