mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-20 22:52:00 +00:00
Introduce STM32MP2 SoCs family support
Add STM32MP257F-EV1 board -----BEGIN PGP SIGNATURE----- iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmVR87YcHHBhdHJpY2Uu Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/ph+cD/0YFWkURt5TASxw49MB EE8PHjuWFPRVhR/lBX0vUxJRfltbmbJOKeGSZZeRW7LGApDVKVxKdrk2gGeLekJk L4i5KHBCDts35v3xfFhfxBYMYgXN7KiCo5Cv49b6ibxNeAUt/zKM1+CmLQWW+O8J 60LhATQduTHE9/QYiZYJusO4ma+HOSlCgbE+4jwj19Y3DaridBZ0/P+yVarjB6Mo j/cpGkQ9YQekx0gD6OJjd13kU8LJ5/qaKpMhLhU5HwnxvSuosy1JX8r9gNA2x5yt EqscRJBnQE2pKCIekzETX347Es/vhcYM6YFIGyY40bDT83on2cgxFm4xKAZ4RdNb uT4G24AueIiyT3Rpd4vGv9cWuSksSiSxcAa4ouMGAxnNyDwJaJ7HYGqnQ4yA8doR VbtwK1bT6LutgMn7ymFAiDEYaeplhF4ybxvXZJT9/qjeMXfwhBGF9UYqQNDUCDah 8ljbA0jIIV1SIVgYL4jPCwby9D53GGVtQ06SVXiJRhHgVJnkQaojByYU7xS8xrqS 1j1Ccy9rmpixS4pt589Q1dKoPGiUVgh9Z58PpR9yrCWzIokIL0WTMttG0PkSUJYJ VpNuQbsKK3LZ01xbhVpZWauOoKTfK2Fe6XsF04WCP+cK8rM+uV6DeE+bqhnadj/M CHJscGOKvhIR3jkF10F5mMJ1RA== =E2zX -----END PGP SIGNATURE----- Merge tag 'u-boot-stm32-20231113' of https://source.denx.de/u-boot/custodians/u-boot-stm into next Introduce STM32MP2 SoCs family support Add STM32MP257F-EV1 board [trini: Adjust some includes] Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
commit
be0724601a
48 changed files with 1595 additions and 108 deletions
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@ -1944,7 +1944,7 @@ config ARCH_STM32MP
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select REGMAP
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select SYSCON
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select SYSRESET
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select SYS_THUMB_BUILD
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select SYS_THUMB_BUILD if !ARM64
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imply SPL_SYSRESET
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imply CMD_DM
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imply CMD_POWEROFF
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@ -1352,6 +1352,9 @@ dtb-$(CONFIG_STM32MP15x) += \
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stm32mp15xx-dhcor-drc-compact.dtb \
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stm32mp15xx-dhcor-testbench.dtb
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dtb-$(CONFIG_STM32MP25X) += \
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stm32mp257f-ev1.dtb
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dtb-$(CONFIG_SOC_K3_AM654) += \
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k3-am654-base-board.dtb \
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k3-am654-r5-base-board.dtb \
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38
arch/arm/dts/stm32mp25-pinctrl.dtsi
Normal file
38
arch/arm/dts/stm32mp25-pinctrl.dtsi
Normal file
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@ -0,0 +1,38 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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&pinctrl {
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usart2_pins_a: usart2-0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
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bias-disable;
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};
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};
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usart2_idle_pins_a: usart2-idle-0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
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bias-disable;
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};
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};
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usart2_sleep_pins_a: usart2-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
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<STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
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};
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};
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};
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102
arch/arm/dts/stm32mp25-u-boot.dtsi
Normal file
102
arch/arm/dts/stm32mp25-u-boot.dtsi
Normal file
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@ -0,0 +1,102 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2023
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*/
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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gpio25 = &gpioz;
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pinctrl0 = &pinctrl;
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pinctrl1 = &pinctrl_z;
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};
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firmware {
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optee {
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bootph-all;
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};
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};
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/* need PSCI for sysreset during board_f */
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psci {
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bootph-all;
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};
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soc@0 {
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bootph-all;
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};
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};
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&gpioa {
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bootph-all;
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};
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&gpiob {
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bootph-all;
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};
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&gpioc {
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bootph-all;
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};
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&gpiod {
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bootph-all;
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};
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&gpioe {
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bootph-all;
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};
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&gpiof {
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bootph-all;
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};
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&gpiog {
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bootph-all;
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};
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&gpioh {
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bootph-all;
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};
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&gpioi {
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bootph-all;
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};
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&gpioj {
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bootph-all;
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};
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&gpiok {
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bootph-all;
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};
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&gpioz {
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bootph-all;
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};
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&pinctrl {
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bootph-all;
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};
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&rifsc {
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bootph-all;
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};
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&scmi_clk {
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bootph-all;
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};
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&syscfg {
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bootph-all;
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};
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285
arch/arm/dts/stm32mp251.dtsi
Normal file
285
arch/arm/dts/stm32mp251.dtsi
Normal file
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@ -0,0 +1,285 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a35";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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interrupt-parent = <&intc>;
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};
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arm_wdt: watchdog {
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compatible = "arm,smc-wdt";
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arm,smc-id = <0xb200005a>;
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status = "disabled";
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};
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clocks {
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ck_flexgen_08: ck-flexgen-08 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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ck_flexgen_51: ck-flexgen-51 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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};
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ck_icn_ls_mcu: ck-icn-ls-mcu {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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};
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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scmi {
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compatible = "linaro,scmi-optee";
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#address-cells = <1>;
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#size-cells = <0>;
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linaro,optee-channel-id = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_reset: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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};
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};
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intc: interrupt-controller@4ac00000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x0 0x4ac10000 0x0 0x1000>,
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<0x0 0x4ac20000 0x0 0x2000>,
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<0x0 0x4ac40000 0x0 0x2000>,
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<0x0 0x4ac60000 0x0 0x2000>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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always-on;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges = <0x0 0x0 0x0 0x80000000>;
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rifsc: rifsc-bus@42080000 {
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compatible = "simple-bus";
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reg = <0x42080000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usart2: serial@400e0000 {
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compatible = "st,stm32h7-uart";
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reg = <0x400e0000 0x400>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ck_flexgen_08>;
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status = "disabled";
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};
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};
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syscfg: syscon@44230000 {
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compatible = "st,stm32mp25-syscfg", "syscon";
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reg = <0x44230000 0x10000>;
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};
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pinctrl: pinctrl@44240000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp257-pinctrl";
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ranges = <0 0x44240000 0xa0400>;
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pins-are-numbered;
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gpioa: gpio@44240000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOA";
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status = "disabled";
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};
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gpiob: gpio@44250000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x10000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOB";
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status = "disabled";
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};
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gpioc: gpio@44260000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x20000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOC";
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status = "disabled";
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};
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gpiod: gpio@44270000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x30000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOD";
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status = "disabled";
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};
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gpioe: gpio@44280000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x40000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOE";
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status = "disabled";
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};
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gpiof: gpio@44290000 {
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gpio-controller;
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#gpio-cells = <2>;
|
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x50000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOF";
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status = "disabled";
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};
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gpiog: gpio@442a0000 {
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gpio-controller;
|
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x60000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOG";
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status = "disabled";
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};
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gpioh: gpio@442b0000 {
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gpio-controller;
|
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#gpio-cells = <2>;
|
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interrupt-controller;
|
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#interrupt-cells = <2>;
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reg = <0x70000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOH";
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status = "disabled";
|
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};
|
||||
|
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gpioi: gpio@442c0000 {
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
||||
interrupt-controller;
|
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#interrupt-cells = <2>;
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reg = <0x80000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOI";
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status = "disabled";
|
||||
};
|
||||
|
||||
gpioj: gpio@442d0000 {
|
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gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x90000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
|
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st,bank-name = "GPIOJ";
|
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status = "disabled";
|
||||
};
|
||||
|
||||
gpiok: gpio@442e0000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xa0000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOK";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pinctrl@46200000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp257-z-pinctrl";
|
||||
ranges = <0 0x46200000 0x400>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioz: gpio@46200000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOZ";
|
||||
st,bank-ioport = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
23
arch/arm/dts/stm32mp253.dtsi
Normal file
23
arch/arm/dts/stm32mp253.dtsi
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include "stm32mp251.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a35";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
};
|
||||
9
arch/arm/dts/stm32mp255.dtsi
Normal file
9
arch/arm/dts/stm32mp255.dtsi
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include "stm32mp253.dtsi"
|
||||
|
||||
/ {
|
||||
};
|
||||
9
arch/arm/dts/stm32mp257.dtsi
Normal file
9
arch/arm/dts/stm32mp257.dtsi
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include "stm32mp255.dtsi"
|
||||
|
||||
/ {
|
||||
};
|
||||
20
arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
Normal file
20
arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
*/
|
||||
|
||||
#include "stm32mp25-u-boot.dtsi"
|
||||
|
||||
&usart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usart2_pins_a {
|
||||
bootph-all;
|
||||
pins1 {
|
||||
bootph-all;
|
||||
};
|
||||
pins2 {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
55
arch/arm/dts/stm32mp257f-ev1.dts
Normal file
55
arch/arm/dts/stm32mp257f-ev1.dts
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp257.dtsi"
|
||||
#include "stm32mp25xf.dtsi"
|
||||
#include "stm32mp25-pinctrl.dtsi"
|
||||
#include "stm32mp25xxai-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
|
||||
compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
|
||||
|
||||
aliases {
|
||||
serial0 = &usart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x1 0x0>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
fw@80000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x0 0x80000000 0x0 0x4000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&arm_wdt {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
pinctrl-names = "default", "idle", "sleep";
|
||||
pinctrl-0 = <&usart2_pins_a>;
|
||||
pinctrl-1 = <&usart2_idle_pins_a>;
|
||||
pinctrl-2 = <&usart2_sleep_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
8
arch/arm/dts/stm32mp25xc.dtsi
Normal file
8
arch/arm/dts/stm32mp25xc.dtsi
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
};
|
||||
8
arch/arm/dts/stm32mp25xf.dtsi
Normal file
8
arch/arm/dts/stm32mp25xf.dtsi
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
};
|
||||
83
arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
Normal file
83
arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AI>;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
status = "okay";
|
||||
ngpios = <14>;
|
||||
gpio-ranges = <&pinctrl 0 32 14>;
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 2 114 12>;
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@442d0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@442e0000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
gpioz: gpio@46200000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 10>;
|
||||
};
|
||||
};
|
||||
71
arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
Normal file
71
arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AK>;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
status = "okay";
|
||||
ngpios = <14>;
|
||||
gpio-ranges = <&pinctrl 0 32 14>;
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 2 114 12>;
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
gpioz: gpio@46200000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 10>;
|
||||
};
|
||||
};
|
||||
71
arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
Normal file
71
arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AL>;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
status = "okay";
|
||||
ngpios = <14>;
|
||||
gpio-ranges = <&pinctrl 0 32 14>;
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 2 114 12>;
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
gpioz: gpio@46200000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 10>;
|
||||
};
|
||||
};
|
||||
|
|
@ -513,14 +513,6 @@ enum dcache_option {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
|
||||
#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
|
||||
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
|
||||
#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
|
||||
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
|
||||
#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
|
||||
#endif
|
||||
|
||||
/* Size of an MMU section */
|
||||
enum {
|
||||
#ifdef CONFIG_ARMV7_LPAE
|
||||
|
|
@ -578,6 +570,14 @@ void psci_system_reset(void);
|
|||
|
||||
#endif /* CONFIG_ARM64 */
|
||||
|
||||
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
|
||||
#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
|
||||
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
|
||||
#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
|
||||
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
|
||||
#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/**
|
||||
* save_boot_params() - Save boot parameters before starting reset sequence
|
||||
|
|
|
|||
|
|
@ -76,6 +76,30 @@ config STM32MP15x
|
|||
STM32MP157, STM32MP153 or STM32MP151
|
||||
STMicroelectronics MPU with core ARMv7
|
||||
dual core A7 for STM32MP157/3, monocore for STM32MP151
|
||||
|
||||
config STM32MP25X
|
||||
bool "Support STMicroelectronics STM32MP25x Soc"
|
||||
select ARM64
|
||||
select CLK_STM32MP25
|
||||
select OF_BOARD
|
||||
select PINCTRL_STM32
|
||||
select STM32_RCC
|
||||
select STM32_RESET
|
||||
select STM32_SERIAL
|
||||
select SYS_ARCH_TIMER
|
||||
select TFABOOT
|
||||
imply CLK_SCMI
|
||||
imply CMD_NVEDIT_INFO
|
||||
imply DM_REGULATOR
|
||||
imply DM_REGULATOR_SCMI
|
||||
imply OPTEE
|
||||
imply RESET_SCMI
|
||||
imply SYSRESET_PSCI
|
||||
imply TEE
|
||||
imply VERSION_VARIABLE
|
||||
help
|
||||
Support of STMicroelectronics SOC STM32MP25x family
|
||||
STMicroelectronics MPU with 2 * A53 core and 1 M33 core
|
||||
endchoice
|
||||
|
||||
config NR_DRAM_BANKS
|
||||
|
|
@ -128,6 +152,6 @@ config CMD_STM32KEY
|
|||
|
||||
source "arch/arm/mach-stm32mp/Kconfig.13x"
|
||||
source "arch/arm/mach-stm32mp/Kconfig.15x"
|
||||
|
||||
source "arch/arm/mach-stm32mp/Kconfig.25x"
|
||||
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
|
||||
endif
|
||||
|
|
|
|||
43
arch/arm/mach-stm32mp/Kconfig.25x
Normal file
43
arch/arm/mach-stm32mp/Kconfig.25x
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
if STM32MP25X
|
||||
|
||||
choice
|
||||
prompt "STM32MP25x board select"
|
||||
optional
|
||||
|
||||
config TARGET_ST_STM32MP25X
|
||||
bool "STMicroelectronics STM32MP25x boards"
|
||||
imply BOOTSTAGE
|
||||
imply CMD_BOOTSTAGE
|
||||
help
|
||||
target the STMicroelectronics board with SOC STM32MP25x
|
||||
managed by board/st/stm32mp2
|
||||
The difference between board are managed with devicetree
|
||||
|
||||
endchoice
|
||||
|
||||
config TEXT_BASE
|
||||
default 0x84000000
|
||||
|
||||
config PRE_CON_BUF_ADDR
|
||||
default 0x84800000
|
||||
|
||||
config PRE_CON_BUF_SZ
|
||||
default 4096
|
||||
|
||||
config BOOTSTAGE_STASH_ADDR
|
||||
default 0x87000000
|
||||
|
||||
if DEBUG_UART
|
||||
|
||||
config DEBUG_UART_BOARD_INIT
|
||||
default y
|
||||
|
||||
# debug on USART2 by default
|
||||
config DEBUG_UART_BASE
|
||||
default 0x400e0000
|
||||
|
||||
endif
|
||||
|
||||
source "board/st/stm32mp2/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
@ -3,24 +3,17 @@
|
|||
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
|
||||
#
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += dram_init.o
|
||||
obj-y += syscon.o
|
||||
obj-y += bsec.o
|
||||
|
||||
obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
|
||||
obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
|
||||
obj-$(CONFIG_STM32MP15x) += stm32mp1/
|
||||
obj-$(CONFIG_STM32MP13x) += stm32mp1/
|
||||
obj-$(CONFIG_STM32MP25X) += stm32mp2/
|
||||
|
||||
obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-y += tzc400.o
|
||||
else
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
obj-y += cmd_stm32prog/
|
||||
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
|
||||
obj-$(CONFIG_ARMV7_PSCI) += psci.o
|
||||
obj-$(CONFIG_TFABOOT) += boot_params.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@
|
|||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: true if locked else false
|
||||
*/
|
||||
static bool bsec_read_lock(u32 address, u32 otp)
|
||||
static bool bsec_read_lock(void __iomem *address, u32 otp)
|
||||
{
|
||||
u32 bit;
|
||||
u32 bank;
|
||||
|
|
@ -118,7 +118,7 @@ static bool bsec_read_lock(u32 address, u32 otp)
|
|||
bit = 1 << (otp & OTP_LOCK_MASK);
|
||||
bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
|
||||
|
||||
return !!(readl(address + bank) & bit);
|
||||
return !!(readl((address + bank)) & bit);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -127,7 +127,7 @@ static bool bsec_read_lock(u32 address, u32 otp)
|
|||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: 0 if no error, -EAGAIN or -ENOTSUPP
|
||||
*/
|
||||
static u32 bsec_check_error(u32 base, u32 otp)
|
||||
static u32 bsec_check_error(void __iomem *base, u32 otp)
|
||||
{
|
||||
u32 bit;
|
||||
u32 bank;
|
||||
|
|
@ -149,7 +149,7 @@ static u32 bsec_check_error(u32 base, u32 otp)
|
|||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: true if locked else false
|
||||
*/
|
||||
static bool bsec_read_SR_lock(u32 base, u32 otp)
|
||||
static bool bsec_read_SR_lock(void __iomem *base, u32 otp)
|
||||
{
|
||||
return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
|
||||
}
|
||||
|
|
@ -160,7 +160,7 @@ static bool bsec_read_SR_lock(u32 base, u32 otp)
|
|||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: true if locked else false
|
||||
*/
|
||||
static bool bsec_read_SP_lock(u32 base, u32 otp)
|
||||
static bool bsec_read_SP_lock(void __iomem *base, u32 otp)
|
||||
{
|
||||
return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
|
||||
}
|
||||
|
|
@ -171,7 +171,7 @@ static bool bsec_read_SP_lock(u32 base, u32 otp)
|
|||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: true if locked else false
|
||||
*/
|
||||
static bool bsec_read_SW_lock(u32 base, u32 otp)
|
||||
static bool bsec_read_SW_lock(void __iomem *base, u32 otp)
|
||||
{
|
||||
return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
|
||||
}
|
||||
|
|
@ -182,7 +182,7 @@ static bool bsec_read_SW_lock(u32 base, u32 otp)
|
|||
* @power: true to power up , false to power down
|
||||
* Return: 0 if succeed
|
||||
*/
|
||||
static int bsec_power_safmem(u32 base, bool power)
|
||||
static int bsec_power_safmem(void __iomem *base, bool power)
|
||||
{
|
||||
u32 val;
|
||||
u32 mask;
|
||||
|
|
@ -208,7 +208,7 @@ static int bsec_power_safmem(u32 base, bool power)
|
|||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: 0 if no error
|
||||
*/
|
||||
static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
|
||||
static int bsec_shadow_register(struct udevice *dev, void __iomem *base, u32 otp)
|
||||
{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
|
@ -253,7 +253,8 @@ static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
|
|||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: 0 if no error
|
||||
*/
|
||||
static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
|
||||
static int bsec_read_shadow(struct udevice *dev, void __iomem *base, u32 *val,
|
||||
u32 otp)
|
||||
{
|
||||
*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
|
||||
|
||||
|
|
@ -268,7 +269,7 @@ static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
|
|||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: 0 if no error
|
||||
*/
|
||||
static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
|
||||
static int bsec_write_shadow(struct udevice *dev, void __iomem *base, u32 val, u32 otp)
|
||||
{
|
||||
/* check if programming of otp is locked */
|
||||
if (bsec_read_SW_lock(base, otp))
|
||||
|
|
@ -288,7 +289,7 @@ static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
|
|||
* after the function the otp data is not refreshed in shadow
|
||||
* Return: 0 if no error
|
||||
*/
|
||||
static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
|
||||
static int bsec_program_otp(struct udevice *dev, void __iomem *base, u32 val, u32 otp)
|
||||
{
|
||||
u32 ret;
|
||||
bool power_up = false;
|
||||
|
|
@ -338,7 +339,7 @@ static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
|
|||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: 0 if no error
|
||||
*/
|
||||
static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
|
||||
static int bsec_permanent_lock_otp(struct udevice *dev, void __iomem *base, uint32_t otp)
|
||||
{
|
||||
int ret;
|
||||
bool power_up = false;
|
||||
|
|
@ -392,7 +393,7 @@ static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
|
|||
|
||||
/* BSEC MISC driver *******************************************************/
|
||||
struct stm32mp_bsec_plat {
|
||||
u32 base;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
struct stm32mp_bsec_priv {
|
||||
|
|
@ -724,7 +725,7 @@ static int stm32mp_bsec_of_to_plat(struct udevice *dev)
|
|||
{
|
||||
struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
|
||||
|
||||
plat->base = (u32)dev_read_addr_ptr(dev);
|
||||
plat->base = dev_read_addr_ptr(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,8 +24,11 @@ int dram_init(void)
|
|||
int ret;
|
||||
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||
if (ret) {
|
||||
log_debug("RAM init failed: %d\n", ret);
|
||||
/* in case there is no RAM driver, retrieve DDR size from DT */
|
||||
if (ret == -ENODEV) {
|
||||
return fdtdec_setup_mem_size_base();
|
||||
} else if (ret) {
|
||||
log_err("RAM init failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
ret = ram_get_info(dev, &ram);
|
||||
|
|
@ -33,7 +36,7 @@ int dram_init(void)
|
|||
log_debug("Cannot get RAM size: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
|
||||
log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
|
||||
|
||||
gd->ram_size = ram.size;
|
||||
|
||||
|
|
@ -49,9 +52,15 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
|
|||
if (!total_size)
|
||||
return gd->ram_top;
|
||||
|
||||
/*
|
||||
* make sure U-Boot uses address space below 4GB boundaries even
|
||||
* if the effective available memory is bigger
|
||||
*/
|
||||
gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
|
||||
|
||||
/* found enough not-reserved memory to relocated U-Boot */
|
||||
lmb_init(&lmb);
|
||||
lmb_add(&lmb, gd->ram_base, get_effective_memsize());
|
||||
lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base);
|
||||
boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
|
||||
/* add 8M for reserved memory for display, fdt, gd,... */
|
||||
size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
|
||||
|
|
|
|||
|
|
@ -6,14 +6,69 @@
|
|||
#ifndef _MACH_STM32_H_
|
||||
#define _MACH_STM32_H_
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/bitops.h>
|
||||
|
||||
enum boot_device {
|
||||
BOOT_FLASH_SD = 0x10,
|
||||
BOOT_FLASH_SD_1 = 0x11,
|
||||
BOOT_FLASH_SD_2 = 0x12,
|
||||
BOOT_FLASH_SD_3 = 0x13,
|
||||
|
||||
BOOT_FLASH_EMMC = 0x20,
|
||||
BOOT_FLASH_EMMC_1 = 0x21,
|
||||
BOOT_FLASH_EMMC_2 = 0x22,
|
||||
BOOT_FLASH_EMMC_3 = 0x23,
|
||||
|
||||
BOOT_FLASH_NAND = 0x30,
|
||||
BOOT_FLASH_NAND_FMC = 0x31,
|
||||
|
||||
BOOT_FLASH_NOR = 0x40,
|
||||
BOOT_FLASH_NOR_QSPI = 0x41,
|
||||
|
||||
BOOT_SERIAL_UART = 0x50,
|
||||
BOOT_SERIAL_UART_1 = 0x51,
|
||||
BOOT_SERIAL_UART_2 = 0x52,
|
||||
BOOT_SERIAL_UART_3 = 0x53,
|
||||
BOOT_SERIAL_UART_4 = 0x54,
|
||||
BOOT_SERIAL_UART_5 = 0x55,
|
||||
BOOT_SERIAL_UART_6 = 0x56,
|
||||
BOOT_SERIAL_UART_7 = 0x57,
|
||||
BOOT_SERIAL_UART_8 = 0x58,
|
||||
|
||||
BOOT_SERIAL_USB = 0x60,
|
||||
BOOT_SERIAL_USB_OTG = 0x62,
|
||||
|
||||
BOOT_FLASH_SPINAND = 0x70,
|
||||
BOOT_FLASH_SPINAND_1 = 0x71,
|
||||
};
|
||||
|
||||
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
|
||||
#define TAMP_BOOT_MODE_SHIFT 8
|
||||
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
|
||||
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
|
||||
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
|
||||
#define TAMP_BOOT_DEBUG_ON BIT(16)
|
||||
|
||||
enum forced_boot_mode {
|
||||
BOOT_NORMAL = 0x00,
|
||||
BOOT_FASTBOOT = 0x01,
|
||||
BOOT_RECOVERY = 0x02,
|
||||
BOOT_STM32PROG = 0x03,
|
||||
BOOT_UMS_MMC0 = 0x10,
|
||||
BOOT_UMS_MMC1 = 0x11,
|
||||
BOOT_UMS_MMC2 = 0x12,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Peripheral memory map
|
||||
* only address used before device tree parsing
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x)
|
||||
#define STM32_RCC_BASE 0x50000000
|
||||
#define STM32_PWR_BASE 0x50001000
|
||||
#define STM32_SYSCFG_BASE 0x50020000
|
||||
|
|
@ -58,12 +113,6 @@
|
|||
#define STM32_DDR_SIZE SZ_1G
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/* enumerated used to identify the SYSCON driver instance */
|
||||
enum {
|
||||
STM32MP_SYSCON_UNKNOWN,
|
||||
STM32MP_SYSCON_SYSCFG,
|
||||
};
|
||||
|
||||
/*
|
||||
* enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
|
||||
* - boot device = bit 8:4
|
||||
|
|
@ -74,40 +123,6 @@ enum {
|
|||
#define BOOT_INSTANCE_MASK 0x0F
|
||||
#define BOOT_INSTANCE_SHIFT 0
|
||||
|
||||
enum boot_device {
|
||||
BOOT_FLASH_SD = 0x10,
|
||||
BOOT_FLASH_SD_1 = 0x11,
|
||||
BOOT_FLASH_SD_2 = 0x12,
|
||||
BOOT_FLASH_SD_3 = 0x13,
|
||||
|
||||
BOOT_FLASH_EMMC = 0x20,
|
||||
BOOT_FLASH_EMMC_1 = 0x21,
|
||||
BOOT_FLASH_EMMC_2 = 0x22,
|
||||
BOOT_FLASH_EMMC_3 = 0x23,
|
||||
|
||||
BOOT_FLASH_NAND = 0x30,
|
||||
BOOT_FLASH_NAND_FMC = 0x31,
|
||||
|
||||
BOOT_FLASH_NOR = 0x40,
|
||||
BOOT_FLASH_NOR_QSPI = 0x41,
|
||||
|
||||
BOOT_SERIAL_UART = 0x50,
|
||||
BOOT_SERIAL_UART_1 = 0x51,
|
||||
BOOT_SERIAL_UART_2 = 0x52,
|
||||
BOOT_SERIAL_UART_3 = 0x53,
|
||||
BOOT_SERIAL_UART_4 = 0x54,
|
||||
BOOT_SERIAL_UART_5 = 0x55,
|
||||
BOOT_SERIAL_UART_6 = 0x56,
|
||||
BOOT_SERIAL_UART_7 = 0x57,
|
||||
BOOT_SERIAL_UART_8 = 0x58,
|
||||
|
||||
BOOT_SERIAL_USB = 0x60,
|
||||
BOOT_SERIAL_USB_OTG = 0x62,
|
||||
|
||||
BOOT_FLASH_SPINAND = 0x70,
|
||||
BOOT_FLASH_SPINAND_1 = 0x71,
|
||||
};
|
||||
|
||||
/* TAMP registers */
|
||||
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
|
||||
|
||||
|
|
@ -123,7 +138,6 @@ enum boot_device {
|
|||
#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0)
|
||||
|
||||
#define TAMP_FWU_BOOT_IDX_OFFSET 0
|
||||
|
||||
#define TAMP_COPRO_STATE_OFF 0
|
||||
#define TAMP_COPRO_STATE_INIT 1
|
||||
#define TAMP_COPRO_STATE_CRUN 2
|
||||
|
|
@ -137,21 +151,23 @@ enum boot_device {
|
|||
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
|
||||
#endif
|
||||
|
||||
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
|
||||
#define TAMP_BOOT_MODE_SHIFT 8
|
||||
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
|
||||
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
|
||||
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
|
||||
|
||||
enum forced_boot_mode {
|
||||
BOOT_NORMAL = 0x00,
|
||||
BOOT_FASTBOOT = 0x01,
|
||||
BOOT_RECOVERY = 0x02,
|
||||
BOOT_STM32PROG = 0x03,
|
||||
BOOT_UMS_MMC0 = 0x10,
|
||||
BOOT_UMS_MMC1 = 0x11,
|
||||
BOOT_UMS_MMC2 = 0x12,
|
||||
};
|
||||
#if CONFIG_STM32MP25X
|
||||
#define STM32_RCC_BASE 0x44200000
|
||||
#define STM32_TAMP_BASE 0x46010000
|
||||
|
||||
#define STM32_DDR_BASE 0x80000000
|
||||
|
||||
#define STM32_DDR_SIZE SZ_4G
|
||||
|
||||
/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */
|
||||
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x))
|
||||
|
||||
/* TAMP registers zone 3 RIF 1 (RW) at 96*/
|
||||
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96)
|
||||
#endif /* STM32MP25X */
|
||||
|
||||
/* offset used for BSEC driver: misc_read and misc_write */
|
||||
#define STM32_BSEC_SHADOW_OFFSET 0x0
|
||||
|
|
@ -175,6 +191,20 @@ enum forced_boot_mode {
|
|||
#define BSEC_OTP_MAC 57
|
||||
#define BSEC_OTP_BOARD 60
|
||||
#endif
|
||||
#ifdef CONFIG_STM32MP25X
|
||||
#define BSEC_OTP_SERIAL 5
|
||||
#define BSEC_OTP_RPN 9
|
||||
#define BSEC_OTP_PKG 246
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
|
||||
/* enumerated used to identify the SYSCON driver instance */
|
||||
enum {
|
||||
STM32MP_SYSCON_UNKNOWN,
|
||||
STM32MP_SYSCON_SYSCFG,
|
||||
};
|
||||
#endif /* __ASSEMBLY__*/
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* _MACH_STM32_H_ */
|
||||
|
|
|
|||
|
|
@ -30,11 +30,30 @@
|
|||
#define CPU_STM32MP131Fxx 0x05010EC8
|
||||
#define CPU_STM32MP131Dxx 0x05010EC9
|
||||
|
||||
/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
|
||||
#define CPU_STM32MP257Cxx 0x00002000
|
||||
#define CPU_STM32MP255Cxx 0x00082000
|
||||
#define CPU_STM32MP253Cxx 0x000B2004
|
||||
#define CPU_STM32MP251Cxx 0x000B3065
|
||||
#define CPU_STM32MP257Axx 0x40002E00
|
||||
#define CPU_STM32MP255Axx 0x40082E00
|
||||
#define CPU_STM32MP253Axx 0x400B2E04
|
||||
#define CPU_STM32MP251Axx 0x400B3E65
|
||||
#define CPU_STM32MP257Fxx 0x80002000
|
||||
#define CPU_STM32MP255Fxx 0x80082000
|
||||
#define CPU_STM32MP253Fxx 0x800B2004
|
||||
#define CPU_STM32MP251Fxx 0x800B3065
|
||||
#define CPU_STM32MP257Dxx 0xC0002E00
|
||||
#define CPU_STM32MP255Dxx 0xC0082E00
|
||||
#define CPU_STM32MP253Dxx 0xC00B2E04
|
||||
#define CPU_STM32MP251Dxx 0xC00B3E65
|
||||
|
||||
/* return CPU_STMP32MP...Xxx constants */
|
||||
u32 get_cpu_type(void);
|
||||
|
||||
#define CPU_DEV_STM32MP15 0x500
|
||||
#define CPU_DEV_STM32MP13 0x501
|
||||
#define CPU_DEV_STM32MP25 0x505
|
||||
|
||||
/* return CPU_DEV constants */
|
||||
u32 get_cpu_dev(void);
|
||||
|
|
@ -59,6 +78,13 @@ u32 get_cpu_package(void);
|
|||
#define STM32MP15_PKG_AD_TFBGA257 1
|
||||
#define STM32MP15_PKG_UNKNOWN 0
|
||||
|
||||
/* package used for STM32MP25x */
|
||||
#define STM32MP25_PKG_CUSTOM 0
|
||||
#define STM32MP25_PKG_AL_TBGA361 3
|
||||
#define STM32MP25_PKG_AK_TBGA424 4
|
||||
#define STM32MP25_PKG_AI_TBGA436 5
|
||||
#define STM32MP25_PKG_UNKNOWN 7
|
||||
|
||||
/* Get SOC name */
|
||||
#define SOC_NAME_SIZE 20
|
||||
void get_soc_name(char name[SOC_NAME_SIZE]);
|
||||
|
|
|
|||
20
arch/arm/mach-stm32mp/stm32mp1/Makefile
Normal file
20
arch/arm/mach-stm32mp/stm32mp1/Makefile
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
|
||||
#
|
||||
|
||||
obj-y += cpu.o
|
||||
|
||||
obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
|
||||
obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
|
||||
|
||||
obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-y += tzc400.o
|
||||
else
|
||||
obj-$(CONFIG_ARMV7_PSCI) += psci.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
|
||||
9
arch/arm/mach-stm32mp/stm32mp2/Makefile
Normal file
9
arch/arm/mach-stm32mp/stm32mp2/Makefile
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
#
|
||||
# Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
#
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += arm64-mmu.o
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
|
||||
obj-$(CONFIG_STM32MP25X) += stm32mp25x.o
|
||||
68
arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c
Normal file
68
arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <mach/stm32.h>
|
||||
|
||||
#define MP2_MEM_MAP_MAX 10
|
||||
|
||||
#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \
|
||||
(CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE))
|
||||
#error "invalid CONFIG_TEXT_BASE value"
|
||||
#endif
|
||||
|
||||
struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
|
||||
{
|
||||
/* PCIe */
|
||||
.virt = 0x10000000UL,
|
||||
.phys = 0x10000000UL,
|
||||
.size = 0x10000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */
|
||||
.virt = 0x20000000UL,
|
||||
.phys = 0x20000000UL,
|
||||
.size = 0x00200000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* Peripherals: alias1 */
|
||||
.virt = 0x40000000UL,
|
||||
.phys = 0x40000000UL,
|
||||
.size = 0x10000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* OSPI and FMC: memory-map area */
|
||||
.virt = 0x60000000UL,
|
||||
.phys = 0x60000000UL,
|
||||
.size = 0x20000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/*
|
||||
* DDR = STM32_DDR_BASE / STM32_DDR_SIZE
|
||||
* the beginning of DDR (before CONFIG_TEXT_BASE) is not
|
||||
* mapped, protected by RIF and reserved for other firmware
|
||||
* (OP-TEE / TF-M / Cube M33)
|
||||
*/
|
||||
.virt = CONFIG_TEXT_BASE,
|
||||
.phys = CONFIG_TEXT_BASE,
|
||||
.size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE),
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = stm32mp2_mem_map;
|
||||
107
arch/arm/mach-stm32mp/stm32mp2/cpu.c
Normal file
107
arch/arm/mach-stm32mp/stm32mp2/cpu.c
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <clk.h>
|
||||
#include <cpu_func.h>
|
||||
#include <debug_uart.h>
|
||||
#include <env_internal.h>
|
||||
#include <init.h>
|
||||
#include <misc.h>
|
||||
#include <wdt.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/stm32.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/system.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/lists.h>
|
||||
#include <dm/uclass.h>
|
||||
|
||||
/*
|
||||
* early TLB into the .data section so that it not get cleared
|
||||
* with 16kB alignment
|
||||
*/
|
||||
#define EARLY_TLB_SIZE 0xA000
|
||||
u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
|
||||
|
||||
/*
|
||||
* initialize the MMU and activate cache in U-Boot pre-reloc stage
|
||||
* MMU/TLB is updated in enable_caches() for U-Boot after relocation
|
||||
*/
|
||||
static void early_enable_caches(void)
|
||||
{
|
||||
if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
|
||||
return;
|
||||
|
||||
if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
|
||||
gd->arch.tlb_size = EARLY_TLB_SIZE;
|
||||
gd->arch.tlb_addr = (unsigned long)&early_tlb;
|
||||
}
|
||||
/* enable MMU (default configuration) */
|
||||
dcache_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
* Early system init
|
||||
*/
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
icache_enable();
|
||||
early_enable_caches();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void enable_caches(void)
|
||||
{
|
||||
/* deactivate the data cache, early enabled in arch_cpu_init() */
|
||||
dcache_disable();
|
||||
/*
|
||||
* Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr
|
||||
* to update the TLB location udpated in board_f.c::reserve_mmu
|
||||
*/
|
||||
gd->arch.tlb_fillptr = 0;
|
||||
dcache_enable();
|
||||
}
|
||||
|
||||
/* used when CONFIG_DISPLAY_CPUINFO is activated */
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
char name[SOC_NAME_SIZE];
|
||||
|
||||
get_soc_name(name);
|
||||
printf("CPU: %s\n", name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Force data-section, as .bss will not be valid
|
||||
* when save_boot_params is invoked.
|
||||
*/
|
||||
static uintptr_t nt_fw_dtb __section(".data");
|
||||
|
||||
uintptr_t get_stm32mp_bl2_dtb(void)
|
||||
{
|
||||
return nt_fw_dtb;
|
||||
}
|
||||
|
||||
/*
|
||||
* Save the FDT address provided by TF-A in r2 at boot time
|
||||
* This function is called from start.S
|
||||
*/
|
||||
void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
|
||||
unsigned long r3)
|
||||
{
|
||||
nt_fw_dtb = r2;
|
||||
|
||||
save_boot_params_ret();
|
||||
}
|
||||
16
arch/arm/mach-stm32mp/stm32mp2/fdt.c
Normal file
16
arch/arm/mach-stm32mp/stm32mp2/fdt.c
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#include <asm/u-boot.h>
|
||||
|
||||
/*
|
||||
* This function is called right before the kernel is booted. "blob" is the
|
||||
* device tree that will be passed to the kernel.
|
||||
*/
|
||||
int ft_system_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
193
arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
Normal file
193
arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <log.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/stm32.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
/* SYSCFG register */
|
||||
#define SYSCFG_DEVICEID_OFFSET 0x6400
|
||||
#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
|
||||
#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
|
||||
#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
|
||||
#define SYSCFG_DEVICEID_REV_ID_SHIFT 16
|
||||
|
||||
/* Device Part Number (RPN) = OTP9 */
|
||||
#define RPN_SHIFT 0
|
||||
#define RPN_MASK GENMASK(31, 0)
|
||||
|
||||
/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
|
||||
* - 000: Custom package
|
||||
* - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
|
||||
* - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
|
||||
* - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
|
||||
* - others: Reserved
|
||||
*/
|
||||
#define PKG_SHIFT 0
|
||||
#define PKG_MASK GENMASK(2, 0)
|
||||
|
||||
static u32 read_deviceid(void)
|
||||
{
|
||||
void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
|
||||
|
||||
return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
|
||||
}
|
||||
|
||||
u32 get_cpu_dev(void)
|
||||
{
|
||||
return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
|
||||
}
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
|
||||
}
|
||||
|
||||
/* Get Device Part Number (RPN) from OTP */
|
||||
u32 get_cpu_type(void)
|
||||
{
|
||||
return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
|
||||
}
|
||||
|
||||
/* Get Package options from OTP */
|
||||
u32 get_cpu_package(void)
|
||||
{
|
||||
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
|
||||
}
|
||||
|
||||
int get_eth_nb(void)
|
||||
{
|
||||
int nb_eth;
|
||||
|
||||
switch (get_cpu_type()) {
|
||||
case CPU_STM32MP257Fxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP257Dxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP257Cxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP257Axx:
|
||||
nb_eth = 5; /* dual ETH with TSN support */
|
||||
break;
|
||||
case CPU_STM32MP253Fxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP253Dxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP253Cxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP253Axx:
|
||||
nb_eth = 2; /* dual ETH */
|
||||
break;
|
||||
case CPU_STM32MP251Fxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP251Dxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP251Cxx:
|
||||
fallthrough;
|
||||
case CPU_STM32MP251Axx:
|
||||
nb_eth = 1; /* single ETH */
|
||||
break;
|
||||
default:
|
||||
nb_eth = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return nb_eth;
|
||||
}
|
||||
|
||||
void get_soc_name(char name[SOC_NAME_SIZE])
|
||||
{
|
||||
char *cpu_s, *cpu_r, *package;
|
||||
|
||||
cpu_s = "????";
|
||||
cpu_r = "?";
|
||||
package = "??";
|
||||
if (get_cpu_dev() == CPU_DEV_STM32MP25) {
|
||||
switch (get_cpu_type()) {
|
||||
case CPU_STM32MP257Fxx:
|
||||
cpu_s = "257F";
|
||||
break;
|
||||
case CPU_STM32MP257Dxx:
|
||||
cpu_s = "257D";
|
||||
break;
|
||||
case CPU_STM32MP257Cxx:
|
||||
cpu_s = "257C";
|
||||
break;
|
||||
case CPU_STM32MP257Axx:
|
||||
cpu_s = "257A";
|
||||
break;
|
||||
case CPU_STM32MP255Fxx:
|
||||
cpu_s = "255F";
|
||||
break;
|
||||
case CPU_STM32MP255Dxx:
|
||||
cpu_s = "255D";
|
||||
break;
|
||||
case CPU_STM32MP255Cxx:
|
||||
cpu_s = "255C";
|
||||
break;
|
||||
case CPU_STM32MP255Axx:
|
||||
cpu_s = "255A";
|
||||
break;
|
||||
case CPU_STM32MP253Fxx:
|
||||
cpu_s = "253F";
|
||||
break;
|
||||
case CPU_STM32MP253Dxx:
|
||||
cpu_s = "253D";
|
||||
break;
|
||||
case CPU_STM32MP253Cxx:
|
||||
cpu_s = "253C";
|
||||
break;
|
||||
case CPU_STM32MP253Axx:
|
||||
cpu_s = "253A";
|
||||
break;
|
||||
case CPU_STM32MP251Fxx:
|
||||
cpu_s = "251F";
|
||||
break;
|
||||
case CPU_STM32MP251Dxx:
|
||||
cpu_s = "251D";
|
||||
break;
|
||||
case CPU_STM32MP251Cxx:
|
||||
cpu_s = "251C";
|
||||
break;
|
||||
case CPU_STM32MP251Axx:
|
||||
cpu_s = "251A";
|
||||
break;
|
||||
default:
|
||||
cpu_s = "25??";
|
||||
break;
|
||||
}
|
||||
/* REVISION */
|
||||
switch (get_cpu_rev()) {
|
||||
case CPU_REV1:
|
||||
cpu_r = "A";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/* PACKAGE */
|
||||
switch (get_cpu_package()) {
|
||||
case STM32MP25_PKG_CUSTOM:
|
||||
package = "XX";
|
||||
break;
|
||||
case STM32MP25_PKG_AL_TBGA361:
|
||||
package = "AL";
|
||||
break;
|
||||
case STM32MP25_PKG_AK_TBGA424:
|
||||
package = "AK";
|
||||
break;
|
||||
case STM32MP25_PKG_AI_TBGA436:
|
||||
package = "AI";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
|
||||
}
|
||||
|
|
@ -10,8 +10,8 @@
|
|||
#include <asm/arch/stm32.h>
|
||||
|
||||
static const struct udevice_id stm32mp_syscon_ids[] = {
|
||||
{ .compatible = "st,stm32mp157-syscfg",
|
||||
.data = STM32MP_SYSCON_SYSCFG },
|
||||
{ .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG },
|
||||
{ .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
13
board/st/stm32mp2/Kconfig
Normal file
13
board/st/stm32mp2/Kconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
if TARGET_ST_STM32MP25X
|
||||
|
||||
config SYS_BOARD
|
||||
default "stm32mp2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "st"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "stm32mp25_common"
|
||||
|
||||
source "board/st/common/Kconfig"
|
||||
endif
|
||||
9
board/st/stm32mp2/MAINTAINERS
Normal file
9
board/st/stm32mp2/MAINTAINERS
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
STM32MP2 BOARD
|
||||
M: Patrice Chotard <patrice.chotard@st.com>
|
||||
M: Patrick Delaunay <patrick.delaunay@st.com>
|
||||
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/dts/stm32mp25*
|
||||
F: board/st/stm32mp2/
|
||||
F: configs/stm32mp25_defconfig
|
||||
F: include/configs/stm32mp25_common.h
|
||||
6
board/st/stm32mp2/Makefile
Normal file
6
board/st/stm32mp2/Makefile
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
#
|
||||
# Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
#
|
||||
|
||||
obj-y += stm32mp2.o
|
||||
51
board/st/stm32mp2/stm32mp2.c
Normal file
51
board/st/stm32mp2/stm32mp2.c
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY LOGC_BOARD
|
||||
|
||||
#include <config.h>
|
||||
#include <env.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
/*
|
||||
* Get a global data pointer
|
||||
*/
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* board dependent setup after realloc */
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
const void *fdt_compat;
|
||||
int fdt_compat_len;
|
||||
char dtb_name[256];
|
||||
int buf_len;
|
||||
|
||||
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
|
||||
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
|
||||
&fdt_compat_len);
|
||||
if (fdt_compat && fdt_compat_len) {
|
||||
if (strncmp(fdt_compat, "st,", 3) != 0) {
|
||||
env_set("board_name", fdt_compat);
|
||||
} else {
|
||||
env_set("board_name", fdt_compat + 3);
|
||||
|
||||
buf_len = sizeof(dtb_name);
|
||||
strlcpy(dtb_name, fdt_compat + 3, buf_len);
|
||||
buf_len -= strlen(fdt_compat + 3);
|
||||
strlcat(dtb_name, ".dtb", buf_len);
|
||||
env_set("fdtfile", dtb_name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
52
configs/stm32mp25_defconfig
Normal file
52
configs/stm32mp25_defconfig
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_STM32MP=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x400000
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="stm32mp257f-ev1"
|
||||
CONFIG_STM32MP25X=y
|
||||
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
|
||||
CONFIG_TARGET_ST_STM32MP25X=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x84000000
|
||||
CONFIG_SYS_MEMTEST_START=0x84000000
|
||||
CONFIG_SYS_MEMTEST_END=0x88000000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_LAST_STAGE_INIT=y
|
||||
CONFIG_SYS_PROMPT="STM32MP> "
|
||||
# CONFIG_CMD_BDI is not set
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_ADTIMG=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_NET is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_RNG=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_LOG=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_STM32F7=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_RAM=y
|
||||
# CONFIG_STM32MP1_DDR is not set
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_SERIAL_RX_BUFFER=y
|
||||
# CONFIG_OPTEE_TA_AVB is not set
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_STM32MP=y
|
||||
CONFIG_WDT_ARM_SMC=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
# CONFIG_LMB_USE_MAX_REGIONS is not set
|
||||
CONFIG_LMB_MEMORY_REGIONS=2
|
||||
CONFIG_LMB_RESERVED_REGIONS=32
|
||||
|
|
@ -505,6 +505,8 @@ static const struct udevice_id stm32_pinctrl_ids[] = {
|
|||
{ .compatible = "st,stm32mp157-pinctrl" },
|
||||
{ .compatible = "st,stm32mp157-z-pinctrl" },
|
||||
{ .compatible = "st,stm32mp135-pinctrl" },
|
||||
{ .compatible = "st,stm32mp257-pinctrl" },
|
||||
{ .compatible = "st,stm32mp257-z-pinctrl" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
*/
|
||||
#define ONE_BYTE_B115200_US 87
|
||||
|
||||
static void _stm32_serial_setbrg(fdt_addr_t base,
|
||||
static void _stm32_serial_setbrg(void __iomem *base,
|
||||
struct stm32_uart_info *uart_info,
|
||||
u32 clock_rate,
|
||||
int baudrate)
|
||||
|
|
@ -75,7 +75,7 @@ static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
|
|||
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
|
||||
bool stm32f4 = plat->uart_info->stm32f4;
|
||||
u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
|
||||
u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
|
||||
void __iomem *cr1 = plat->base + CR1_OFFSET(stm32f4);
|
||||
u32 config = 0;
|
||||
uint parity = SERIAL_GET_PARITY(serial_config);
|
||||
uint bits = SERIAL_GET_BITS(serial_config);
|
||||
|
|
@ -122,7 +122,7 @@ static int stm32_serial_getc(struct udevice *dev)
|
|||
{
|
||||
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
|
||||
bool stm32f4 = plat->uart_info->stm32f4;
|
||||
fdt_addr_t base = plat->base;
|
||||
void __iomem *base = plat->base;
|
||||
u32 isr = readl(base + ISR_OFFSET(stm32f4));
|
||||
|
||||
if ((isr & USART_ISR_RXNE) == 0)
|
||||
|
|
@ -141,7 +141,7 @@ static int stm32_serial_getc(struct udevice *dev)
|
|||
return readl(base + RDR_OFFSET(stm32f4));
|
||||
}
|
||||
|
||||
static int _stm32_serial_putc(fdt_addr_t base,
|
||||
static int _stm32_serial_putc(void __iomem *base,
|
||||
struct stm32_uart_info *uart_info,
|
||||
const char c)
|
||||
{
|
||||
|
|
@ -166,7 +166,7 @@ static int stm32_serial_pending(struct udevice *dev, bool input)
|
|||
{
|
||||
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
|
||||
bool stm32f4 = plat->uart_info->stm32f4;
|
||||
fdt_addr_t base = plat->base;
|
||||
void __iomem *base = plat->base;
|
||||
|
||||
if (input)
|
||||
return readl(base + ISR_OFFSET(stm32f4)) &
|
||||
|
|
@ -176,7 +176,7 @@ static int stm32_serial_pending(struct udevice *dev, bool input)
|
|||
USART_ISR_TXE ? 0 : 1;
|
||||
}
|
||||
|
||||
static void _stm32_serial_init(fdt_addr_t base,
|
||||
static void _stm32_serial_init(void __iomem *base,
|
||||
struct stm32_uart_info *uart_info)
|
||||
{
|
||||
bool stm32f4 = uart_info->stm32f4;
|
||||
|
|
@ -250,11 +250,14 @@ static const struct udevice_id stm32_serial_id[] = {
|
|||
static int stm32_serial_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
|
||||
fdt_addr_t addr;
|
||||
|
||||
plat->base = dev_read_addr(dev);
|
||||
if (plat->base == FDT_ADDR_T_NONE)
|
||||
addr = dev_read_addr(dev);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
plat->base = (void __iomem *)addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -297,7 +300,7 @@ static inline struct stm32_uart_info *_debug_uart_info(void)
|
|||
|
||||
static inline void _debug_uart_init(void)
|
||||
{
|
||||
fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
|
||||
void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
|
||||
struct stm32_uart_info *uart_info = _debug_uart_info();
|
||||
|
||||
_stm32_serial_init(base, uart_info);
|
||||
|
|
@ -308,7 +311,7 @@ static inline void _debug_uart_init(void)
|
|||
|
||||
static inline void _debug_uart_putc(int c)
|
||||
{
|
||||
fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
|
||||
void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
|
||||
struct stm32_uart_info *uart_info = _debug_uart_info();
|
||||
|
||||
while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ struct stm32_uart_info stm32h7_info = {
|
|||
|
||||
/* Information about a serial port */
|
||||
struct stm32x7_serial_plat {
|
||||
fdt_addr_t base; /* address of registers in physical memory */
|
||||
void __iomem *base; /* address of registers in physical memory */
|
||||
struct stm32_uart_info *uart_info;
|
||||
unsigned long int clock_rate;
|
||||
};
|
||||
|
|
|
|||
24
include/configs/stm32mp25_common.h
Normal file
24
include/configs/stm32mp25_common.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* Configuration settings for the STM32MP25x CPU
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_STM32MP25_COMMMON_H
|
||||
#define __CONFIG_STM32MP25_COMMMON_H
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/stm32.h>
|
||||
|
||||
/*
|
||||
* Configuration of the external SRAM memory used by U-Boot
|
||||
*/
|
||||
#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
|
||||
|
||||
/*
|
||||
* For booting Linux, use the first 256 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_SYS_BOOTMAPSZ SZ_256M
|
||||
|
||||
#endif /* __CONFIG_STM32MP25_COMMMON_H */
|
||||
|
|
@ -37,6 +37,9 @@
|
|||
#define STM32MP_PKG_AB 0x2
|
||||
#define STM32MP_PKG_AC 0x4
|
||||
#define STM32MP_PKG_AD 0x8
|
||||
#define STM32MP_PKG_AI 0x100
|
||||
#define STM32MP_PKG_AK 0x400
|
||||
#define STM32MP_PKG_AL 0x800
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue