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Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next

Browse source 
Device tree improvents for Paz00 and DM PMIC convertion of recently
merged Tegra boards.
This commit is contained in:
Tom Rini 2023-11-30 09:33:31 -05:00
commit 4a363dd516
52 changed files with 1053 additions and 1250 deletions
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19
arch/arm/dts/tegra20-paz00.dts
View file

@ -315,20 +315,19 @@
clock-frequency = <100000>;
};
nvec@7000c500 {
i2c@7000c500 {
compatible = "nvidia,nvec";
reg = <0x7000c500 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
/delete-property/ #address-cells;
/delete-property/ #size-cells;
/delete-property/ dmas;
/delete-property/ dma-names;
clock-frequency = <80000>;
request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
slave-addr = <138>;
clocks = <&tegra_car TEGRA20_CLK_I2C3>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 67>;
reset-names = "i2c";
status = "okay";
};
i2c@7000d000 {

7
arch/arm/dts/tegra30-asus-grouper-common.dtsi
View file

@ -71,6 +71,13 @@
dr_mode = "otg";
};
usb-phy@7d000000 {
status = "okay";
nvidia,hssync-start-delay = <0>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
};
backlight: backlight {
compatible = "pwm-backlight";

1
arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts
View file

@ -35,6 +35,7 @@
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-boot-on;
};
};
};

1
arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts
View file

@ -36,6 +36,7 @@
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};

1
arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts
View file

@ -35,6 +35,7 @@
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-boot-on;
};
};
};

17
arch/arm/dts/tegra30-asus-p1801-t.dts
View file

@ -101,6 +101,7 @@
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
/* uSD slot VDD */
@ -108,6 +109,7 @@
regulator-name = "vdd_usd";
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-boot-on;
};
/* uSD slot VDDIO */
@ -148,17 +150,32 @@
dr_mode = "otg";
};
usb-phy@7d000000 {
status = "okay";
nvidia,hssync-start-delay = <0>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
};
/* Mini USB port */
usb2: usb@7d004000 {
status = "okay";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
};
usb-phy@7d004000 {
status = "okay";
};
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";
};
usb-phy@7d008000 {
status = "okay";
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";

15
arch/arm/dts/tegra30-asus-tf600t.dts
View file

@ -84,12 +84,14 @@
regulator-name = "vdd_1v2_backlight";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
};
vcore_lcd: vdd2 {
regulator-name = "vcore_lcd";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
};
vdd_1v8_vio: vddio {
@ -105,6 +107,7 @@
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
/* uSD slot VDDIO */
@ -119,6 +122,7 @@
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
};
};
};
@ -161,11 +165,22 @@
dr_mode = "otg";
};
usb-phy@7d000000 {
status = "okay";
nvidia,hssync-start-delay = <0>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
};
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";
};
usb-phy@7d008000 {
status = "okay";
};
backlight: backlight {
compatible = "pwm-backlight";

9
arch/arm/dts/tegra30-asus-transformer.dtsi
View file

@ -82,6 +82,7 @@
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
/* uSD slot VDD */
@ -89,6 +90,7 @@
regulator-name = "vdd_usd";
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-boot-on;
};
/* uSD slot VDDIO */
@ -129,6 +131,13 @@
dr_mode = "otg";
};
usb-phy@7d000000 {
status = "okay";
nvidia,hssync-start-delay = <0>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
};
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";

8
arch/arm/dts/tegra30-htc-endeavoru.dts
View file

@ -81,6 +81,7 @@
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
};
};
};
@ -100,6 +101,13 @@
dr_mode = "otg";
};
usb-phy@7d000000 {
status = "okay";
nvidia,hssync-start-delay = <0>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
};
backlight: backlight {
compatible = "nvidia,tegra-pwm-backlight";

9
arch/arm/dts/tegra30-lg-x3.dtsi
View file

@ -110,6 +110,7 @@
regulator-name = "vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-boot-on;
};
};
};
@ -152,6 +153,14 @@
dr_mode = "otg";
};
usb-phy@7d000000 {
status = "okay";
nvidia,hssync-start-delay = <0>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
vbus-supply = <&avdd_3v3_periph>;
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";

5
arch/arm/mach-tegra/board2.c
View file

@ -11,6 +11,7 @@
#include <init.h>
#include <log.h>
#include <ns16550.h>
#include <power/regulator.h>
#include <usb.h>
#include <asm/global_data.h>
#include <asm/io.h>
@ -185,6 +186,10 @@ int board_init(void)
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
/* Set up boot-on regulators */
regulators_enable_boot_on(_DEBUG);
return nvidia_board_init();
}

8
board/asus/grouper/Kconfig
View file

@ -9,12 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "grouper"
config GROUPER_TPS65911
bool "Enable support TI TPS65911 PMIC"
select CMD_POWEROFF
config GROUPER_MAX77663
bool "Enable support MAXIM MAX77663 PMIC"
select CMD_POWEROFF
endif

4
board/asus/grouper/Makefile
View file

@ -7,8 +7,8 @@
# Svyatoslav Ryhel <clamor95@gmail.com>
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_GROUPER_MAX77663) += grouper-spl-max.o
obj-$(CONFIG_GROUPER_TPS65911) += grouper-spl-ti.o
obj-$(CONFIG_DM_PMIC_MAX77663) += grouper-spl-max.o
obj-$(CONFIG_DM_PMIC_TPS65910) += grouper-spl-ti.o
endif
obj-y += grouper.o

6
board/asus/grouper/configs/grouper_E1565.config
View file

@ -1,2 +1,6 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
CONFIG_GROUPER_MAX77663=y
CONFIG_CMD_POWEROFF=y
# CONFIG_MAX77663_GPIO is not set
CONFIG_DM_PMIC_MAX77663=y
CONFIG_DM_REGULATOR_MAX77663=y
CONFIG_SYSRESET_MAX77663=y

6
board/asus/grouper/configs/grouper_PM269.config
View file

@ -1,2 +1,6 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-PM269"
CONFIG_GROUPER_TPS65911=y
CONFIG_CMD_POWEROFF=y
CONFIG_DM_PMIC_TPS65910=y
# CONFIG_DM_REGULATOR_TPS65910 is not set
CONFIG_DM_REGULATOR_TPS65911=y
CONFIG_SYSRESET_TPS65910=y

6
board/asus/grouper/configs/tilapia.config
View file

@ -1,3 +1,7 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-tilapia-E1565"
CONFIG_GROUPER_MAX77663=y
CONFIG_SYS_PROMPT="Tegra30 (Tilapia) # "
CONFIG_CMD_POWEROFF=y
# CONFIG_MAX77663_GPIO is not set
CONFIG_DM_PMIC_MAX77663=y
CONFIG_DM_REGULATOR_MAX77663=y
CONFIG_SYSRESET_MAX77663=y

2
board/asus/grouper/grouper-spl-max.c
View file

@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <common.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>

2
board/asus/grouper/grouper-spl-ti.c
View file

@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <common.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>

153
board/asus/grouper/grouper.c
View file

@ -7,106 +7,13 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <i2c.h>
#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include "pinmux-config-grouper.h"
#define TPS65911_I2C_ADDRESS 0x2D
#define TPS65911_REG_LDO1 0x30
#define TPS65911_REG_DEVCTRL 0x3F
#define DEVCTRL_PWR_OFF_MASK BIT(7)
#define DEVCTRL_DEV_ON_MASK BIT(2)
#define DEVCTRL_DEV_OFF_MASK BIT(0)
#define MAX77663_I2C_ADDRESS 0x3C
#define MAX77663_REG_SD2 0x18
#define MAX77663_REG_LDO3 0x29
#define MAX77663_REG_ONOFF_CFG1 0x41
#define ONOFF_PWR_OFF BIT(1)
#ifdef CONFIG_CMD_POWEROFF
#ifdef CONFIG_GROUPER_TPS65911
int do_poweroff(struct cmd_tbl *cmdtp,
int flag, int argc, char *const argv[])
{
struct udevice *dev;
uchar data_buffer[1];
int ret;
ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return 0;
}
ret = dm_i2c_read(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
if (ret)
return ret;
data_buffer[0] |= DEVCTRL_PWR_OFF_MASK;
ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
if (ret)
return ret;
data_buffer[0] |= DEVCTRL_DEV_OFF_MASK;
data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK;
ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
if (ret)
return ret;
// wait some time and then print error
mdelay(5000);
printf("Failed to power off!!!\n");
return 1;
}
#endif /* CONFIG_GROUPER_TPS65911 */
#ifdef CONFIG_GROUPER_MAX77663
int do_poweroff(struct cmd_tbl *cmdtp,
int flag, int argc, char *const argv[])
{
struct udevice *dev;
uchar data_buffer[1];
int ret;
ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return 0;
}
ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
if (ret)
return ret;
data_buffer[0] |= ONOFF_PWR_OFF;
ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
if (ret)
return ret;
// wait some time and then print error
mdelay(5000);
printf("Failed to power off!!!\n");
return 1;
}
#endif /* CONFIG_GROUPER_MAX77663 */
#endif /* CONFIG_CMD_POWEROFF */
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
@ -120,64 +27,6 @@ void pinmux_init(void)
ARRAY_SIZE(grouper_padctrl));
}
#ifdef CONFIG_MMC_SDHCI_TEGRA
static void __maybe_unused tps65911_voltage_init(void)
{
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return;
}
/* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */
ret = dm_i2c_reg_write(dev, TPS65911_REG_LDO1, 0xC9);
if (ret)
log_debug("vcore_emmc set failed: %d\n", ret);
}
static void __maybe_unused max77663_voltage_init(void)
{
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return;
}
/* 0x60 for 1.8v, bit7:0 = voltage */
ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60);
if (ret)
log_debug("vdd_1v8_vio set failed: %d\n", ret);
/* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC);
if (ret)
log_debug("vcore_emmc set failed: %d\n", ret);
}
/*
* Routine: pin_mux_mmc
* Description: setup the MMC muxes, power rails, etc.
*/
void pin_mux_mmc(void)
{
#ifdef CONFIG_GROUPER_MAX77663
/* Bring up eMMC power on MAX PMIC */
max77663_voltage_init();
#endif
#ifdef CONFIG_GROUPER_TPS65911
/* Bring up eMMC power on TI PMIC */
tps65911_voltage_init();
#endif
}
#endif /* MMC */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{

10
board/asus/transformer-t30/Kconfig
View file

@ -9,14 +9,4 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "transformer-t30"
config TRANSFORMER_SPI_BOOT
bool "Enable support for SPI based flash"
select TEGRA20_SLINK
select DM_SPI_FLASH
select SPI_FLASH_WINBOND
help
Tegra 3 based Transformers with Windows RT have core
boot sequence (BCT and EBT) on separate SPI FLASH
memory with 4MB size.
endif

2
board/asus/transformer-t30/configs/tf600t.config
View file

@ -1,4 +1,4 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t"
CONFIG_TRANSFORMER_SPI_BOOT=y
CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00

2
board/asus/transformer-t30/transformer-t30-spl.c
View file

@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <common.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>

120
board/asus/transformer-t30/transformer-t30.c
View file

@ -9,71 +9,13 @@
/* T30 Transformers derive from Cardhu board */
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <i2c.h>
#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include "pinmux-config-transformer.h"
#define TPS65911_I2C_ADDRESS 0x2D
#define TPS65911_VDD1 0x21
#define TPS65911_VDD1_OP 0x22
#define TPS65911_LDO1 0x30
#define TPS65911_LDO2 0x31
#define TPS65911_LDO3 0x37
#define TPS65911_LDO5 0x32
#define TPS65911_LDO6 0x35
#define TPS65911_DEVCTRL 0x3F
#define DEVCTRL_PWR_OFF_MASK BIT(7)
#define DEVCTRL_DEV_ON_MASK BIT(2)
#define DEVCTRL_DEV_OFF_MASK BIT(0)
#ifdef CONFIG_CMD_POWEROFF
int do_poweroff(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
struct udevice *dev;
uchar data_buffer[1];
int ret;
ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return 0;
}
ret = dm_i2c_read(dev, TPS65911_DEVCTRL, data_buffer, 1);
if (ret)
return ret;
data_buffer[0] |= DEVCTRL_PWR_OFF_MASK;
ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1);
if (ret)
return ret;
data_buffer[0] |= DEVCTRL_DEV_OFF_MASK;
data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK;
ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1);
if (ret)
return ret;
// wait some time and then print error
mdelay(5000);
printf("Failed to power off!!!\n");
return 1;
}
#endif
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
@ -92,66 +34,6 @@ void pinmux_init(void)
}
}
#ifdef CONFIG_MMC_SDHCI_TEGRA
static void tps65911_voltage_init(void)
{
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return;
}
/* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */
ret = dm_i2c_reg_write(dev, TPS65911_LDO1, 0xc9);
if (ret)
log_debug("vcore_emmc set failed: %d\n", ret);
if (of_machine_is_compatible("asus,tf600t")) {
/* TPS659110: VDD1_REG = 1.2v, ACTIVE to backlight */
ret = dm_i2c_reg_write(dev, TPS65911_VDD1_OP, 0x33);
if (ret)
log_debug("vdd_bl set failed: %d\n", ret);
ret = dm_i2c_reg_write(dev, TPS65911_VDD1, 0x0d);
if (ret)
log_debug("vdd_bl enable failed: %d\n", ret);
/* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 VIO */
ret = dm_i2c_reg_write(dev, TPS65911_LDO5, 0x65);
if (ret)
log_debug("vdd_usd set failed: %d\n", ret);
/* TPS659110: LDO6_REG = 1.2v, ACTIVE to MIPI */
ret = dm_i2c_reg_write(dev, TPS65911_LDO6, 0x11);
if (ret)
log_debug("vdd_mipi set failed: %d\n", ret);
} else {
/* TPS659110: LDO2_REG = 3.1v, ACTIVE to SDMMC1 */
ret = dm_i2c_reg_write(dev, TPS65911_LDO2, 0xb9);
if (ret)
log_debug("vdd_usd set failed: %d\n", ret);
/* TPS659110: LDO3_REG = 3.1v, ACTIVE to SDMMC1 VIO */
ret = dm_i2c_reg_write(dev, TPS65911_LDO3, 0x5d);
if (ret)
log_debug("vddio_usd set failed: %d\n", ret);
}
}
/*
* Routine: pin_mux_mmc
* Description: setup the MMC muxes, power rails, etc.
*/
void pin_mux_mmc(void)
{
/* Bring up uSD and eMMC power */
tps65911_voltage_init();
}
#endif /* MMC */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{

1
board/hisilicon/hikey/MAINTAINERS
View file

@ -2,5 +2,6 @@ HIKEY BOARD
M: Peter Griffin <peter.griffin@linaro.org>
S: Maintained
F: board/hisilicon/hikey
F: doc/board/hisilicon/hikey.rst
F: include/configs/hikey.h
F: configs/hikey_defconfig

227
board/hisilicon/hikey/README
View file

@ -1,227 +0,0 @@
Introduction
============
HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: -
* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
* ARM Mali 450-MP4 GPU
* 1GB 800MHz LPDDR3 DRAM
* 4GB eMMC Flash Storage
* microSD
* 802.11a/b/g/n WiFi, Bluetooth
The HiKey schematic can be found here: -
https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_schematics_LeMaker_version_Rev_A1.pdf
The SoC datasheet can be found here: -
https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Currently the u-boot port supports: -
* USB
* eMMC
* SD card
* GPIO
The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
U-Boot as the bl33.bin executable.
Compile from source
===================
First get all the sources
> mkdir -p ~/hikey/src ~/hikey/bin
> cd ~/hikey/src
> git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
> git clone https://github.com/ARM-software/arm-trusted-firmware
> git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
> git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
> git clone https://github.com/96boards-hikey/atf-fastboot
> wget https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/hisi-idt.py
Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
The latest version can be obtained from the OpenPlatformPkg repo.
> cp OpenPlatformPkg/Platforms/Hisilicon/HiKey/Binary/mcuimage.bin ~/hikey/bin/
Get nvme.img binary
> wget -P ~/hikey/bin https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/nvme.img
Compile U-Boot
==============
> cd ~/hikey/src/u-boot
> make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
> make CROSS_COMPILE=aarch64-linux-gnu-
> cp u-boot.bin ~/hikey/bin
Compile ARM Trusted Firmware (ATF)
==================================
> cd ~/hikey/src/arm-trusted-firmware
> make CROSS_COMPILE=aarch64-linux-gnu- all fip \
SCP_BL2=~/hikey/bin/mcuimage.bin \
BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
Copy the resulting FIP binary
> cp build/hikey/debug/fip.bin ~/hikey/bin
Compile ATF Fastboot
====================
> cd ~/hikey/src/atf-fastboot
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=hikey DEBUG=1
Compile l-loader
================
> cd ~/hikey/src/l-loader
> ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl1.bin
> ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl2.bin
> ln -sf ~/hikey/src/atf-fastboot/build/hikey/debug/bl1.bin fastboot.bin
> make hikey PTABLE_LST=aosp-8g
Copy the resulting binaries
> cp *.img ~/hikey/bin
> cp l-loader.bin ~/hikey/bin
> cp recovery.bin ~/hikey/bin
These instructions are adapted from
https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey.rst
FLASHING
========
1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
the hisi-idt.py utility. Then connect a USB A to B mini cable from your PC to the USB OTG port of HiKey and execute the below command.
The command below assumes HiKey enumerated as the first USB serial port
> sudo python ~/hikey/src/hisi-idt.py -d /dev/ttyUSB0 --img1 ~/hikey/bin/recovery.bin
2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device.
> sudo fastboot devices
0123456789ABCDEF fastboot
3. Flash the images
> sudo fastboot flash ptable ~/hikey/bin/prm_ptable.img
> sudo fastboot flash loader ~/hikey/bin/l-loader.bin
> sudo fastboot flash fastboot ~/hikey/bin/fip.bin
> sudo fastboot flash nvme ~/hikey/bin/nvme.img
4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
have ATF, booting u-boot from eMMC.
Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
will get 'dwc_otg_core_host_init: Timeout!' errors.
See working boot trace below on UART3 available at Low Speed Expansion header: -
NOTICE: BL2: v1.5(debug):v1.5-694-g6d4f6aea
NOTICE: BL2: Built : 09:21:42, Aug 29 2018
INFO: BL2: Doing platform setup
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 150mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 266mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 400mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 533mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 800mhz
INFO: Samsung DDR
INFO: ddr test value:0xa5a55a5a
INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
INFO: BL2: TrustZone: protecting 4194304 bytes of memory at 0x3e800000
INFO: [BDID] [fff91c18] midr: 0x410fd033
INFO: init_acpu_dvfs: pmic version 17
INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
INFO: acpu_dvfs_volt_init: success!
INFO: acpu_dvfs_set_freq: support freq num is 5
INFO: acpu_dvfs_set_freq: start prof is 0x4
INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
INFO: acpu_dvfs_set_freq: voltage:
INFO: - 0: 0x49
INFO: - 1: 0x49
INFO: - 2: 0x50
INFO: - 3: 0x60
INFO: - 4: 0x78
NOTICE: acpu_dvfs_set_freq: set acpu freq success!INFO: BL2: Loading image id 2
INFO: Loading image id=2 at address 0x1000000
INFO: Image id=2 loaded: 0x1000000 - 0x1023d00
INFO: hisi_mcu_load_image: mcu sections 0:
INFO: hisi_mcu_load_image: src = 0x1000200
INFO: hisi_mcu_load_image: dst = 0xf6000000
INFO: hisi_mcu_load_image: size = 31184
INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x8000 0x3701 0x7695 0x7689
INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x8000 0x3701 0x7695 0x7689
INFO: hisi_mcu_load_image: mcu sections 1:
INFO: hisi_mcu_load_image: src = 0x1007bd0
INFO: hisi_mcu_load_image: dst = 0x5e00000
INFO: hisi_mcu_load_image: size = 93828
INFO: hisi_mcu_load_image: [SRC 0x1007bd0] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
INFO: hisi_mcu_load_image: [DST 0x5e00000] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
INFO: hisi_mcu_load_image: mcu sections 2:
INFO: hisi_mcu_load_image: src = 0x101ea54
INFO: hisi_mcu_load_image: dst = 0x5e16e84
INFO: hisi_mcu_load_image: size = 15428
INFO: hisi_mcu_load_image: [SRC 0x101ea54] 0x9 0x1020640 0x10001 0x8f0d180
INFO: hisi_mcu_load_image: [DST 0x5e16e84] 0x9 0x1020640 0x10001 0x8f0d180
INFO: hisi_mcu_load_image: mcu sections 3:
INFO: hisi_mcu_load_image: src = 0x1022698
INFO: hisi_mcu_load_image: dst = 0x5e22a10
INFO: hisi_mcu_load_image: size = 3060
INFO: hisi_mcu_load_image: [SRC 0x1022698] 0x0 0x0 0x0 0x0
INFO: hisi_mcu_load_image: [DST 0x5e22a10] 0x0 0x0 0x0 0x0
INFO: hisi_mcu_load_image: mcu sections 4:
INFO: hisi_mcu_load_image: src = 0x102328c
INFO: hisi_mcu_load_image: dst = 0x5e23604
INFO: hisi_mcu_load_image: size = 2616
INFO: hisi_mcu_load_image: [SRC 0x102328c] 0xf80000a0 0x0 0xf80000ac 0x0
INFO: hisi_mcu_load_image: [DST 0x5e23604] 0xf80000a0 0x0 0xf80000ac 0x0
INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
INFO: plat_hikey_bl2_handle_scp_bl2: MCU PC is at 0x42933301
INFO: plat_hikey_bl2_handle_scp_bl2: AO_SC_PERIPH_CLKSTAT4 is 0x3b018f09
WARNING: BL2: Platform setup already done!!
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xf9858000
INFO: Image id=3 loaded: 0xf9858000 - 0xf9860058
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x35000000
INFO: Image id=5 loaded: 0x35000000 - 0x35061cd2
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xf9858000
INFO: SPSR = 0x3cd
NOTICE: BL31: v1.5(debug):v1.5-694-g6d4f6aea
NOTICE: BL31: Built : 09:21:44, Aug 29 2018
WARNING: Using deprecated integer interrupt array in gicv2_driver_data_t
WARNING: Please migrate to using an interrupt_prop_t array
INFO: ARM GICv2 driver initialized
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied
INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x35000000
INFO: SPSR = 0x3c9
U-Boot 2018.09-rc1 (Aug 22 2018 - 14:55:49 +0530)hikey
DRAM: 990 MiB
HI6553 PMIC init
MMC: config_sd_carddetect: SD card present
Hisilicon DWMMC: 0, Hisilicon DWMMC: 1
Loading Environment from FAT... Unable to use mmc 1:1... Failed (-5)
In: uart@f7113000
Out: uart@f7113000
Err: uart@f7113000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
starting USB...
USB0: scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found

1
board/hisilicon/hikey960/MAINTAINERS
View file

@ -2,5 +2,6 @@ HIKEY960 BOARD
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: board/hisilicon/hikey960
F: doc/board/hisilicon/hikey960.rst
F: include/configs/hikey960.h
F: configs/hikey960_defconfig

247
board/hisilicon/hikey960/README
View file

@ -1,247 +0,0 @@
Introduction
============
HiKey960 is one of the 96Boards Consumer Edition board from HiSilicon.
The board/SoC has: -
* HiSilicon Kirin960 (HI3660) SoC with 4xCortex-A73 and 4xCortex-A53
* ARM Mali G71 MP8 GPU
* 3GB LPDDR4 SDRAM
* 32GB UFS Flash Storage
* microSD
* 802.11a/b/g/n WiFi, Bluetooth
More information about this board can be found in 96Boards website:
https://www.96boards.org/product/hikey960/
Currently the u-boot port supports: -
* SD card
Compile from source
===================
First get all the sources
> mkdir -p ~/hikey960/src ~/hikey960/bin
> cd ~/hikey960/src
> git clone https://github.com/ARM-software/arm-trusted-firmware
> git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
> git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
> wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/config
> wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_usb_xloader.img
> wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_uce_boot.img
> wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_xloader.img
> wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/recovery.bin
> wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hikey_idt
Get the SCP_BL2 lpm3.img binary. It is shipped as part of the UEFI source.
The latest version can be obtained from the OpenPlatformPkg repo.
> cp OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Binary/lpm3.img ~/hikey960/bin/
Compile U-Boot
==============
> cd ~/hikey960/src/u-boot
> make CROSS_COMPILE=aarch64-linux-gnu- hikey960_defconfig
> make CROSS_COMPILE=aarch64-linux-gnu-
> cp u-boot.bin ~/hikey960/bin/
Compile ARM Trusted Firmware (ATF)
==================================
> cd ~/hikey960/src/arm-trusted-firmware
> make CROSS_COMPILE=aarch64-linux-gnu- all fip \
SCP_BL2=~/hikey960/bin/lpm3.img \
BL33=~/hikey960/bin/u-boot.bin DEBUG=1 PLAT=hikey960
Copy the resulting FIP binary
> cp build/hikey960/debug/fip.bin ~/hikey960/bin
Compile l-loader
================
> cd ~/hikey960/src/l-loader
> ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl1.bin
> ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl2.bin
> ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/fip.bin
> ln -sf ~/hikey960/bin/u-boot.bin
> make hikey960 PTABLE_LST=linux-32g NS_BL1U=u-boot.bin
Copy the resulting binaries
> cp *.img ~/hikey960/bin
> cp l-loader.bin ~/hikey960/bin
These instructions are adapted from
https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey960.rst
Setup Console
=============
Install ser2net. Use telnet as the console since UEFI in recovery mode
output window fails to display in minicom.
> sudo apt-get install ser2net
Configure ser2net
> sudo vi /etc/ser2net.conf
Append one line for serial-over-USB in #ser2net.conf
> 2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
Start ser2net
> sudo killall ser2net
> sudo ser2net -u
Open the console.
> telnet localhost 2004
And you could open the console remotely, too.
Flashing
========
1. Boot Hikey960 into recovery mode as per the below document:
https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/installation/board-recovery.md
Once Hikey960 is in recovery mode, flash the recovery binary:
> cd ~/hikey960/src
> chmod +x ./hikey_idt
> sudo ./hikey_idt -c config -p /dev/ttyUSB1
Now move to the Hikey960 console and press `f` during UEFI boot. This
will allow the board to boot into fastboot mode. Once the board is in
fastboot mode, you should see the ID of the HiKey960 board using the
following command
> sudo fastboot devices
1ED3822A018E3372 fastboot
3. Flash the images
Now, the images can be flashed using fastboot:
> sudo fastboot flash ptable ~/hikey960/bin/prm_ptable.img
> sudo fastboot flash xloader ~/hikey960/bin/hisi-sec_xloader.img
> sudo fastboot flash fastboot ~/hikey960/bin/l-loader.bin
> sudo fastboot flash fip ~/hikey960/bin/fip.bin
4. Set the "Boot Mode" switch to OFF position for normal boot mode.
Then power on HiKey960
Observe the console traces using UART6 on the Low Speed Expansion header:
NOTICE: BL2: v2.1(debug):v2.1-531-g3ee48f40
NOTICE: BL2: Built : 18:15:58, Aug 2 2019
INFO: BL2: Doing platform setup
INFO: UFS LUN0 contains 1024 blocks with 4096-byte size
INFO: UFS LUN1 contains 1024 blocks with 4096-byte size
INFO: UFS LUN2 contains 2048 blocks with 4096-byte size
INFO: UFS LUN3 contains 7805952 blocks with 4096-byte size
INFO: ufs: change power mode success
INFO: BL2: Loading image id 2
INFO: Loading image id=2 at address 0x89c80000
INFO: Image id=2 loaded: 0x89c80000 - 0x89cb5088
INFO: BL2: Initiating SCP_BL2 transfer to SCP
INFO: BL2: SCP_BL2: 0x89c80000@0x35088
INFO: BL2: SCP_BL2 HEAD:
INFO: BL2: SCP_BL2 0x7000 0x179 0x159 0x149
INFO: BL2: SCP_BL2 0x189 0x18b 0x18d 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x18f
INFO: BL2: SCP_BL2 0x191 0x0 0x193 0x195
INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
INFO: BL2: SCP_BL2 0x4d454355 0x43494741 0x424d554e 0x21215245
INFO: BL2: SCP_BL2 0x4a054904 0x42912000 0xf841bfbc 0xe7fa0b04
INFO: BL2: SCP_BL2 0xb88cf000 0x3b18 0x3d1c 0x6809493e
INFO: BL2: SCP_BL2 0x4613680a 0x201f102 0xf0002a04 0x600a804c
INFO: BL2: SCP_BL2 0x204f04f 0xf203fb02 0xf102440a 0x60100204
INFO: BL2: SCP_BL2 0x160f04f 0xf103fb01 0x68004834 0x61044408
INFO: BL2: SCP_BL2 0x61866145 0xf8c061c7 0xf8c08020 0xf8c09024
INFO: BL2: SCP_BL2 0xf8c0a028 0xf3efb02c 0xf3ef8208 0x68118309
INFO: BL2: SCP_BL2 0xf1026401 0xf0110204 0xbf070f04 0x46113220
INFO: BL2: SCP_BL2 TAIL:
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x19cad151 0x19b80040 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 transferred to SCP
INFO: start fw loading
INFO: fw load success
WARNING: BL2: Platform setup already done!!
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0x1ac58000
INFO: Image id=3 loaded: 0x1ac58000 - 0x1ac63024
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x1ac98000
INFO: Image id=5 loaded: 0x1ac98000 - 0x1ad0819c
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0x1ac58000
INFO: SPSR = 0x3cd
NOTICE: BL31: v2.1(debug):v2.1-531-g3ee48f40
NOTICE: BL31: Built : 18:16:01, Aug 2 2019
INFO: ARM GICv2 driver initialized
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
INFO: plat_setup_psci_ops: sec_entrypoint=0x1ac580fc
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x1ac98000
INFO: SPSR = 0x3c9
U-Boot 2019.07-00628-g286f05a6fc-dirty (Aug 02 2019 - 17:14:05 +0530)
Hikey960
DRAM: 3 GiB
PSCI: v1.1
MMC: dwmmc1@ff37f000: 0
Loading Environment from EXT4... ** File not found /uboot.env **
** Unable to read "/uboot.env" from mmc0:2 **
In: serial@fff32000
Out: serial@fff32000
Err: serial@fff32000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
201 bytes read in 12 ms (15.6 KiB/s)
1: hikey960-kernel
Retrieving file: /Image
24689152 bytes read in 4377 ms (5.4 MiB/s)
append: earlycon=pl011,mmio32,0xfff32000 console=ttyAMA6,115200 rw root=/dev/mmcblk0p2 rot
Retrieving file: /hi3660-hikey960.dtb
35047 bytes read in 14 ms (2.4 MiB/s)
## Flattened Device Tree blob at 10000000
Booting using the fdt blob at 0x10000000
Using Device Tree in place at 0000000010000000, end 000000001000b8e6
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 5.2.0-03138-gd75da80dce39 (mani@Mani-XPS-13-9360) (gcc versi9
[ 0.000000] Machine model: HiKey960
[ 0.000000] earlycon: pl11 at MMIO32 0x00000000fff32000 (options '')
[ 0.000000] printk: bootconsole [pl11] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:

1
board/hisilicon/poplar/MAINTAINERS
View file

@ -3,5 +3,6 @@ M: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
M: Shawn Guo <shawn.guo@linaro.org>
S: Maintained
F: board/hisilicon/poplar
F: doc/board/hisilicon/poplar.rst
F: include/configs/poplar.h
F: configs/poplar_defconfig

288
board/hisilicon/poplar/README
View file

@ -1,288 +0,0 @@
================================================================================
Board Information
================================================================================
Developed by HiSilicon, the board features the Hi3798C V200 with an
integrated quad-core 64-bit ARM Cortex A53 processor and high
performance Mali T720 GPU, making it capable of running any commercial
set-top solution based on Linux or Android. Its high performance
specification also supports a premium user experience with up to H.265
HEVC decoding of 4K video at 60 frames per second.
SOC Hisilicon Hi3798CV200
CPU Quad-core ARM Cortex-A53 64 bit
DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
USB Two USB 2.0 ports One USB 3.0 ports
CONSOLE USB-micro port for console support
ETHERNET 1 GBe Ethernet
PCIE One PCIe 2.0 interfaces
JTAG 8-Pin JTAG
EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot
DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
WIFI 802.11AC 2*2 with Bluetooth
CONNECTORS One connector for Smart Card One connector for TSI
================================================================================
BUILD INSTRUCTIONS
================================================================================
Note of warning:
================
U-Boot has a *strong* dependency with the l-loader and the arm trusted firmware
repositories.
The boot sequence is:
l-loader --> arm_trusted_firmware --> u-boot
U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
over it. Currently, BL31 is being placed below the kernel text offset (check
poplar.c) but this could change in the future.
The current version of u-boot has been tested with:
- https://github.com/Linaro/poplar-l-loader.git
commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c
Author: Alex Elder <elder@linaro.org>
Date: Fri Jun 16 08:57:59 2017 -0500
l-loader: use external memory region definitions
The ARM Trusted Firmware code now has a header file that collects
all the definitions for the memory regions used for its boot stages.
Include that file where needed, and use the definitions found therein
Signed-off-by: Alex Elder <elder@linaro.org>
- https://github.com/Linaro/poplar-arm-trusted-firmware.git
commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68
Author: Alex Elder <elder@linaro.org>
Date: Fri Jun 16 09:24:50 2017 -0500
poplar: define memory regions in a separate file
Separate the definitions for memory regions used for the BL stage
images and FIP into a new file. The "l-loader" image uses knowledge
of the sizes and locations of these memory regions, and it can now
include this (external) header to get these definitions, rather than
having to make coordinated changes to both code bases.
The new file has a complete set of definitions (more than may be
required by one or the other user). It also includes a summary of
how the boot process works, and how it uses these regions.
It should now be relatively easy to adjust the sizes and locations
of these memory regions, or to add to them (e.g. for TEE).
Signed-off-by: Alex Elder <elder@linaro.org>
Compile from source:
====================
Get all the sources
> mkdir -p ~/poplar/src ~/poplar/bin
> cd ~/poplar/src
> git clone https://github.com/Linaro/poplar-l-loader.git l-loader
> git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf
> git clone https://github.com/Linaro/poplar-u-boot.git u-boot
Make sure you are using the correct branch on each one of these repositories.
The definition of "correct" might change over time (at this moment in time this
would be the "latest" branch).
Compile U-Boot:
===============
Prerequisite:
# sudo apt-get install device-tree-compiler
> cd ~/poplar/src/u-boot
> make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig
> make CROSS_COMPILE=aarch64-linux-gnu-
> cp u-boot.bin ~/poplar/bin
Compile ARM Trusted Firmware (ATF):
===================================
> cd ~/poplar/src/atf
> make CROSS_COMPILE=aarch64-linux-gnu- all fip \
SPD=none BL33=~/poplar/bin/u-boot.bin DEBUG=1 PLAT=poplar
Copy resulting binaries
> cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/
> cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/
Compile l-loader:
=================
> cd ~/poplar/src/l-loader
> make clean
> make CROSS_COMPILE=arm-linux-gnueabi-
Due to BootROM requiremets, rename l-loader.bin to fastboot.bin:
> cp l-loader.bin ~/poplar/bin/fastboot.bin
================================================================================
FLASH INSTRUCTIONS
================================================================================
Two methods:
Using USB debrick support:
Copy fastboot.bin to a FAT partition on the USB drive and reboot the
poplar board while pressing S3(usb_boot).
The system will execute the new u-boot and boot into a shell which you
can then use to write to eMMC.
Using U-BOOT from shell:
1) using AXIS usb ethernet dongle and tftp
2) using FAT formated USB drive
1. TFTP (USB ethernet dongle)
=============================
Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board.
Copy fastboot.bin to your tftp server.
In u-boot make sure your network is properly setup.
Then
=> tftp 0x30000000 fastboot.bin
starting USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
USB1: USB EHCI 1.00
scanning bus 1 for devices... 3 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
scanning usb for ethernet devices... 1 Ethernet Device(s) found
Waiting for Ethernet connection... done.
Using asx0 device
TFTP from server 192.168.1.4; our IP address is 192.168.1.10
Filename 'poplar/fastboot.bin'.
Load address: 0x30000000
Loading: #################################################################
#################################################################
###############################################################
2 MiB/s
done
Bytes transferred = 983040 (f0000 hex)
=> mmc write 0x30000000 0 0x780
MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
=> reset
2. USING USB FAT DRIVE
=======================
Copy fastboot.bin to any partition on a FAT32 formated usb flash drive.
Enter the uboot prompt
=> fatls usb 0:2
983040 fastboot.bin
1 file(s), 0 dir(s)
=> fatload usb 0:2 0x30000000 fastboot.bin
reading fastboot.bin
983040 bytes read in 44 ms (21.3 MiB/s)
=> mmc write 0x30000000 0 0x780
MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
================================================================================
BOOT TRACE
================================================================================
Bootrom start
Boot Media: eMMC
Decrypt auxiliary code ...OK
lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000
Entry boot auxiliary code
Auxiliary code - v1.00
DDR code - V1.1.2 20160205
Build: Mar 24 2016 - 17:09:44
Reg Version: v134
Reg Time: 2016/03/18 09:44:55
Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg
Boot auxiliary code success
Bootrom success
LOADER: Switched to aarch64 mode
LOADER: Entering ARM TRUSTED FIRMWARE
LOADER: CPU0 executes at 0x000ce000
INFO: BL1: 0xe1000 - 0xe7000 [size = 24576]
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60
NOTICE: BL1: Built : 17:51:33, Apr 30 2017
INFO: BL1: RAM 0xe1000 - 0xe7000
INFO: BL1: Loading BL2
INFO: Loading image id=1 at address 0xe9000
INFO: Image id=1 loaded at address 0xe9000, size = 0x5008
NOTICE: BL1: Booting BL2
INFO: Entry point address = 0xe9000
INFO: SPSR = 0x3c5
NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60
NOTICE: BL2: Built : 17:51:33, Apr 30 2017
INFO: BL2: Loading BL31
INFO: Loading image id=3 at address 0x129000
INFO: Image id=3 loaded at address 0x129000, size = 0x8038
INFO: BL2: Loading BL33
INFO: Loading image id=5 at address 0x37000000
INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17
NOTICE: BL1: Booting BL31
INFO: Entry point address = 0x129000
INFO: SPSR = 0x3cd
INFO: Boot bl33 from 0x37000000 for 364311 Bytes
NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60
NOTICE: BL31: Built : 17:51:33, Apr 30 2017
INFO: BL31: Initializing runtime services
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x37000000
INFO: SPSR = 0x3c9
U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar
Model: HiSilicon Poplar Development Board
BOARD: Hisilicon HI3798cv200 Poplar
DRAM: 1 GiB
MMC: Hisilicon DWMMC: 0
In: serial@f8b00000
Out: serial@f8b00000
Err: serial@f8b00000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
starting USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
USB1: USB EHCI 1.00
scanning bus 1 for devices... 4 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
scanning usb for ethernet devices... 1 Ethernet Device(s) found
USB device 0:
Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade
Type: Removable Hard Disk
Capacity: 7632.0 MB = 7.4 GB (15630336 x 512)
... is now current device
Scanning usb 0:1...
=>

2
board/htc/endeavoru/endeavoru-spl.c
View file

@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <common.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>

71
board/htc/endeavoru/endeavoru.c
View file

@ -7,49 +7,12 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <i2c.h>
#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include "pinmux-config-endeavoru.h"
#define TPS80032_CTL1_I2C_ADDR 0x48
#define TPS80032_PHOENIX_DEV_ON 0x25
#define DEVOFF BIT(0)
#define TPS80032_LDO1_CFG_STATE 0x9E
#define TPS80032_LDO1_CFG_VOLTAGE 0x9F
#ifdef CONFIG_CMD_POWEROFF
int do_poweroff(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return 0;
}
ret = dm_i2c_reg_write(dev, TPS80032_PHOENIX_DEV_ON, DEVOFF);
if (ret)
return ret;
// wait some time and then print error
mdelay(5000);
printf("Failed to power off!!!\n");
return 1;
}
#endif
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
@ -60,38 +23,6 @@ void pinmux_init(void)
ARRAY_SIZE(endeavoru_pinmux_common));
}
#ifdef CONFIG_MMC_SDHCI_TEGRA
static void tps80032_voltage_init(void)
{
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev);
if (ret)
log_debug("cannot find PMIC I2C chip\n");
/* TPS80032: LDO1_REG = 1.2v to DSI */
ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_VOLTAGE, 0x03);
if (ret)
log_debug("avdd_dsi_csi voltage set failed: %d\n", ret);
/* TPS80032: LDO1_REG enable */
ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_STATE, 0x01);
if (ret)
log_debug("avdd_dsi_csi enable failed: %d\n", ret);
}
/*
* Routine: pin_mux_mmc
* Description: setup the MMC muxes, power rails, etc.
*/
void pin_mux_mmc(void)
{
/* Bring up DSI power */
tps80032_voltage_init();
}
#endif /* MMC */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{

2
board/lg/x3-t30/x3-t30-spl.c
View file

@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <common.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>

93
board/lg/x3-t30/x3-t30.c
View file

@ -7,61 +7,14 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <i2c.h>
#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/fuse.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include "pinmux-config-x3.h"
#define MAX77663_I2C_ADDR 0x1C
#define MAX77663_REG_SD2 0x18
#define MAX77663_REG_LDO2 0x27
#define MAX77663_REG_LDO3 0x29
#define MAX77663_REG_LDO5 0x2D
#define MAX77663_REG_ONOFF_CFG1 0x41
#define ONOFF_PWR_OFF BIT(1)
#ifdef CONFIG_CMD_POWEROFF
int do_poweroff(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
struct udevice *dev;
uchar data_buffer[1];
int ret;
ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return 0;
}
ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
if (ret)
return ret;
data_buffer[0] |= ONOFF_PWR_OFF;
ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
if (ret)
return ret;
/* wait some time and then print error */
mdelay(5000);
printf("Failed to power off!!!\n");
return 1;
}
#endif
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
@ -82,50 +35,6 @@ void pinmux_init(void)
#endif
}
#ifdef CONFIG_MMC_SDHCI_TEGRA
static void max77663_voltage_init(void)
{
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return;
}
/* 0x60 for 1.8v, bit7:0 = voltage */
ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60);
if (ret)
log_debug("vdd_1v8_vio set failed: %d\n", ret);
/* 0xF2 for 3.30v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO2, 0xF2);
if (ret)
log_debug("avdd_usb set failed: %d\n", ret);
/* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC);
if (ret)
log_debug("vdd_usd set failed: %d\n", ret);
/* 0xE9 for 2.85v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO5, 0xE9);
if (ret)
log_debug("vcore_emmc set failed: %d\n", ret);
}
/*
* Routine: pin_mux_mmc
* Description: setup the MMC muxes, power rails, etc.
*/
void pin_mux_mmc(void)
{
/* Bring up uSD and eMMC power */
max77663_voltage_init();
}
#endif /* MMC */
int nvidia_board_init(void)
{
/* Set up panel bridge clocks */

5
cmd/eficonfig.c
View file

@ -528,7 +528,10 @@ struct efi_device_path *eficonfig_create_device_path(struct efi_device_path *dp_
p += fp_size;
*((struct efi_device_path *)p) = END;
dp = efi_dp_append(dp_volume, (struct efi_device_path *)buf);
dp = efi_dp_shorten(dp_volume);
if (!dp)
dp = dp_volume;
dp = efi_dp_append(dp, &fp->dp);
free(buf);
return dp;

4
configs/endeavoru_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
@ -61,10 +62,13 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_TPS80031=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_TPS80031=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET_TPS80031=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y

1
configs/grouper_common_defconfig
View file

@ -43,6 +43,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

5
configs/transformer_t30_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
@ -65,10 +66,14 @@ CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_TPS65910=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_TPS65911=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
CONFIG_SYSRESET_TPS65910=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y

4
configs/x3_t30_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
@ -64,11 +65,14 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77663=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_MAX77663=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
CONFIG_SYSRESET_MAX77663=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y

261
doc/board/hisilicon/hikey.rst Normal file
View file

@ -0,0 +1,261 @@
.. SPDX-License-Identifier: GPL-2.0-or-later
HiKey board
###########
Introduction
============
HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has:
* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
* ARM Mali 450-MP4 GPU
* 1GB 800MHz LPDDR3 DRAM
* 4GB eMMC Flash Storage
* microSD
* 802.11a/b/g/n WiFi, Bluetooth
The HiKey schematic can be found here:
https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_schematics_LeMaker_version_Rev_A1.pdf
The SoC datasheet can be found here:
https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Currently the u-boot port supports:
* USB
* eMMC
* SD card
* GPIO
The HiKey U-Boot port has been tested with l-loader, booting ATF, which then
boots U-Boot as the bl33.bin executable.
Compile from source
===================
First get all the sources
.. code-block:: bash
mkdir -p ~/hikey/src ~/hikey/bin
cd ~/hikey/src
git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
git clone https://github.com/ARM-software/arm-trusted-firmware
git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
git clone https://github.com/96boards-hikey/atf-fastboot
wget https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/hisi-idt.py
Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
The latest version can be obtained from the OpenPlatformPkg repo.
.. code-block:: bash
cp OpenPlatformPkg/Platforms/Hisilicon/HiKey/Binary/mcuimage.bin ~/hikey/bin/
Get nvme.img binary
.. code-block:: bash
wget -P ~/hikey/bin https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/nvme.img
Compile U-Boot
==============
.. code-block:: bash
cd ~/hikey/src/u-boot
make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
make CROSS_COMPILE=aarch64-linux-gnu-
cp u-boot.bin ~/hikey/bin
Compile ARM Trusted Firmware (ATF)
==================================
.. code-block:: bash
cd ~/hikey/src/arm-trusted-firmware
make CROSS_COMPILE=aarch64-linux-gnu- all fip \
SCP_BL2=~/hikey/bin/mcuimage.bin \
BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
Copy the resulting FIP binary
.. code-block:: bash
cp build/hikey/debug/fip.bin ~/hikey/bin
Compile ATF Fastboot
====================
.. code-block:: bash
cd ~/hikey/src/atf-fastboot
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=hikey DEBUG=1
Compile l-loader
================
.. code-block:: bash
cd ~/hikey/src/l-loader
ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl1.bin
ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl2.bin
ln -sf ~/hikey/src/atf-fastboot/build/hikey/debug/bl1.bin fastboot.bin
make hikey PTABLE_LST=aosp-8g
Copy the resulting binaries
.. code-block:: bash
cp *.img ~/hikey/bin
cp l-loader.bin ~/hikey/bin
cp recovery.bin ~/hikey/bin
These instructions are adapted from
https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey.rst
Flashing
========
1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
the hisi-idt.py utility. Then connect a USB A to B mini cable from your PC to the USB OTG port of HiKey and execute the below command.
The command below assumes HiKey enumerated as the first USB serial port
.. code-block:: bash
sudo python ~/hikey/src/hisi-idt.py -d /dev/ttyUSB0 --img1 ~/hikey/bin/recovery.bin
2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device.
.. code-block::
sudo fastboot devices
0123456789ABCDEF fastboot
3. Flash the images
.. code-block::
sudo fastboot flash ptable ~/hikey/bin/prm_ptable.img
sudo fastboot flash loader ~/hikey/bin/l-loader.bin
sudo fastboot flash fastboot ~/hikey/bin/fip.bin
sudo fastboot flash nvme ~/hikey/bin/nvme.img
4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
have ATF, booting u-boot from eMMC.
Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
will get 'dwc_otg_core_host_init: Timeout!' errors.
See working boot trace below on UART3 available at Low Speed Expansion header::
NOTICE: BL2: v1.5(debug):v1.5-694-g6d4f6aea
NOTICE: BL2: Built : 09:21:42, Aug 29 2018
INFO: BL2: Doing platform setup
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 150mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 266mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 400mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 533mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 800mhz
INFO: Samsung DDR
INFO: ddr test value:0xa5a55a5a
INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
INFO: BL2: TrustZone: protecting 4194304 bytes of memory at 0x3e800000
INFO: [BDID] [fff91c18] midr: 0x410fd033
INFO: init_acpu_dvfs: pmic version 17
INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
INFO: acpu_dvfs_volt_init: success!
INFO: acpu_dvfs_set_freq: support freq num is 5
INFO: acpu_dvfs_set_freq: start prof is 0x4
INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
INFO: acpu_dvfs_set_freq: voltage:
INFO: - 0: 0x49
INFO: - 1: 0x49
INFO: - 2: 0x50
INFO: - 3: 0x60
INFO: - 4: 0x78
NOTICE: acpu_dvfs_set_freq: set acpu freq success!INFO: BL2: Loading image id 2
INFO: Loading image id=2 at address 0x1000000
INFO: Image id=2 loaded: 0x1000000 - 0x1023d00
INFO: hisi_mcu_load_image: mcu sections 0:
INFO: hisi_mcu_load_image: src = 0x1000200
INFO: hisi_mcu_load_image: dst = 0xf6000000
INFO: hisi_mcu_load_image: size = 31184
INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x8000 0x3701 0x7695 0x7689
INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x8000 0x3701 0x7695 0x7689
INFO: hisi_mcu_load_image: mcu sections 1:
INFO: hisi_mcu_load_image: src = 0x1007bd0
INFO: hisi_mcu_load_image: dst = 0x5e00000
INFO: hisi_mcu_load_image: size = 93828
INFO: hisi_mcu_load_image: [SRC 0x1007bd0] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
INFO: hisi_mcu_load_image: [DST 0x5e00000] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
INFO: hisi_mcu_load_image: mcu sections 2:
INFO: hisi_mcu_load_image: src = 0x101ea54
INFO: hisi_mcu_load_image: dst = 0x5e16e84
INFO: hisi_mcu_load_image: size = 15428
INFO: hisi_mcu_load_image: [SRC 0x101ea54] 0x9 0x1020640 0x10001 0x8f0d180
INFO: hisi_mcu_load_image: [DST 0x5e16e84] 0x9 0x1020640 0x10001 0x8f0d180
INFO: hisi_mcu_load_image: mcu sections 3:
INFO: hisi_mcu_load_image: src = 0x1022698
INFO: hisi_mcu_load_image: dst = 0x5e22a10
INFO: hisi_mcu_load_image: size = 3060
INFO: hisi_mcu_load_image: [SRC 0x1022698] 0x0 0x0 0x0 0x0
INFO: hisi_mcu_load_image: [DST 0x5e22a10] 0x0 0x0 0x0 0x0
INFO: hisi_mcu_load_image: mcu sections 4:
INFO: hisi_mcu_load_image: src = 0x102328c
INFO: hisi_mcu_load_image: dst = 0x5e23604
INFO: hisi_mcu_load_image: size = 2616
INFO: hisi_mcu_load_image: [SRC 0x102328c] 0xf80000a0 0x0 0xf80000ac 0x0
INFO: hisi_mcu_load_image: [DST 0x5e23604] 0xf80000a0 0x0 0xf80000ac 0x0
INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
INFO: plat_hikey_bl2_handle_scp_bl2: MCU PC is at 0x42933301
INFO: plat_hikey_bl2_handle_scp_bl2: AO_SC_PERIPH_CLKSTAT4 is 0x3b018f09
WARNING: BL2: Platform setup already done!!
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xf9858000
INFO: Image id=3 loaded: 0xf9858000 - 0xf9860058
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x35000000
INFO: Image id=5 loaded: 0x35000000 - 0x35061cd2
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xf9858000
INFO: SPSR = 0x3cd
NOTICE: BL31: v1.5(debug):v1.5-694-g6d4f6aea
NOTICE: BL31: Built : 09:21:44, Aug 29 2018
WARNING: Using deprecated integer interrupt array in gicv2_driver_data_t
WARNING: Please migrate to using an interrupt_prop_t array
INFO: ARM GICv2 driver initialized
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied
INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x35000000
INFO: SPSR = 0x3c9
U-Boot 2018.09-rc1 (Aug 22 2018 - 14:55:49 +0530)hikey
DRAM: 990 MiB
HI6553 PMIC init
MMC: config_sd_carddetect: SD card present
Hisilicon DWMMC: 0, Hisilicon DWMMC: 1
Loading Environment from FAT... Unable to use mmc 1:1... Failed (-5)
In: uart@f7113000
Out: uart@f7113000
Err: uart@f7113000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
starting USB...
USB0: scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found

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.. SPDX-License-Identifier: GPL-2.0-or-later
HiKey960 board
##############
Introduction
============
HiKey960 is one of the 96Boards Consumer Edition board from HiSilicon.
The board/SoC has:
* HiSilicon Kirin960 (HI3660) SoC with 4xCortex-A73 and 4xCortex-A53
* ARM Mali G71 MP8 GPU
* 3GB LPDDR4 SDRAM
* 32GB UFS Flash Storage
* microSD
* 802.11a/b/g/n WiFi, Bluetooth
More information about this board can be found in 96Boards website:
https://www.96boards.org/product/hikey960/
Currently the u-boot port supports:
* SD card
Compile from source
===================
First get all the sources
.. code-block:: bash
mkdir -p ~/hikey960/src ~/hikey960/bin
cd ~/hikey960/src
git clone https://github.com/ARM-software/arm-trusted-firmware
git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/config
wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_usb_xloader.img
wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_uce_boot.img
wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_xloader.img
wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/recovery.bin
wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hikey_idt
Get the SCP_BL2 lpm3.img binary. It is shipped as part of the UEFI source.
The latest version can be obtained from the OpenPlatformPkg repo.
.. code-block:: bash
cp OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Binary/lpm3.img ~/hikey960/bin/
Compile U-Boot
==============
.. code-block:: bash
cd ~/hikey960/src/u-boot
make CROSS_COMPILE=aarch64-linux-gnu- hikey960_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
cp u-boot.bin ~/hikey960/bin/
Compile ARM Trusted Firmware (ATF)
==================================
.. code-block:: bash
cd ~/hikey960/src/arm-trusted-firmware
make CROSS_COMPILE=aarch64-linux-gnu- all fip \
SCP_BL2=~/hikey960/bin/lpm3.img \
BL33=~/hikey960/bin/u-boot.bin DEBUG=1 PLAT=hikey960
Copy the resulting FIP binary
.. code-block:: bash
cp build/hikey960/debug/fip.bin ~/hikey960/bin
Compile l-loader
================
.. code-block:: bash
cd ~/hikey960/src/l-loader
ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl1.bin
ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl2.bin
ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/fip.bin
ln -sf ~/hikey960/bin/u-boot.bin
make hikey960 PTABLE_LST=linux-32g NS_BL1U=u-boot.bin
Copy the resulting binaries
.. code-block:: bash
cp *.img ~/hikey960/bin
cp l-loader.bin ~/hikey960/bin
These instructions are adapted from
https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey960.rst
Setup console
=============
Install ser2net. Use telnet as the console since UEFI in recovery mode
output window fails to display in minicom.
.. code-block:: bash
sudo apt-get install ser2net
Configure ser2net
.. code-block:: bash
sudo vi /etc/ser2net.conf
Append one line for serial-over-USB in #ser2net.conf
2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
Start ser2net
.. code-block:: bash
sudo killall ser2net
sudo ser2net -u
Open the console.
.. code-block:: bash
telnet localhost 2004
And you could open the console remotely, too.
Flashing
========
1. Boot Hikey960 into recovery mode as per the below document:
https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/installation/board-recovery.md
Once Hikey960 is in recovery mode, flash the recovery binary:
.. code-block:: bash
cd ~/hikey960/src
chmod +x ./hikey_idt
sudo ./hikey_idt -c config -p /dev/ttyUSB1
Now move to the Hikey960 console and press `f` during UEFI boot. This
will allow the board to boot into fastboot mode. Once the board is in
fastboot mode, you should see the ID of the HiKey960 board using the
following command
.. code-block:: bash
sudo fastboot devices
1ED3822A018E3372 fastboot
3. Flash the images
Now, the images can be flashed using fastboot:
.. code-block:: bash
sudo fastboot flash ptable ~/hikey960/bin/prm_ptable.img
sudo fastboot flash xloader ~/hikey960/bin/hisi-sec_xloader.img
sudo fastboot flash fastboot ~/hikey960/bin/l-loader.bin
sudo fastboot flash fip ~/hikey960/bin/fip.bin
4. Set the "Boot Mode" switch to OFF position for normal boot mode.
Then power on HiKey960
Observe the console traces using UART6 on the Low Speed Expansion header::
NOTICE: BL2: v2.1(debug):v2.1-531-g3ee48f40
NOTICE: BL2: Built : 18:15:58, Aug 2 2019
INFO: BL2: Doing platform setup
INFO: UFS LUN0 contains 1024 blocks with 4096-byte size
INFO: UFS LUN1 contains 1024 blocks with 4096-byte size
INFO: UFS LUN2 contains 2048 blocks with 4096-byte size
INFO: UFS LUN3 contains 7805952 blocks with 4096-byte size
INFO: ufs: change power mode success
INFO: BL2: Loading image id 2
INFO: Loading image id=2 at address 0x89c80000
INFO: Image id=2 loaded: 0x89c80000 - 0x89cb5088
INFO: BL2: Initiating SCP_BL2 transfer to SCP
INFO: BL2: SCP_BL2: 0x89c80000@0x35088
INFO: BL2: SCP_BL2 HEAD:
INFO: BL2: SCP_BL2 0x7000 0x179 0x159 0x149
INFO: BL2: SCP_BL2 0x189 0x18b 0x18d 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x18f
INFO: BL2: SCP_BL2 0x191 0x0 0x193 0x195
INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
INFO: BL2: SCP_BL2 0x4d454355 0x43494741 0x424d554e 0x21215245
INFO: BL2: SCP_BL2 0x4a054904 0x42912000 0xf841bfbc 0xe7fa0b04
INFO: BL2: SCP_BL2 0xb88cf000 0x3b18 0x3d1c 0x6809493e
INFO: BL2: SCP_BL2 0x4613680a 0x201f102 0xf0002a04 0x600a804c
INFO: BL2: SCP_BL2 0x204f04f 0xf203fb02 0xf102440a 0x60100204
INFO: BL2: SCP_BL2 0x160f04f 0xf103fb01 0x68004834 0x61044408
INFO: BL2: SCP_BL2 0x61866145 0xf8c061c7 0xf8c08020 0xf8c09024
INFO: BL2: SCP_BL2 0xf8c0a028 0xf3efb02c 0xf3ef8208 0x68118309
INFO: BL2: SCP_BL2 0xf1026401 0xf0110204 0xbf070f04 0x46113220
INFO: BL2: SCP_BL2 TAIL:
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x19cad151 0x19b80040 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
INFO: BL2: SCP_BL2 transferred to SCP
INFO: start fw loading
INFO: fw load success
WARNING: BL2: Platform setup already done!!
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0x1ac58000
INFO: Image id=3 loaded: 0x1ac58000 - 0x1ac63024
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x1ac98000
INFO: Image id=5 loaded: 0x1ac98000 - 0x1ad0819c
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0x1ac58000
INFO: SPSR = 0x3cd
NOTICE: BL31: v2.1(debug):v2.1-531-g3ee48f40
NOTICE: BL31: Built : 18:16:01, Aug 2 2019
INFO: ARM GICv2 driver initialized
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
INFO: plat_setup_psci_ops: sec_entrypoint=0x1ac580fc
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x1ac98000
INFO: SPSR = 0x3c9
U-Boot 2019.07-00628-g286f05a6fc-dirty (Aug 02 2019 - 17:14:05 +0530)
Hikey960
DRAM: 3 GiB
PSCI: v1.1
MMC: dwmmc1@ff37f000: 0
Loading Environment from EXT4... ** File not found /uboot.env **
** Unable to read "/uboot.env" from mmc0:2 **
In: serial@fff32000
Out: serial@fff32000
Err: serial@fff32000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
201 bytes read in 12 ms (15.6 KiB/s)
1: hikey960-kernel
Retrieving file: /Image
24689152 bytes read in 4377 ms (5.4 MiB/s)
append: earlycon=pl011,mmio32,0xfff32000 console=ttyAMA6,115200 rw root=/dev/mmcblk0p2 rot
Retrieving file: /hi3660-hikey960.dtb
35047 bytes read in 14 ms (2.4 MiB/s)
## Flattened Device Tree blob at 10000000
Booting using the fdt blob at 0x10000000
Using Device Tree in place at 0000000010000000, end 000000001000b8e6
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 5.2.0-03138-gd75da80dce39 (mani@Mani-XPS-13-9360) (gcc versi9
[ 0.000000] Machine model: HiKey960
[ 0.000000] earlycon: pl11 at MMIO32 0x00000000fff32000 (options '')
[ 0.000000] printk: bootconsole [pl11] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:

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.. SPDX-License-Identifier: GPL-2.0-or-later
HiSilicon
=========
.. toctree::
:maxdepth: 2
hikey
hikey960
poplar

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.. SPDX-License-Identifier: GPL-2.0-or-later
Poplar board
############
Board Information
=================
Developed by HiSilicon, the board features the Hi3798C V200 with an
integrated quad-core 64-bit ARM Cortex A53 processor and high
performance Mali T720 GPU, making it capable of running any commercial
set-top solution based on Linux or Android. Its high performance
specification also supports a premium user experience with up to H.265
HEVC decoding of 4K video at 60 frames per second.
* SOC Hisilicon Hi3798CV200
* CPU Quad-core ARM Cortex-A53 64 bit
* DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
* USB Two USB 2.0 ports One USB 3.0 ports
* CONSOLE USB-micro port for console support
* ETHERNET 1 GBe Ethernet
* PCIE One PCIe 2.0 interfaces
* JTAG 8-Pin JTAG
* EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot
* DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
* WIFI 802.11AC 2*2 with Bluetooth
* CONNECTORS One connector for Smart Card One connector for TSI
Build instructions
==================
.. note::
U-Boot has a **strong** dependency with the l-loader and the ARM trusted
firmware repositories.
The boot sequence is::
l-loader --> arm_trusted_firmware --> U-Boot
U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
over it. Currently, BL31 is being placed below the kernel text offset (check
poplar.c) but this could change in the future.
The current version of U-Boot has been tested with
- https://github.com/Linaro/poplar-l-loader.git::
commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c
Author: Alex Elder <elder@linaro.org>
Date: Fri Jun 16 08:57:59 2017 -0500
l-loader: use external memory region definitions
The ARM Trusted Firmware code now has a header file that collects
all the definitions for the memory regions used for its boot stages.
Include that file where needed, and use the definitions found therein
Signed-off-by: Alex Elder <elder@linaro.org>
- https://github.com/Linaro/poplar-arm-trusted-firmware.git::
commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68
Author: Alex Elder <elder@linaro.org>
Date: Fri Jun 16 09:24:50 2017 -0500
poplar: define memory regions in a separate file
Separate the definitions for memory regions used for the BL stage
images and FIP into a new file. The "l-loader" image uses knowledge
of the sizes and locations of these memory regions, and it can now
include this (external) header to get these definitions, rather than
having to make coordinated changes to both code bases.
The new file has a complete set of definitions (more than may be
required by one or the other user). It also includes a summary of
how the boot process works, and how it uses these regions.
It should now be relatively easy to adjust the sizes and locations
of these memory regions, or to add to them (e.g. for TEE).
Signed-off-by: Alex Elder <elder@linaro.org>
Compile from source
-------------------
Get all the sources
.. code-block:: bash
mkdir -p ~/poplar/src ~/poplar/bin
cd ~/poplar/src
git clone https://github.com/Linaro/poplar-l-loader.git l-loader
git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf
git clone https://github.com/Linaro/poplar-U-Boot.git U-Boot
Make sure you are using the correct branch on each one of these repositories.
The definition of "correct" might change over time (at this moment in time this
would be the "latest" branch).
Compile U-Boot
~~~~~~~~~~~~~~
Prerequisite:
.. code-block:: bash
sudo apt-get install device-tree-compiler
.. code-block:: bash
cd ~/poplar/src/U-Boot
make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
cp U-Boot.bin ~/poplar/bin
Compile ARM Trusted Firmware (ATF)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. code-block:: bash
cd ~/poplar/src/atf
make CROSS_COMPILE=aarch64-linux-gnu- all fip \
SPD=none BL33=~/poplar/bin/U-Boot.bin DEBUG=1 PLAT=poplar
Copy resulting binaries
.. code-block:: bash
cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/
cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/
Compile l-loader
~~~~~~~~~~~~~~~~
.. code-block:: bash
cd ~/poplar/src/l-loader
make clean
make CROSS_COMPILE=arm-linux-gnueabi-
Due to BootROM requiremets, rename l-loader.bin to fastboot.bin:
.. code-block:: bash
cp l-loader.bin ~/poplar/bin/fastboot.bin
Flash instructions
==================
Two methods:
Using USB debrick support
Copy fastboot.bin to a FAT partition on the USB drive and reboot the
poplar board while pressing S3(usb_boot).
The system will execute the new U-Boot and boot into a shell which you
can then use to write to eMMC.
Using U-BOOT from shell
1) using AXIS usb ethernet dongle and tftp
2) using FAT formated USB drive
Flash using TFTP (USB ethernet dongle)
--------------------------------------
Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board.
Copy fastboot.bin to your tftp server.
In U-Boot make sure your network is properly setup.
Then::
=> tftp 0x30000000 fastboot.bin
starting USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
USB1: USB EHCI 1.00
scanning bus 1 for devices... 3 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
scanning usb for ethernet devices... 1 Ethernet Device(s) found
Waiting for Ethernet connection... done.
Using asx0 device
TFTP from server 192.168.1.4; our IP address is 192.168.1.10
Filename 'poplar/fastboot.bin'.
Load address: 0x30000000
Loading: #################################################################
#################################################################
###############################################################
2 MiB/s
done
Bytes transferred = 983040 (f0000 hex)
=> mmc write 0x30000000 0 0x780
MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
=> reset
Flash using USB FAT drive
-------------------------
Copy fastboot.bin to any partition on a FAT32 formated usb flash drive.
Enter the uboot prompt::
=> fatls usb 0:2
983040 fastboot.bin
1 file(s), 0 dir(s)
=> fatload usb 0:2 0x30000000 fastboot.bin
reading fastboot.bin
983040 bytes read in 44 ms (21.3 MiB/s)
=> mmc write 0x30000000 0 0x780
MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
Boot trace
==========
::
Bootrom start
Boot Media: eMMC
Decrypt auxiliary code ...OK
lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000
Entry boot auxiliary code
Auxiliary code - v1.00
DDR code - V1.1.2 20160205
Build: Mar 24 2016 - 17:09:44
Reg Version: v134
Reg Time: 2016/03/18 09:44:55
Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg
Boot auxiliary code success
Bootrom success
LOADER: Switched to aarch64 mode
LOADER: Entering ARM TRUSTED FIRMWARE
LOADER: CPU0 executes at 0x000ce000
INFO: BL1: 0xe1000 - 0xe7000 [size = 24576]
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60
NOTICE: BL1: Built : 17:51:33, Apr 30 2017
INFO: BL1: RAM 0xe1000 - 0xe7000
INFO: BL1: Loading BL2
INFO: Loading image id=1 at address 0xe9000
INFO: Image id=1 loaded at address 0xe9000, size = 0x5008
NOTICE: BL1: Booting BL2
INFO: Entry point address = 0xe9000
INFO: SPSR = 0x3c5
NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60
NOTICE: BL2: Built : 17:51:33, Apr 30 2017
INFO: BL2: Loading BL31
INFO: Loading image id=3 at address 0x129000
INFO: Image id=3 loaded at address 0x129000, size = 0x8038
INFO: BL2: Loading BL33
INFO: Loading image id=5 at address 0x37000000
INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17
NOTICE: BL1: Booting BL31
INFO: Entry point address = 0x129000
INFO: SPSR = 0x3cd
INFO: Boot bl33 from 0x37000000 for 364311 Bytes
NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60
NOTICE: BL31: Built : 17:51:33, Apr 30 2017
INFO: BL31: Initializing runtime services
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x37000000
INFO: SPSR = 0x3c9
U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar
Model: HiSilicon Poplar Development Board
BOARD: Hisilicon HI3798cv200 Poplar
DRAM: 1 GiB
MMC: Hisilicon DWMMC: 0
In: serial@f8b00000
Out: serial@f8b00000
Err: serial@f8b00000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
starting USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
USB1: USB EHCI 1.00
scanning bus 1 for devices... 4 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
scanning usb for ethernet devices... 1 Ethernet Device(s) found
USB device 0:
Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade
Type: Removable Hard Disk
Capacity: 7632.0 MB = 7.4 GB (15630336 x 512)
... is now current device
Scanning usb 0:1...
=>

1
doc/board/index.rst
View file

@ -27,6 +27,7 @@ Board-specific doc
gateworks/index
google/index
highbank/index
hisilicon/index
htc/index
intel/index
kontron/index

2
doc/develop/bootstd.rst
View file

@ -247,7 +247,7 @@ fdtfile
Name of the flattened device tree (FDT) file to load, e.g.
"rockchip/rk3399-rockpro64.dtb"
fdtaddr_addr_r
fdt_addr_r
Address at which to load the FDT, e.g. 0x01f00000
fdtoverlay_addr_r (needed if overlays are used)

6
doc/sphinx/load_config.py
View file

@ -3,7 +3,7 @@
import os
import sys
from sphinx.util.pycompat import execfile_
from sphinx.util.osutil import fs_encoding
# ------------------------------------------------------------------------------
def loadConfig(namespace):
@ -48,7 +48,9 @@ def loadConfig(namespace):
sys.stdout.write("load additional sphinx-config: %s\n" % config_file)
config = namespace.copy()
config['__file__'] = config_file
execfile_(config_file, config)
with open(config_file, 'rb') as f:
code = compile(f.read(), fs_encoding, 'exec')
exec(code, config)
del config['__file__']
namespace.update(config)
else:

2
drivers/i2c/i2c-uclass.c
View file

@ -427,7 +427,7 @@ int i2c_get_chip_by_phandle(const struct udevice *parent, const char *prop_name,
goto err_exit;
}
ret = dev_read_u32(parent, "i2cbcdev", &phandle);
ret = dev_read_u32(parent, prop_name, &phandle);
if (ret)
goto err_exit;

38
drivers/usb/gadget/ci_udc.c
View file

@ -13,6 +13,7 @@
#include <cpu_func.h>
#include <net.h>
#include <malloc.h>
#include <wait_bit.h>
#include <asm/byteorder.h>
#include <asm/cache.h>
#include <linux/delay.h>
@ -354,12 +355,49 @@ static int ci_ep_enable(struct usb_ep *ep,
return 0;
}
static int ep_disable(int num, int in)
{
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
unsigned int ep_bit, enable_bit;
int err;
if (in) {
ep_bit = EPT_TX(num);
enable_bit = CTRL_TXE;
} else {
ep_bit = EPT_RX(num);
enable_bit = CTRL_RXE;
}
/* clear primed buffers */
do {
writel(ep_bit, &udc->epflush);
err = wait_for_bit_le32(&udc->epflush, ep_bit, false, 1000, false);
if (err)
return err;
} while (readl(&udc->epstat) & ep_bit);
/* clear enable bit */
clrbits_le32(&udc->epctrl[num], enable_bit);
return 0;
}
static int ci_ep_disable(struct usb_ep *ep)
{
struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
int num, in, err;
num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
err = ep_disable(num, in);
if (err)
return err;
ci_ep->desc = NULL;
ep->desc = NULL;
ci_ep->req_primed = false;
return 0;
}

2
drivers/usb/gadget/f_fastboot.c
View file

@ -520,7 +520,7 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
cmdbuf[req->actual] = '\0';
cmd = fastboot_handle_command(cmdbuf, response);
} else {
pr_err("buffer overflow");
pr_err("buffer overflow\n");
fastboot_fail("buffer overflow", response);
}

14
lib/efi_loader/Kconfig
View file

@ -133,18 +133,20 @@ endif
config EFI_VAR_BUF_SIZE
int "Memory size of the UEFI variable store"
default 16384 if EFI_MM_COMM_TEE
default 65536
default 131072
range 4096 2147483647
help
This defines the size in bytes of the memory area reserved for keeping
UEFI variables.
When using StandAloneMM (CONFIG_EFI_MM_COMM_TEE=y) this value should
match the value of PcdFlashNvStorageVariableSize used to compile the
StandAloneMM module.
When using StandAloneMM (CONFIG_EFI_MM_COMM_TEE=y) is used the
available size for storing variables is defined in
PcdFlashNvStorageVariableSize.
That value is probed at runtime from U-Boot. In that case,
EFI_VAR_BUF_SIZE represents the memory U-Boot reserves to present
runtime variables to the OS.
Minimum 4096, default 65536, or 16384 when using StandAloneMM.
Minimum 4096, default 131072
config EFI_GET_TIME
bool "GetTime() runtime service"

5
lib/efi_loader/efi_tcg2.c
View file

@ -944,8 +944,11 @@ static efi_status_t efi_init_event_log(void)
* Add SCRTM version to the log if previous firmmware
* doesn't pass an eventlog.
*/
if (!elog.found)
if (!elog.found) {
ret = efi_append_scrtm_version(dev);
if (ret != EFI_SUCCESS)
goto free_pool;
}
ret = create_final_event();
if (ret != EFI_SUCCESS)

7
lib/efi_loader/efi_var_file.c
View file

@ -204,8 +204,11 @@ efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe)
* File ubootefi.var is read from the EFI system partitions and the variables
* stored in the file are created.
*
* In case the file does not exist yet or a variable cannot be set EFI_SUCCESS
* is returned.
* On first boot the file ubootefi.var does not exist yet. This is why we must
* return EFI_SUCCESS in this case.
*
* If the variable file is corrupted, e.g. incorrect CRC32, we do not want to
* stop the boot process. We deliberately return EFI_SUCCESS in this case, too.
*
* Return: status code
*/

3
tools/renesas_spkgimage.c
View file

@ -147,7 +147,8 @@ static int spkgimage_verify_header(unsigned char *ptr, int size,
/* Check the marker bytes */
if (memcmp(header->marker, marker, 4)) {
fprintf(stderr, "Error: invalid marker bytes\n");
if (param->type == IH_TYPE_RENESAS_SPKG)
fprintf(stderr, "Error: invalid marker bytes\n");
return -EINVAL;
}