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https://github.com/AsahiLinux/u-boot
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arm: dts: imx8mn: Sync with linux-next 20231019
Sync imx8mn.dtsi with linux-next 20231019. Signed-off-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Fabio Estevam
Fabio Estevam
parent
5037bd532d
commit
05dffb9fb1
1 changed files with 154 additions and 13 deletions
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@ -139,6 +139,7 @@
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A53_L2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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@ -295,6 +296,7 @@
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sai2: sai@30020000 {
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compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
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reg = <0x30020000 0x10000>;
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#sound-dai-cells = <0>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
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<&clk IMX8MN_CLK_DUMMY>,
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@ -309,6 +311,7 @@
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sai3: sai@30030000 {
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compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
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reg = <0x30030000 0x10000>;
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#sound-dai-cells = <0>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
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<&clk IMX8MN_CLK_DUMMY>,
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@ -323,6 +326,7 @@
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sai5: sai@30050000 {
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compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
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reg = <0x30050000 0x10000>;
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#sound-dai-cells = <0>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
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<&clk IMX8MN_CLK_DUMMY>,
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@ -339,6 +343,7 @@
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sai6: sai@30060000 {
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compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
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reg = <0x30060000 0x10000>;
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#sound-dai-cells = <0>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
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<&clk IMX8MN_CLK_DUMMY>,
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@ -366,6 +371,7 @@
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"pll8k", "pll11k", "clkext3";
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dmas = <&sdma2 24 25 0x80000000>;
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dma-names = "rx";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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@ -396,6 +402,7 @@
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sai7: sai@300b0000 {
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compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
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reg = <0x300b0000 0x10000>;
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#sound-dai-cells = <0>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
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<&clk IMX8MN_CLK_DUMMY>,
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@ -497,6 +504,8 @@
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compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
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reg = <0x30260000 0x10000>;
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clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
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nvmem-cells = <&tmu_calib>;
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nvmem-cell-names = "calib";
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#thermal-sensor-cells = <0>;
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};
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@ -551,7 +560,7 @@
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reg = <0x30330000 0x10000>;
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};
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gpr: iomuxc-gpr@30340000 {
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gpr: syscon@30340000 {
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compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
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reg = <0x30340000 0x10000>;
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};
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@ -563,23 +572,40 @@
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#address-cells = <1>;
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#size-cells = <1>;
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imx8mn_uid: unique-id@410 {
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/*
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* The register address below maps to the MX8M
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* Fusemap Description Table entries this way.
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* Assuming
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* reg = <ADDR SIZE>;
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* then
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* Fuse Address = (ADDR * 4) + 0x400
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* Note that if SIZE is greater than 4, then
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* each subsequent fuse is located at offset
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* +0x10 in Fusemap Description Table (e.g.
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* reg = <0x4 0x8> describes fuses 0x410 and
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* 0x420).
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*/
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imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
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reg = <0x4 0x8>;
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};
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cpu_speed_grade: speed-grade@10 {
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cpu_speed_grade: speed-grade@10 { /* 0x440 */
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reg = <0x10 4>;
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};
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fec_mac_address: mac-address@90 {
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tmu_calib: calib@3c { /* 0x4f0 */
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reg = <0x3c 4>;
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};
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fec_mac_address: mac-address@90 { /* 0x640 */
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reg = <0x90 6>;
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};
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};
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anatop: anatop@30360000 {
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compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
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"syscon";
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anatop: clock-controller@30360000 {
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compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
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reg = <0x30360000 0x10000>;
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#clock-cells = <1>;
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};
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snvs: snvs@30370000 {
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@ -662,7 +688,6 @@
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pgc_otg1: power-domain@1 {
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#power-domain-cells = <0>;
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reg = <IMX8MN_POWER_DOMAIN_OTG1>;
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power-domains = <&pgc_hsiomix>;
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};
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pgc_gpumix: power-domain@2 {
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@ -1038,6 +1063,72 @@
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#size-cells = <1>;
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ranges;
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lcdif: lcdif@32e00000 {
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compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
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reg = <0x32e00000 0x10000>;
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clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
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<&clk IMX8MN_CLK_DISP_APB_ROOT>,
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<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
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clock-names = "pix", "axi", "disp_axi";
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
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status = "disabled";
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port {
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lcdif_to_dsim: endpoint {
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remote-endpoint = <&dsim_from_lcdif>;
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};
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};
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};
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mipi_dsi: dsi@32e10000 {
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compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
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reg = <0x32e10000 0x400>;
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clocks = <&clk IMX8MN_CLK_DSI_CORE>,
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<&clk IMX8MN_CLK_DSI_PHY_REF>;
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clock-names = "bus_clk", "sclk_mipi";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsim_from_lcdif: endpoint {
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remote-endpoint = <&lcdif_to_dsim>;
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};
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};
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};
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};
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isi: isi@32e20000 {
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compatible = "fsl,imx8mn-isi";
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reg = <0x32e20000 0x8000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
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<&clk IMX8MN_CLK_DISP_APB_ROOT>;
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clock-names = "axi", "apb";
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fsl,blk-ctrl = <&disp_blk_ctrl>;
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power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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isi_in: endpoint {
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remote-endpoint = <&mipi_csi_out>;
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};
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};
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};
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};
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disp_blk_ctrl: blk-ctrl@32e28000 {
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compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
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reg = <0x32e28000 0x100>;
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@ -1063,11 +1154,60 @@
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"lcdif-axi", "lcdif-apb", "lcdif-pix",
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"dsi-pclk", "dsi-ref",
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"csi-aclk", "csi-pclk";
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assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
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<&clk IMX8MN_CLK_DSI_PHY_REF>,
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<&clk IMX8MN_CLK_DISP_PIXEL>,
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<&clk IMX8MN_CLK_DISP_AXI>,
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<&clk IMX8MN_CLK_DISP_APB>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
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<&clk IMX8MN_CLK_24M>,
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<&clk IMX8MN_VIDEO_PLL1_OUT>,
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<&clk IMX8MN_SYS_PLL2_1000M>,
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<&clk IMX8MN_SYS_PLL1_800M>;
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assigned-clock-rates = <266000000>,
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<24000000>,
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<594000000>,
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<500000000>,
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<200000000>;
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#power-domain-cells = <1>;
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};
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mipi_csi: mipi-csi@32e30000 {
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compatible = "fsl,imx8mm-mipi-csi2";
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reg = <0x32e30000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
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assigned-clock-rates = <333000000>;
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clock-frequency = <333000000>;
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clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
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<&clk IMX8MN_CLK_CAMERA_PIXEL>,
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<&clk IMX8MN_CLK_CSI1_PHY_REF>,
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<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
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clock-names = "pclk", "wrap", "phy", "axi";
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power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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mipi_csi_out: endpoint {
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remote-endpoint = <&isi_in>;
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};
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};
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};
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};
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usbotg1: usb@32e40000 {
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compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
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compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
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reg = <0x32e40000 0x200>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
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@ -1076,12 +1216,13 @@
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
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phys = <&usbphynop1>;
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fsl,usbmisc = <&usbmisc1 0>;
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power-domains = <&pgc_otg1>;
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power-domains = <&pgc_hsiomix>;
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status = "disabled";
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};
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usbmisc1: usbmisc@32e40200 {
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compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
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compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc",
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"fsl,imx6q-usbmisc";
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#index-cells = <1>;
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reg = <0x32e40200 0x200>;
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};
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@ -1094,7 +1235,6 @@
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
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#dma-cells = <1>;
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dma-channels = <4>;
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clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
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@ -1103,7 +1243,7 @@
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gpmi: nand-controller@33002000 {
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compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <0>;
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reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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@ -1175,5 +1315,6 @@
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assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
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clock-names = "main_clk";
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power-domains = <&pgc_otg1>;
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};
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};
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