Commit graph

20714 commits

Author SHA1 Message Date
Stefan Mätje
a6e562fe36 Fix wrong QSPI clock calculation for AM4372
On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.

The QSPI_FCLK therefore needs to take this factor into account and
becomes (192000000 / 4).

Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
2022-01-16 08:31:03 -05:00
Christian Gmeiner
e660cfad53 omap: timer: implement timer_get_boot_us
To make the OMAP DM timer driver useful for the timing of
bootstages, we need to implement timer_get_boot_us(..).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-01-16 08:31:03 -05:00
chao zeng
b6e59617c8 gpio: da8xx_gpio: Fix gpio name with address
The GPIO bank numbers do not appear in the device tree,
so make the gpio name based on the address
(ie gpio@42110000_25 vs 25)

Signed-off-by: chao zeng <chao.zeng@siemens.com>
2022-01-16 08:31:03 -05:00
Christian Gmeiner
046bf8d4c5 net: fastboot: make UDP port net: configurable
The fastboot protocol uses per default the UDP port 5554. In some cases
it might be needed to change the used port. The fastboot utility provides
a way to specifiy an other port number to use already.

  fastboot -s udp:192.168.1.76:1234 boot fastboot.img

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-15 18:54:21 +02:00
Markus Koch
eab18b3b06 net: fsl: Fix busy flag polling register
NXP's mEMAC reference manual, Chapter 6.5.5 "MDIO Ethernet Management
Interface usage", specifies to poll the BSY (0) bit in the CFG/STAT
register to wait until a transaction has finished, not bit 31 in the
data register.

In the Linux kernel, this has already been fixed in commit 26eee0210ad7
("net/fsl: fix a bug in xgmac_mdio").

This patch changes the register in the fman_mdio and fsl_ls_mdio
drivers.

As the MDIO_DATA_BSY define is no longer in use, this patch also removes
its definition from the fsl_memac header.

Signed-off-by: Markus Koch <markus@notsyncing.net>
Reviewed-by: Camelia Groza <camelia.groza@nxp.com>
2022-01-15 18:53:16 +02:00
Marek Vasut
766ba78375 net: eth-phy: Demote missing phy-handle log message to debug
Reduce the missing phy-handle log message to debug message. It is
possible for ethernet DT node to have no phy-handle e.g. in case
of a fixed-link connection. Furthermore, drop the FEC: prefix,
which is a copy-paste error and rather print the ethernet device
name.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-15 18:51:49 +02:00
Dominic Rath
f3e22eea81 net: phy: add TI DP83869HM ethernet driver
This driver is based on an older downstream TI kernel, with
changes and cleanups to work with mainline device-tree bindings.

Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-15 18:50:16 +02:00
Vladimir Oltean
6372ece6e8 net: dsa: sja1105: fix device id detection
The sja1105_check_device_id() function contains logic to work without
changing the device tree on reworked boards, one of which I have (the
NXP LS1021A-TSN normally has a SJA1105T, but I have a version with a
resoldered SJA1105Q which is pin compatible). This logic is taken from
the Linux driver.

However this logic gets shortcircuited in U-Boot by an earlier check for
the exact device ID specified in the device tree. So the reworked board
does not probe the SJA1105Q switch. Remove this duplicated logic and let
the automatic device ID detection do its job.

Fixes: f24b666b22 ("net: dsa: add driver for NXP SJA1105 L2 switch")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-15 18:49:13 +02:00
Vignesh Raghavendra
38922b1f4a net: ti: am65-cpsw: Add support for multi port independent MAC mode
On certain TI SoC, like AM64x there is a CPSW3G which supports 2
external independent MAC ports for single CPSW instance.
It is not possible for Ethernet driver to register more than one port
for given instance.

This patch modifies top level CPSW NUSS as UCLASS_MISC and binds
UCLASS_ETH to individual ports so as to support bring up more than one
Ethernet interface in U-Boot.

Note that there is no isolation in the since, CPSW NUSS is in promisc
mode and forwards all packets to host.

Since top level driver is now UCLASS_MISC, board files would need to
instantiate this driver explicitly.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
4af5e5f6fd dma: ti: k3-udma: Fix rflow reservation for PKTDMA
Driver has a bug in that it uses rflow_in_use bitmap when setting up free rflow range
from TISCI but use rflow_map for reservation in __udma_reserve_rflow()

Fix this by dropping rflow_in_use bitmap array and use rflow_map for
PKTDMA. BCDMA does not need rflow_in_use either.

This fixes CPSW3g not able to get DMA channels at R5 SPL on AM64x

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Alper Nebi Yasak
226fce6108 phy: Track power-on and init counts in uclass
On boards using the RK3399 SoC, the USB OHCI and EHCI controllers share
the same PHY device instance. While these controllers are being stopped
they both attempt to power-off and deinitialize it, but trying to
power-off the deinitialized PHY device results in a hang. This usually
happens just before booting an OS, and can be explicitly triggered by
running "usb start; usb stop" in the U-Boot shell.

Implement a uclass-wide counting mechanism for PHY initialization and
power state change requests, so that we don't power-off/deinitialize a
PHY instance until all of its users want it done. The Allwinner A10 USB
PHY driver does this counting in-driver, remove those parts in favour of
this in-uclass implementation.

The sandbox PHY operations test needs some changes since the uclass will
no longer call into the drivers for actions matching its tracked state
(e.g. powering-off a powered-off PHY). Update that test, and add a new
one which simulates multiple users of a single PHY.

The major complication here is that PHY handles aren't deduplicated per
instance, so the obvious idea of putting the counts in the PHY handles
don't immediately work. It seems possible to bind a child udevice per
PHY instance to the PHY provider and deduplicate the handles in each
child's uclass-private areas, like in the CLK framework. An alternative
approach could be to use those bound child udevices themselves as the
PHY handles. Instead, to avoid the architectural changes those would
require, this patch solves things by dynamically allocating a list of
structs (one per instance) in the provider's uclass-private area.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com> - Rock960
2022-01-14 14:36:57 -05:00
Joel Peshkin
36a3b4ed56 BRCMNAND: Fix reporting of uncorrectable errors on subpages during page read
Previously, a subpage with an uncorrectable error followed by a subpage
with a correctable error would return an erroneous correctable status.

Signed-off-by: Joel Peshkin <joel.peshkin@broadcom.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-14 13:16:11 -05:00
Pali Rohár
d17ab6e128 nvme: Do not allocate 8kB buffer on stack
Calling 'nvme scan' followed by 'nvme detail' crashes U-Boot on Turris
Omnia with the following error:

  undefined instruction
  pc : [<0a000000>]          lr : [<7ff80bfc>]
  reloc pc : [<8a8c0000>]    lr : [<00840bfc>]
  sp : 7fb2b908  ip : 0000002a     fp : 02000000
  r10: 04000000  r9 : 7fb2fed0     r8 : e1000000
  r7 : 0c000000  r6 : 03000000     r5 : 06000000  r4 : 01000000
  r3 : 7fb30928  r2 : 7fb30928     r1 : 00000000  r0 : 00000000
  Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
  Code: 0f0fb4f0 0f0fb4f0 0f0fb4f0 0f0fb4f0 (f0f04b0f)
  Resetting CPU ...

This happens when nvme_print_info() tries to return to the caller. It
looks like this error is caused by trying to allocate 8 KiB of memory
on the stack by the two uses of ALLOC_CACHE_ALIGN_BUFFER().

Use malloc_cache_aligned() to allocate this memory dynamically instead.

This fixes 'nvme detail' on Turris Omnia.

Note that similar change was applied to file drivers/nvme/nvme.c in past by
commit 2f83481dff ("nvme: use page-aligned buffer for identify command").

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
2022-01-14 13:16:10 -05:00
Maciej W. Rozycki
a398a51ccc pci: Work around PCIe link training failures
Attempt to handle cases with a downstream port of a PCIe switch where
link training never completes and the link continues switching between
speeds indefinitely with the data link layer never reaching the active
state.

It has been observed with a downstream port of the ASMedia ASM2824 Gen 3
switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2
switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device,
P/N 41433, wired to a SiFive HiFive Unmatched board.  In this setup the
switches are supposed to negotiate the link speed of preferably 5.0GT/s,
falling back to 2.5GT/s.

However the link continues oscillating between the two speeds, at the
rate of 34-35 times per second, with link training reported repeatedly
active ~84% of the time, e.g.:

02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode])
[...]
	Bus: primary=02, secondary=05, subordinate=05, sec-latency=0
[...]
	Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00
[...]
		LnkSta:	Speed 5GT/s (downgraded), Width x1 (ok)
			TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt-
[...]
		LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
[...]

Forcibly limiting the target link speed to 2.5GT/s with the upstream
ASM2824 device makes the two switches communicate correctly however:

02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode])
[...]
	Bus: primary=02, secondary=05, subordinate=09, sec-latency=0
[...]
	Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00
[...]
		LnkSta:	Speed 2.5GT/s (downgraded), Width x1 (ok)
			TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
[...]
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
[...]

and then:

05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode])
[...]
	Bus: primary=05, secondary=06, subordinate=09, sec-latency=0
[...]
	Capabilities: [c0] Express (v2) Upstream Port, MSI 00
[...]
		LnkSta:	Speed 2.5GT/s (downgraded), Width x1 (downgraded)
			TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
[...]
		LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
[...]

Make use of this observation then and attempt to detect the inability to
negotiate the link speed automatically, and then handle it by hand.  Use
the Data Link Layer Link Active status flag as the primary indicator of
successful link speed negotiation, but given that the flag is optional
by hardware to implement (the ASM2824 does have it though), resort to
checking for the mandatory Link Bandwidth Management Status flag showing
that the link speed or width has been changed in an attempt to correct
unreliable link operation (the ASM2824 does set it too).

If these checks indicate that link may not operate correctly, then poll
the Data Link Layer Link Active status flag along with the Link Training
flag for the duration of 200ms to see if the link has stabilised, that
is either that the Data Link Layer Link Active status flag has been set
or that Link Training has been inactive during at least the second half
of the interval.

If that has indicated failure, restrict the target speed to 2.5GT/s,
request a link retrain and check again if the link has stabilised.  If
that does not work either, then restore the original speed setting and
claim defeat, otherwise we are done.

NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration
referred above asking the ASM2824 to retrain with a higher target link
speed once the 2.5GT/s speed has been negotiated makes the two devices
successfully negotiate 5.0GT/s.  Lifting the 2.5GT/s speed restriction
would however prevent our workaround from working with an OS that issues
a reset and that is unaware of the problem.  This is because the devices
would then try to negotiate a higher link speed from scratch and fail,
while the sticky property of the Target Link Speed setting will keep the
2.5GT/s speed restriction across a reset.

Keep the 2.5GT/s speed restriction then, conservatively, if functional
once applied.

Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 12:26:42 -05:00
Marek Behún
3fc92a215b ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision
This is a cleaned up and fixed version of a patch
  mv_ddr: a380: fix SPLIT_OUT_MIX state decision

  in each pattern cycle the bus state can be changed
  in order to avoide it, need to back to the same bus state on each
  pattern cycle
by
  Moti Boskula <motib@marvell.com>

The original patch is not in Marvell's mv-ddr-marvell repository. It was
gives to us by Marvell to fix an issues with DDR training on some
boards, but it cannot be applied as is to mv-ddr-marvell, because it is
a very dirty draft patch that would certainly break other things, mainly
DDR4 training code in mv-ddr-marvell, since it changes common functions.

I have cleaned up the patch and removed stuff that seemed unnecessary
(when removed, it still fixed things). Note that I don't understand
completely what the code does exactly, since I haven't studied the DDR
training code extensively (and I suspect that no one besides some few
people in Marvell understand the code completely).

Anyway after the cleanup the patch still fixes isssues with DDR training
on the failing boards.

There was also a problem with the original patch on some of the Allied
Telesis' x530 boards, reported by Chris Packham. I have asked Chris to
send me some logs, and managed to fix it:
- if you look at the change, you'll notice that it introduces
  subtraction of cur_start_win[] and cur_end_win[] members, depending on
  a bit set in the current_byte_status variable
- the original patch subtracted cur_start_win[] if either
  BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but
  subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX)
  was set
- from Chris Packham logs I discovered that the x530 board where the
  original patch introduced DDR training failure, only the
  BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the
  patch is needed only the BYTE_SPLIT_OUT_MIX is set in the
  current_byte_status variable
- this led me to the hypothesis that both cur_start_win[] and
  cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is
  set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all
- this hypothesis also gains credibility when considering the commit
  title ("fix SPLIT_OUT_MIX state decision")

Hopefully this will fix things without breaking anything else.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Chris Packham <judge.packham@gmail.com>
2022-01-14 11:39:15 +01:00
Marek Behún
eadc4f512f ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination
Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
mode"), Asynchornous Mode was only used when the CPU Subsystem Clock
Options[4:0] field in the SAR1 register was set to value 0x13: CPU at
2 GHz and DDR at 933 MHz.

Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
mode") added support for Asynchornous Modes with frequencies other than
933 MHz (but at least 467 MHz), but the code it added to check for
whether Asynchornous Mode should be used is wrong: it checks whether the
frequency setting in board DDR topology map is set to value other than
MV_DDR_FREQ_SAR.

Thus boards which define a specific value, greater than 400 MHz, for DDR
frequency in their board topology (e.g. Turris Omnia defines
MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that
commit.

The A38x Functional Specification, section 10.12 DRAM Clocking, says:
  In Synchornous mode, the DRAM and CPU clocks are edge aligned and run
  in 1:2 or 1:3 CPU to DRAM frequency ratios.

Change the check for whether Asynchornous Mode should be used according
to this explanation in Functional Specification.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 07:47:57 +01:00
Pierre Bourdon
c03f4da187 mtd: nand: pxa3xx: use marvell, prefix for custom DT properties
The DT properties for the "enable-arbiter" and "keep-config" config
knobs were previously named inconsistently:

- The u-boot driver used "nand-enable-arbiter" and "nand-keep-config"
  names, without Marvell prefixes.

- The Linux driver uses "marvell,nand-keep-config" ("enable-arbiter"
  does not exist anymore in recent kernels, but it also used to be
  "marvell,nand-enable-arbiter").

- The device trees almost all use "marvell," prefixed names, except for
  one single instance of "nand-enable-arbiter" without vendor prefix.

This commit standardizes on the vendor prefixed version, making the
u-boot driver read from DT props "marvell,nand-enable-arbiter" and
"marvell,nand-keep-config". The one device tree using the unprefixed
version is also changed to use the new naming.

This has the side effect of making the previously no-op "marvell,"
config knobs already present in some DTs actually do something. This was
likely the original intention of the DT authors, but note that this
commit was not tested on every single impacted board.

Signed-off-by: Pierre Bourdon <delroth@gmail.com>
2022-01-14 07:47:57 +01:00
Pali Rohár
94c30f9c8f arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c
As explained in commit 3bedbcc3aa ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.

Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.

Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.

Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.

This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
e7ff4271ab pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe()
After function mvebu_pcie_probe() returns U-Boot DM expects that PCIe link
is already up. In followup patches link initialization will be moved from
SPL to proper and therefore explicitly link up delay is required.

Delay mvebu_pcie_probe() for 100ms to ensure that PCIe link is up after
function finish. In the case when no card is connected to the PCIe slot,
this will delay probe time by 100ms, which should not be problematic.

This change fixes detection and initialization of some QCA98xx cards on
the first serdes when configured in x1 mode. Default configuration of
the first serdes on A385 is x4 mode, so it looks as if some delay is
required when x4 is changed to x1 and card correctly links with A385.
Other PCIe serdes ports on A385 are x1-only, and so they don't have this
problem.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
afef9f4215 pci: pci_mvebu: Split initialization of PCIe ports into 3 phases
In first phase just parse DT properties and fill struct mvebu_pcie. In
second phase setup all PCIe links (without enabling them). And in the last
third phase enable all PCIe links and create UCLASS_PCI device for each
one.

Because parsing of DT is done before UCLASS_PCI is created, we cannot use
DM for this action anymore. So remove .of_to_plat callback and replace it
by ad-hoc function for parsing DT properties and filling struct mvebu_pcie.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
137db2af14 pci: pci_mvebu: Remove dependency on SOC_REGS_PHY_BASE macro
SoC specific macro SOC_REGS_PHY_BASE is used for two things:

* calculation of base PCIe port address
* filling PCIe register with address of internal registers

For calculating base PCIe port address use function
ofnode_translate_address() which translates DT "assigned-addresses" to
final PCIe port address.

And for calculating address of internal registers use untranslated and
translated DT "assigned-addresses".

Basically this change reads SOC_REGS_PHY_BASE address indirectly from DT.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
6f4988f90c pci: pci_mvebu: Inline mvebu_pcie_port_parse_dt() function
Function mvebu_pcie_port_parse_dt() is called only from
mvebu_pcie_of_to_plat() function. Both these function parse DT properties
required to setup mvebu pcie. So inline mvebu_pcie_port_parse_dt() function
into mvebu_pcie_of_to_plat() to have all code related to parsing DT
properties at one place.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
537b0142b0 pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping
Do not call pci_set_region() for resources which were not properly mapped.
This prevents U-Boot to access unmapped memory space.

Update MBUS_PCI_MEM_SIZE and MBUS_PCI_IO_SIZE macros to cover all PCIe MEM
and IO ranges. Previously these macros covered only address ranges for the
first PCIe port. Between MBUS_PCI_IO_BASE and MBUS_PCI_MEM_BASE there is
space for six 128 MB long address ranges. So set MBUS_PCI_MEM_SIZE to value
of 6*128 MB. Similarly set MBUS_PCI_IO_SIZE to 6*64 KB.

Function resource_size() returns zero when start address is 0 and end
address is -1. So set invalid resources to these values to indicate that
resource has no mapping.

Split global PCIe MEM and IO resources (defined by MBUS_PCI_*_* macros)
into PCIe ports in mvebu_pcie_bind() function which allocates per-port
based struct mvebu_pcie, instead of using global state variables
mvebu_pcie_membase and mvebu_pcie_iobase. This makes pci_mvebu.c driver
independent of global static variables (which store the state of
allocation) and allows to bind and unbind the driver more times.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
2022-01-14 07:47:57 +01:00
Simon Glass
f350f67764 fdt: Drop SPL_BUILD macro
This old macro is not needed anymore since we can use IS_ENABLED() now.
Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Michal Simek
d8ef446fec dm: core: Switch order of pinctrl and power domain calls
The commit 3ad3077848 ("dm: core: device: enable power domain in probe")
introduced enabling power domain when device is probed.
By checking this sequence in Linux kernel was found that power domain is
handled first followed by pinctrl setting.

This patch is switching this order to follow Linux kernel that power
domains are handled first follow by pinctrl setting.

The issue was found on Xilinx Kria SOM where firmware is blocking setting
up pin configuration/muxes without enabling power domain for the specific
IP first.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Tom Rini
743c562d0c Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Add Apple M1 watchdog timer (Mark)
2022-01-13 08:00:02 -05:00
Vagrant Cascadian
5e7658925b drivers/usb/gadget/dwc2_udc_otg.c: Fix spelling of "resetting". 2022-01-13 07:57:50 -05:00
Vagrant Cascadian
0776c5fbb7 drivers/ddr/altera/sequencer.c: Fix spelling of "resetting". 2022-01-13 07:57:50 -05:00
Vagrant Cascadian
0580cd1636 drivers/core/of_addr.c: Fix spelling of "shouldn't". 2022-01-13 07:57:50 -05:00
Vagrant Cascadian
f697addf8a drivers/net/fec_mxc.c: Fix spelling of "resetting". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
a5c20f6b91 drivers/usb/musb/musb_udc.c: Fix spelling of "mismatch". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
70463798b2 drivers/mtd/ubispl/ubispl.c: Fix spelling of "mismatched". 2022-01-13 07:57:49 -05:00
Sean Anderson
46ad7cef64 treewide: invaild -> invalid
Somewhere along the way, someone misspelt "invalid" and it got copied
everywhere. Fix it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-13 07:57:49 -05:00
Eugen Hristev
009b108d80 i2c: at91: add compatible with microchip,sam9x60-i2c
Add compatible and data platform struct for sam9x60 SoC.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-01-13 11:44:07 +02:00
Mark Kettenis
ee327d1d93 watchdog: Add a driver for the Apple watchdog
This driver supports the watchdog timer found on Apple's M1 SoC.
On systems that use these SoC, the watchdog timer is the primary
way to reboot the system.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-on: Apple M1 Macbook
Tested-by: Simon Glass <sjg@chromium.org>
2022-01-13 06:55:46 +01:00
Pali Rohár
2a67bf65dd pci: sh7751: Fix access to config space via PCI_CONF1_ADDRESS() macro
sh7751 platform uses standard format of Config Address for PCI
Configuration Mechanism #1.

Commit 72c2f4acd7 ("pci: sh7751: Convert to DM and DT probing") which did
conversion of PCI sh7751 driver to DM, broke access to config space as that
commit somehow swapped device and function bits in config address.

Fix all these issues by using new U-Boot macro PCI_CONF1_ADDRESS() which
calculates Config Address correctly.

Also remove nonsense function sh7751_pci_addr_valid() which was introduced
in commit 72c2f4acd7 ("pci: sh7751: Convert to DM and DT probing")
probably due to workarounded issues with mixing/swapping device and
function bits of config address which probably resulted in non-working
access to some devices. With correct composing of config address there
should not be such issue anymore.

Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 72c2f4acd7 ("pci: sh7751: Convert to DM and DT probing")
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
7fabaa5313 pci: sh7780: Use PCI_CONF1_ADDRESS() macro
PCI sh7780 driver uses standard format of Config Address for PCI
Configuration Mechanism #1.

So use new U-Boot macro PCI_CONF1_ADDRESS().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
022d43bdfb pci: mediatek: Use PCI_CONF1_EXT_ADDRESS() macro
PCI mediatek driver uses extended format of Config Address for PCI
Configuration Mechanism #1 but with cleared Enable bit.

So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() with clearing
PCI_CONF1_ENABLE bit and remove old custom driver address macros.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
f031f07f3a pci: fsl: Use PCI_CONF1_EXT_ADDRESS() macro
PCI fsl driver uses extended format of Config Address for PCI
Configuration Mechanism #1.

So use new U-Boot macro PCI_CONF1_EXT_ADDRESS().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
86be29e9d9 pci: tegra: Use PCI_CONF1_EXT_ADDRESS() macro
PCI tegra driver uses extended format of Config Address for PCI
Configuration Mechanism #1 but with cleared Enable bit.

So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() with clearing
PCI_CONF1_ENABLE bit and remove old custom driver address function.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
d0dd49f929 pci: mvebu: Use PCI_CONF1_EXT_ADDRESS() macro
PCI mvebu driver uses extended format of Config Address for PCI
Configuration Mechanism #1.

So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() and remove old custom
driver address macros.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
f146bd96e4 pci: msc01: Use PCI_CONF1_ADDRESS() macro
PCI msc01 driver uses standard format of Config Address for PCI
Configuration Mechanism #1 but with cleared Enable bit.

So use new U-Boot macro PCI_CONF1_ADDRESS() with clearing PCI_CONF1_ENABLE
bit and remove old custom driver address macros.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
247ffc6b36 pci: mpc85xx: Use PCI_CONF1_EXT_ADDRESS() macro
PCI mpc85xx driver uses extended format of Config Address for PCI
Configuration Mechanism #1.

So use new U-Boot macro PCI_CONF1_EXT_ADDRESS().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
2b29d79be8 pci: gt64120: Use PCI_CONF1_ADDRESS() macro
PCI gt64120 driver uses standard format of Config Address for PCI
Configuration Mechanism #1.

So use new U-Boot macro PCI_CONF1_ADDRESS() and remove old custom driver
address macros.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
95ab5784bf pci: When disabling pref MEM set all base bits
It is common to set all base address bits to one and all limit address bits
to zero for disabling address forwarding. Forwarding is disabled when base
address is higher than limit address, so this change should not have any
effect.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-12 14:21:24 -05:00
Pali Rohár
06f25bd2a9 pci: Disable I/O forwarding during autoconfiguration if unsupported
If U-Boot does not have any I/O resource for assignment then disable I/O
forwarding in PCI bridge autoconfiguration code. Default initial state of
PCI bridge IO registers is unspecified, therefore they can be in enabled if
U-Boot does not touch them.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-12 14:21:24 -05:00
Pali Rohár
f2094143c5 pci: Fix register for determining type of IO base address
Function dm_pciauto_prescan_setup_bridge() configures base address
registers, therefore it should read type of IO from base address registers
(and not from limit address registers).

Note that base and limit address registers should have same type, so this
change is just usage correction and has no functional change on correctly
working hardware.

Fixes: 8e85f36a8f ("pci: Fix configuring io/memory base and limit registers of PCI bridges")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-12 14:21:24 -05:00
Pali Rohár
bf667d5f15 pci: pci_octeontx: Use PCIE_ECAM_OFFSET() macro
Replace custom driver macros by PCIE_ECAM_OFFSET() macro from pci.h

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-12 14:21:24 -05:00
Pali Rohár
3264b6177f pci: pcie_iproc: Use PCIE_ECAM_OFFSET() macro
Replace custom driver macros by PCIE_ECAM_OFFSET() macro from pci.h

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
fbfa15c0b8 pci: pcie-brcmstb: Use PCIE_ECAM_OFFSET() macro
Replace custom driver macros by PCIE_ECAM_OFFSET() macro from pci.h

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
2022-01-12 14:21:24 -05:00
Michal Simek
1d78d68349 phy: zynqmp: Add serdes/psgtr driver
Add PSGTR driver for Xilinx ZynqMP.
The most of configurations are taken from Linux kernel psgtr driver.

USB3.0 and SGMII configurations are tested on SOM. In SGMII case also
IOU_SLCR reg is updated to get proper clock setup and signal detection
configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com
2022-01-12 10:41:46 +01:00
Michal Simek
28880b68d4 serial: zynq: Add missing xlnx,zynqmp-uart compatible
Based on Linux kernel DT binding xlnx,zynqmp-uart is another compatible
string which can be used for this driver. That's why also list it here.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/959a4cbbdd06a7fca2d9251ff0f535863a562b96.1641905717.git.michal.simek@xilinx.com
2022-01-12 10:40:32 +01:00
John Keeping
66d0b7e1f2 mmc: dwmmc: return a proper error code when busy
When failing to send a command because the hardware is busy, return
EBUSY to indicate the cause instead of just -1.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12 09:56:40 +09:00
Sean Anderson
b2acee4bb0 mmc: fsl_esdhc_imx: set sysctl register for clock initialization
[ fsl_esdhc commit 263ddfc345 ]

The initial clock setting should be through sysctl register only,
while the mmc_set_clock() will call mmc_set_ios() introduce other
configurations like bus width, mode, and so on.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-01-12 09:56:40 +09:00
Sean Anderson
00e0cd7fda mmc: fsl_esdhc_imx: Replace more #ifdefs by if
This builds on the previous patch by converting yet more preprocessor
macros to C ifs. This is split off so that the changes adapted from
Micheal's patch may be clearly distinguished from the ones I have
authored myself.

MMC_SUPPORTS_TUNING should really get a Kconfig conversion. And DM_GPIO
needs some -ENOSYS stubs when it isn't defined.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-01-12 09:56:40 +09:00
Sean Anderson
4f01db814a mmc: fsl_esdhc_imx: replace most #ifdefs by IS_ENABLED()
[ fsl_esdhc commit 52faec3182 ]

Make the code cleaner and drop the old-style #ifdef constructs where it is
possible.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-01-12 09:56:40 +09:00
Sean Anderson
41c6a22fc2 mmc: fsl_esdhc_imx: simplify esdhc_setup_data()
[ fsl_esdhc commit 7e48a028a4 ]

First, we need the waterlevel setting for PIO mode only. Secondy, both DMA
setup code is identical for both directions, except for the data pointer.
Thus, unify them.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12 09:56:40 +09:00
Sean Anderson
0167267769 mmc: fsl_esdhc_imx: use dma-mapping API
[ fsl_esdhc commit b1ba1460a4 ]

Use the dma_{map,unmap}_single() calls. These will take care of the
flushing and invalidation of caches.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12 09:56:40 +09:00
Sean Anderson
ed9e9b2213 mmc: fsl_esdhc_imx: simplify 64bit check for SDMA transfers
[ fsl_esdhc commit da86e8cfcb ]

SDMA can only do DMA with 32 bit addresses. This is true for all
architectures (just doesn't apply to 32 bit ones). Simplify the code and
remove unnecessary CONFIG_FSL_LAYERSCAPE.

Also make the error message more concise.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12 09:56:40 +09:00
Sean Anderson
4ea11bf241 mmc: fsl_esdhc_imx: fix mmc->clock with actual clock
[ fsl_esdhc commit 30f6444d02 ]

Fix mmc->clock with actual clock which is divided by the
controller, and record it with priv->clock.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12 09:56:39 +09:00
Sean Anderson
d39aa73ca8 mmc: fsl_esdhc_imx: drop redundant code for non-removable feature
[ fsl_esdhc commit commit 08197cb8df ]

Drop redundant code for non-removable feature. "non-removable" property
has been read in mmc_of_parse().

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
[ set MMC_CAP_NONREMOVABLE in plat->cfg.host_caps ]
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-01-12 09:56:39 +09:00
Sean Anderson
95d6b74cf8 mmc: fsl_esdhc_imx: clean up bus width configuration code
[ fsl_esdhc commit 07bae1de38 ]

This patch is to clean up bus width setting code.

- For DM_MMC, remove getting "bus-width" from device tree.
  This has been done in mmc_of_parse().

- For non-DM_MMC, move bus width configuration from fsl_esdhc_init()
  to fsl_esdhc_initialize() which is non-DM_MMC specific.
  And fix up bus width configuration to support only 1-bit, 4-bit,
  or 8-bit. Keep using 8-bit if it's not set because many platforms
  use driver without providing max bus width.

- Remove bus_width member from fsl_esdhc_priv structure.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
[ converted if statement to switch ]
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12 09:56:39 +09:00
Sean Anderson
2fd7d1f247 mmc: fsl_esdhc_imx: fix voltage validation
[ fsl_esdhc commit 5b05fc0310 ]

Voltage validation should be done by CMD8. Current comparison between
mmc_cfg voltages and host voltage capabilities is meaningless.
So drop current comparison and let voltage validation is through CMD8.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12 09:56:39 +09:00
Sean Anderson
308a4ff77d mmc: fsl_esdhc_imx: remove redundant DM_MMC checking
[ fsl_esdhc commit 2913926f3b ]

Remove redundant DM_MMC checking which is already in DM_MMC conditional
compile block.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12 09:56:39 +09:00
Sean Anderson
297d2de2ef mmc: fsl_esdhc_imx: make BLK as hard requirement of DM_MMC
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already
support it, so let's force to use it.

- Drop non-BLK support for DM_MMC introduced by below patch.
   66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled

- Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC).

- Use DM_MMC instead of BLK for conditional compile.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12 08:22:42 +09:00
Tom Rini
fe04d885fb Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-01-10 14:01:57 -05:00
Tom Rini
0dadad6d7c - disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
 - add changes to support VIM3/L android boot by using meson64_android.h config
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Merge tag 'u-boot-amlogic-20220107' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next

- disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
- add changes to support VIM3/L android boot by using meson64_android.h config
2022-01-09 07:56:31 -05:00
Gary Bisson
8f758683a8 usb: gadget: dwc2_udc_otg: set ep's desc during enable/disable
Fastboot support has been broken on platforms using dwc2 controller
since the gadget gets its max packet size from it.
This patch is the equivalent of 723fd5668f which fixed the same issue
but for the chipidea controller.

Fixes: 27c9141b11 ("usb: gadget: fastboot: use correct max packet size")

Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2022-01-08 11:16:03 -05:00
Marek Vasut
75f080df46 Revert "clk: Detect failure to set defaults"
This reverts commit 92f1e9a4b3.
The aforementioned patch causes massive breakage on all platforms which
have 'assigned-clock' DT property in their DT which references any clock
that are not supported by the platform clock driver. That can easily
happen either in SPL, or because the clock driver is reduced. Currently
it seems all iMX8M are affected and fail to boot altogether.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@oss.nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-07 09:30:45 -05:00
Ashok Reddy Soma
2a9caba1ce net: gem: Reduce timeout of mdio phy idle status check
Timeout for checking mdio phy idle status is 20seconds. In case of errors
this timeout will be too much. Reduce it to 100ms.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/1b73aa57b77587391e1bcd6d9f0480163367ed1b.1637237121.git.michal.simek@xilinx.com
2022-01-05 11:16:21 +01:00
Michal Simek
10c50b1fac net: zynq: Add support for PHY configuration in SGMII mode
SGMII configuration depends on proper GT setting that's why when node has
phys property call PSGTR driver to configure it properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/bbc8d7ed9d308199168e4455c7a3e3a5ac0890e7.1639562397.git.michal.simek@xilinx.com
2022-01-05 11:16:21 +01:00
Michal Simek
b5ffc9f758 net: zynq: Add support for GEM reset
Perform reset before core initialization.
Standard flow which close to 99% users are using getting all IPs out of
reset that there is no need to reset IP again. This is because of all low
level initialization is done in previous bootloader stage.
In SOM case these IPs are not touched by previous bootloader stage that's
why reset needs to be called before IP is accessed to make sure that it is
in correct state.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/5ae1c85b282d632bb62030f1f24a0065661b9153.1638804318.git.michal.simek@xilinx.com
2022-01-05 11:16:21 +01:00
Michal Simek
12133b11a7 net: zynq: Add support for mdio bus address decoding
Xilinx DTS files are using two way how to describe ethernet phy.

The first (already supported) has phy as subnode of gem node.
eth {
        phy-handle = <&phy0>;
         phy0: ethernet-phy@21 {
                ...
        };
};

The second has mdio subnode (with mdio name) which has phy subnode. This
structure allow hadling MDIO reset signal (based on Linux mdio.yaml)
eth {
        phy-handle = <&phy0>;
        mdio {
                phy0: ethernet-phy@21 {
                        ...
                };
        };
};

This patch adds support for the second case where mdio subnode
is found driver will look at its parent to find out which gem is handling
MDIO bus.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/6748007f0b6db9554d7a4b52352dce23ca403f9d.1638798796.git.michal.simek@xilinx.com
2022-01-05 11:16:21 +01:00
Ovidiu Panait
fc7220f0c4 microblaze: branch to base vector address on reset
Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze using the
CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option. Update the
reset routines to branch to this location instead.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-10-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Michal Simek
380bd08370 xilinx: firmware: Move dcache handling directly to pmufw load config
Core function should make sure that data is stored properly that's why move
cache operations directly to zynqmp_pmufw_load_config_object() to be able
to call it from other functions.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8c92edd3650ce34a3cfd1c1e4e9103980830b1fa.1637236800.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Michal Simek
0e789d26b7 clk: zynqmp: Fix gem tx/rx/ref clock handling
gemX_ref clock IDs starts at number 104. Till now it was at gemX_tx
location which wasn't correct.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d073e159b6316707306092a62bccb876cd89a602.1635506016.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Michal Simek
e959ade02c clk: zynqmp: Add support for setting up clock for USB
USB range is not enabled but for setting up frequency it is needed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/c55c423f48ca8f953a2dfbdcb25068278d8e5ad6.1635506016.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
T Karthik Reddy
3b441cf4e4 zynqmp: gpio: Add support for zynqmp gpio modepin driver
ZynqMP modepin driver has capability to get/set/check status of modepin
gpios. These modepins are accessed using xilinx firmware. In modepin
register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits
set/clear IO.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Tom Rini
5fec3c853d Pull request of efi-next
Documentation:
 
 * Add Sunxi board description
 
 UEFI:
 
 * Improvements to U-Boot running on top of UEFI
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Merge tag 'efi-next' of https://source.denx.de/u-boot/custodians/u-boot-efi into next

Pull request of efi-next

Documentation:

* Add Sunxi board description

UEFI:

* Improvements to U-Boot running on top of UEFI
2021-12-31 07:28:36 -05:00
Simon Glass
2996066110 efi: serial: Support arrow keys
At present only the backspace key is supported in U-Boot, when running as
an EFI app. Add support for arrows, home and end as well, to make the CLI
more friendly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-31 06:45:01 +01:00
Tom Rini
87a9aa604d - various fixes to the sandbox display support
- support for showing a logo without splash screen config
 - support for BMP drawing to depths other than 16bpp
 - tests for the different types of supported BMP images
 - support showing a logo when running coreboot via qemu
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Merge tag 'video-next-20211228' of https://source.denx.de/u-boot/custodians/u-boot-video into next

- various fixes to the sandbox display support
- support for showing a logo without splash screen config
- support for BMP drawing to depths other than 16bpp
- tests for the different types of supported BMP images
- support showing a logo when running coreboot via qemu
2021-12-28 11:28:31 -05:00
Tom Rini
b3f84a939f - mxsfb axi/disp_axi clock enable fix
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Merge tag 'video-20211228' of https://source.denx.de/u-boot/custodians/u-boot-video

- mxsfb axi/disp_axi clock enable fix
2021-12-28 11:19:26 -05:00
Tom Rini
880f3ee4f5 Pull request for efi-2022-01-rc4-4
UEFI:
 
 * allow for more than 16 KiB UEFI variable size when using StMM
 
 Others:
 
 * make watchdog sysreset compatible with separate poweroff driver
 * avoid OpenSSL deprecation warnings
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Merge tag 'efi-2022-01-rc4-4' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2022-01-rc4-4

UEFI:

* allow for more than 16 KiB UEFI variable size when using StMM

Others:

* make watchdog sysreset compatible with separate poweroff driver
* avoid OpenSSL deprecation warnings
2021-12-28 07:59:56 -05:00
Tom Rini
b2d1c828b9 Convert CONFIG_KIRKWOOD_GPIO to Kconfig
This converts the following to Kconfig:
   CONFIG_KIRKWOOD_GPIO

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
6328f95ea0 serial: arm_dcc: Use CONFIG_ARM64 not CONFIG_CPU_ARMV8
The only place we use CONFIG_CPU_ARMV8 was in the arm_dcc serial driver.
Switch this to CONFIG_ARM64 today, and if in the future we need finer
granularity tuning here, a new CONFIG_SERIAL option needs to be
introduced.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
2f8a6db5d8 Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig
In order to finish moving this symbol to Kconfig for all platforms, we
need to do a few more things.  First, for all platforms that define this
to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to
CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h.  This entails
also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk()
and updating a few preprocessor tests.

With that done, all platforms that define a value here can be converted
to Kconfig, and a fall-back of zero is sufficiently safe to use (and
what is used today in cases where code may or may not have this
available).  Make sure that code which calls this function includes
<clock_legacy.h> to get the prototype.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
068c41f1cc Finish conversion CONFIG_SYS_NAND_SELF_INIT to Kconfig
In order to finish this conversion we need to add a symbols for
SPL_SYS_NAND_SELF_INIT and TPL_SYS_NAND_SELF_INIT as there are cases
there where we need to, or need to not, use that framework as things
stand.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
bfb5387fe9 Convert CONFIG_TEGRA_NAND to Kconfig
This converts the following to Kconfig:
   CONFIG_TEGRA_NAND

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
7856cd5a6d Convert CONFIG_SYS_PCI_64BIT to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_PCI_64BIT

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:17 -05:00
Tom Rini
be7dbb60c5 Convert CONFIG_SYS_IMMR to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_IMMR

We do this by consolidating the SYS_IMMR options we have and providing
defaults.

We also, in the few places where M68K was also sharing code with these
platforms, define it within the file to CONFIG_SYS_MBAR to match usage.
This should be cleaned up longer term.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
954a2f8177 pci: Remove unused FSL_PCI_INIT code
The symbol CONFIG_FSL_PCI_INIT is no longer enabled anywhere, removed
now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
4d69303299 Convert CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT

In order to do this conversion, expose this option to the user and
use "save" not "safe" in the text.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
98ab831da7 Convert CONFIG_FSL_IFC to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_IFC

This is done via select statements to match previous logic.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:40:33 -05:00
Tom Rini
7e6a6fd821 Convert CONFIG_ENV_SPI_BUS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_SPI_BUS
   CONFIG_ENV_SPI_CS
   CONFIG_ENV_SPI_MAX_HZ
   CONFIG_ENV_SPI_MODE

As part of this, we use Kconfig to provide the defaults now that were
done in include/spi_flash.h.  We also in some cases change from using
CONFIG_ENV_SPI_FOO to CONFIG_SF_DEFAULT_FOO as those were the values in
use anyhow as ENV was not enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:40:33 -05:00
Tom Rini
5fd4a7ed0c Clarify CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW in Kconfig
This is a "hex" prompt but the default value was given as an int.
Switch the default to hex (0x0) and remove the defconfigs that were
using the default, but as hex before.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:40:33 -05:00
Giulio Benetti
f36b3f8f17 video: mxsfb: fix clk_get_by_name() return value check
If clk_get_by_name() returns 0 it means it executed successfully while now
we consider it as an error. So let's check if return value is negative to
be an error. Otherwise this prevents "axi" and "disp_axi" to be enabled.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-12-27 00:30:37 +01:00
Simon Glass
7a8555d871 video: Show the U-Boot logo by default
Enable this for boards with a display, unless they are using the SPLASH
feature.

This shows a U-Boot logo on boards with a display, which seems like a
useful thing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:33:11 +01:00
Simon Glass
84e63abfff video: Support showing the U-Boot logo
Show the U-Boot logo by default. This is only 7KB in size so seems like
a useful default for boards that enable a display.

If SPLASH_SCREEN is enabled, it is not enabled by default, so as not to
conflict with that feature.

Also disable it for tests, since we don't want to complicate the output.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:32:46 +01:00
Simon Glass
2c8ee30b97 video: Drop VIDEO_LOGO from cfb_console
This driver is obsolete and only used by nokia_rx51. It should be deleted.
For now, drop the VIDEO_LOGO code to avoid confusion with the new
implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:25:29 +01:00
Simon Glass
64cfeda8ae video: Convert CONFIG_VIDEO_LOGO to Kconfig
This converts the following to Kconfig:
   CONFIG_VIDEO_LOGO

Note that this option depends on CONFIG_DM_VIDEO now, since cfb_console is
deprecated. The only relevant code is now in splash.c

Drop the check for DM_VIDEO in that file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:24:46 +01:00
Simon Glass
cd4fb0f054 video: Drop #ifdefs from video_bmp
Convert the current preprocessor macros to C code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:24:29 +01:00
Simon Glass
4ea1548210 video: theadorable: Use RGB565 for BMP blitting
At present this uses RGB555 format for blitting to a display. Sandbox uses
565 and that seems to be more normal for BMP as well. Update the code
accordingly and add a test.

Note that this likely breaks the theadorable board so we may need to
discuss supporting both formats.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:23:52 +01:00
Simon Glass
f5aa93eb53 video: Tidy up 24/32 BMP blitting
Drop the unnecessary brackets.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
ecb8b4f8f3 video: Drop the uclass colour map
We don't need this anymore since we use the BMP palette directly. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
646e169aa0 video: bmp: Update RLE8 support to use the write function
Update this code to use write_pix8() rather than writing the pixels only
for a single supported display depth. This allows us to support any
depth.

Add some more tests too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
51f92c1430 video: Move BMP pixel-writing into a function
At present the code that writes to a pixel is quite convoluted. It uses a
colour map which is in the uclass and the same code is repeated in
different places within video_bmp_display().

As a first step, create a function which can write a pixel from the
bitmap, no matter what the display depth. Use any provided palette
directly, rather than using the uclass version.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
19c828c525 video: Drop fb_put_byte() el at
These functions are not used with driver model, nor in any U-Boot boards.
Drop them and inline the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
6a19e938f8 video: Expand video debugging buffer size
On sandbox these addresses are 16 hex digits log so we need more space
for the debug string. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
8657ad43f3 sandbox: video: Add BMP tests for 32bpp and 8bpp modes
Add a few more tests for BMP rendering. Use a back door into the sandbox
SDL driver to adjust the resolution at runtime.

The truetype code does not support 8bpp. Add this so that the display is
not blank when running in this mode.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
8405174391 sandbox: video: Correct the address of the copy base
The intention is for the copy base to start halfway through the
frame-buffer area. At present is it actually below the frame buffer,
which could have anything in it (probably it is malloc space). Fix
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
301af2388a video: sandbox: Set a maximum frame-buffer size
If U-Boot starts with the frame buffer set to 16bpp but then runs a test
that uses 32bpp, there is not enough space. Update the driver to use the
maximum possible frame-buffer size, to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
250e735c69 video: sandbox: Avoid duplicate display windows
When unit tests are run they currently create a new window. Update the
code so that the old one is removed first. This avoids the confusion as to
which one is active.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
0fe5e9481e sandbox: video: Support 8bpp depth
At present sandbox only supports 16 and 32bpp depths, since those are the
easy ones with SDL.

We can support other depths by manually converting the pixel formats. Add
support for this, to enable an 8ppp (monochrome) format.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Tom Rini
c9964879ab Merge https://source.denx.de/u-boot/custodians/u-boot-spi 2021-12-26 14:07:41 -05:00
Heinrich Schuchardt
88c4cbedfb sysreset: watchdog: watchdog cannot power off
The watchdog system reset driver can reboot the device but it cannot power
it off. If power off is requested, the driver should not reset the system
but leave powering off to one of the other system reset drivers.

As power cycling is typically not a feature of a watchdog driver the reset
types SYSRESET_POWER and SYSRESET_POWER_OFF shall both be excluded.

Fixes: 17a0c14164 ("dm: sysreset: add watchdog-reboot driver")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-26 06:49:14 +01:00
Quentin Schulz
2206356a3e power: pmic/fan53555: allow dm be omitted by SPL
Allow the dm driver be omitted by SPL.

Cc: Quentin Schulz <foss+u-boot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 15:15:03 +08:00
Simon Glass
6476c4d981 dm: core: Allow getting some basic stats
Add a function that returns some basic stats about driver model. For now
we only have two.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:40 -05:00
Pali Rohár
c68a73c559 pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTR
The global data pointer is not used in this driver, remove it's
declaration.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-21 07:42:01 +01:00
Pali Rohár
e1cee89e28 pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size()
Use more appropriate resource_size() function when working with data in
struct resource.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-21 07:40:26 +01:00
Pali Rohár
4a1a593d17 pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup
Function mvebu_pcie_setup_wins() sets up all other BARs, so move setup of
BAR[0] to this function to have common code at one place.

In the past, commit 193a1e9f19 ("pci: pci_mvebu: set BAR0 after memory
space is set") moved setup of BAR[0] to another location, due to ath10k
not working in kernel, but the reason why was unknown, but it seems to
work now, and we think the issue then was cause by the PCIe Root Port
presenting itself as a Memory Controller and therefore U-Boot's code
have overwritten the BAR. Since the driver now ignores any write
operations to PCIe Root Port BARs, this should not be an issue anymore.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-21 07:40:26 +01:00
Tom Rini
4afab30cae Prepare v2022.01-rc4
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Merge tag 'v2022.01-rc4' into next

Prepare v2022.01-rc4
2021-12-20 17:12:04 -05:00
Stefan Roese
ccea46c05b i2c: mvtwsi: Swab the register address if its size is > 1
Testing on Armada XP with an EEPROM using register address with size
of 2 has shown, that the register address bytes are sent to the I2C
EEPROM in the incorrect order. This patch swabs the address bytes so
that the correct address is transferred to the I2C device.

BTW: This worked without any issues before migrating Armada XP to
DM I2C.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Samuel Holland <samuel@sholland.org>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Pali Rohár <pali@kernel.org>
Cc: Marek Behún <marek.behun@nic.cz>
Tested-by: Marek Behún <marek.behun@nic.cz>
2021-12-20 07:57:48 +01:00
Pali Rohár
c53a30f039 arm: mvebu: serial: Add me as co-maintainer and author of Marvell serial drivers
There is no maintainer entry for serial_mvebu_a3700.c. Add entry with Pali
and Stefan as maintainers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Pali Rohár
22f69fc79b arm: mvebu: pci: Add me as co-maintainer and author of Marvell PCIe drivers
There is no maintainer entry for pci-aardvark.c. Add entry for
pci-aardvark.c and pci_mvebu.c with Pali and Stefan as maintainers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Pali Rohár
d368e10705 phy: marvell: a3700: Convert to official DT bindings in COMPHY driver
Convert A3720 common PHY driver to official DT bindings.

This puts us closer to be able to synchronize A3720 device-trees with
those from Linux.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Marcin Wojtas <mw@semihalf.com>
Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Marek Behún
2105cd0421 fdt_support: Remove FDT_STATUS_FAIL_ERROR_CODE
Since no one uses this feature and I am not aware of any parsers of this
in Linux, remove it.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-19 09:50:47 +01:00
Marek Behún
68a2faa9bc treewide: Use fdt_create_phandle() where appropriate
Replace fdt_alloc_phandle() with subsequent fdt_set_phandle() by
fdt_create_phandle().

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
2021-12-19 09:50:47 +01:00
Stefan Roese
0cbd3d8121 arm: mvebu: axp: ddr: Switch to using DM I2C API
No functional change intended. This patch switches from the legacy I2C
API to the DM I2C API, so that this code can be used with DM I2C
enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Stefan Roese
622882893d arm: mvebu: axp: Remove unreferenced ddr3_get_eprom_fabric() function
This function is not referenced in mainline U-Boot. Let's remove now.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
AKASHI Takahiro
19b241c61f blk: add a helper function, blk_probe_or_unbind()
This function will be commonly used in block device drivers
in the succeeding patches.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-18 12:05:19 +01:00
Tom Rini
b9c9ce8a40 First set of u-boot-at91 features for the 2022.04 cycle
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Merge tag 'u-boot-at91-2022.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2022.04 cycle:

This feature set includes : support for the new QSPI hardware on
sama7g5, small fixes on sam9x60 and sama7g5, some additions of commands
and PIO controller on sam9x60/sam9x60ek.
2021-12-17 07:25:34 -05:00
Tien Fong Chee
4720b83d2c arm: socfpga: arria10: Enable double peripheral RBF configuration
Double peripheral RBF configuration are needed on some devices or boards
to stabilize the IO configuration system.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17 12:58:01 +08:00
Ram Narayanan
d7b1d8259e mtd: spi-nor-ids: Add support for W25Q01JV
Adds support for Winbond's new 128MB spi nor flash.

datasheet: https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevC%2005032021%20Plus%20dummy.pdf

Signed-off-by: Ram Narayanan <ramnara@linux.microsoft.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-12-16 12:58:47 +05:30
Tom Rini
5b20efeafe Clock patches for v2022.01-rc3
This adds better logging support for many CCF drivers, and clarifies some
 documentation regarding clk_get_rate.
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Merge tag 'clk-2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-clk

Clock patches for v2022.01-rc3

This adds better logging support for many CCF drivers, and clarifies some
documentation regarding clk_get_rate.
2021-12-15 14:51:44 -05:00
Patrick Delaunay
560e1e0050 clk: define LOG_CATEGORY for generic and ccf clocks
Define LOG_CATEGORY to allow filtering with log command
for generic clock and CCF clocks.

This patch also change existing printf, debug and pr_ macro
to log_ or dev_ macro.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15 12:16:16 -05:00
Patrick Delaunay
572c446e98 clk: cosmetic: reorder include files
Reorder include files in the U-Boot expected order:

the common.h header should always be first,
followed by other headers in order,
then headers with directories,
then local files.

It is a preliminary step for next patch.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15 12:16:16 -05:00
Pali Rohár
fed5beca18 arm: a37xx: pci: Do not allow setting ROM BAR on PCI Bridge
PCI Bridge which represents aardvark PCIe Root Port has Expansion ROM Base
Address register at offset 0x30 but its meaning is different than PCI's
Expansion ROM BAR register. Only address format of register is same.

In reality, this device does not have any configurable PCI BARs. So ensure
that write operation into BARs (including Expansion ROM BAR) is noop and
registers always contain zero address which indicates that bars are
unsupported.

Fixes: cb056005dc ("arm: a37xx: pci: Add support for accessing PCI Bridge on root bus")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-15 08:57:36 +01:00
Pali Rohár
a48e4287d6 pci: pci_mvebu: Do not allow setting ROM BAR on PCI Bridge
The PCI Bridge which represents mvebu PCIe Root Port has Expansion ROM
Base Address register at offset 0x30 but its meaning is different that
of PCI's Expansion ROM BAR register, although the address format of
the register is the same.

In reality, this device does not have any configurable PCI BARs. So
ensure that write operation into BARs (including Expansion ROM BAR) is a
noop and registers always contain zero address which indicates that BARs
are unsupported.

Fixes: a7b61ab58d ("pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-15 08:57:36 +01:00
Marek Behún
e967c84a6d pci: pci_mvebu, pci_aardvark: Fix size of configuration cache
Since u32 takes up 4 bytes, we need to divide the number of u32s by 4
for cfgcache.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-15 08:57:36 +01:00
Adam Ford
182754f43a net: ravb: Support multiple clocks
The RZ/G2 series uses an external clock as a reference to the AVB.
If this clock is controlled by an external programmable clock,
it must be requested by the consumer or it will not turn on.
In order to do this, update the driver to use bulk enable and
disable functions to enable clocks for boards with multiple clocks.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-12-13 00:37:28 +01:00
Simon Glass
d8063dc373 efi: Add a media/block driver for EFI block devices
Add a block driver which handles read/write for EFI block devices. This
driver actually already exists ('efi_block') but is not really suitable
for use as a real U-Boot driver:

- The operations do not provide a udevice
- The code is designed for running as part of EFI loader, so uses
    EFI_PRINT() and EFI_CALL().
- The bind method probes the device, which is not permitted
- It uses 'EFI' as its parent device

The new driver is more 'normal', just requiring its platform data be set
up in advance.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-09 11:43:25 -08:00
Simon Glass
42b7f4212a efi: Add uclass for devices provided by UEFI firmware
UCLASS_EFI_LOADER is used for devices created by applications and
drivers loaded by U-Boots UEFI implementation.

This patch provides a new uclass (UCLASS_EFI_MEDIA) to be used for devices
that provided by a UEFI firmware calling U-Boot as an EFI application.

If the two uclasses can be unified, is left to future redesign.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-09 11:43:25 -08:00
Simon Glass
2abd8d1c99 efi: Rename UCLASS_EFI and IF_TYPE_EFI
These names are better used for access to devices provided by an EFI
layer. Use EFI_LOADER instead here, since these are only available in
U-Boot's EFI_LOADER layer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-09 11:43:25 -08:00
Tudor Ambarus
2fd1b97f33 spi: atmel-quadspi: Add support for SAMA7G5 QSPI
sama7g5 QSPI has:
1/ One Octal Serial Peripheral Interfaces (QSPI0) Supporting Up to
   200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported
2/ One Quad Serial Peripheral Interfaces (QSPI1) Supporting Up to
   90 MHz DDR/133 MHz SDR

The QSPI controller of SAMA7G5 uses different clock domains, hence extra
synchronization operations must be performed before accessing some
registers. Differentiate between the versions of the IP using has_gclk.
Differentiate between QSPI0 and QSPI1 with has_octal.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-12-07 08:55:22 +02:00
Simon Glass
c229cd2b6e ide: Drop ATA_PORT_ADDR
This is not needed anymore. Drop it to simplify the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-12-05 09:26:26 -07:00
Simon Glass
7ee2016d61 ide: Drop unused CONFIG options
CONFIG_SYS_ATA_PORT_ADDR is not used in the code anymore. Drop it and use
ATA_PORT_ADDR() locally instead.

Drop CONFIG_IDE_RESET_ROUTINE and CONFIG_IDE_SWAP_IO which are also
unused.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-05 09:26:26 -07:00
Simon Glass
93e1edffb0 Convert CONFIG_KEYBOARD to Kconfig
This converts the following to Kconfig:
   CONFIG_KEYBOARD

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-05 09:26:26 -07:00
Simon Glass
32c8566f13 sandbox: Drop CONFIG_HOST_MAX_DEVICES
This can go in the related header file. Drop the CONFIG option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-12-05 09:23:15 -07:00
Tom Rini
558002a0f2 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2021-12-03 09:02:49 -05:00
Alexander Preißner
fe67ba7418 drivers: core: lists: fix for loop index type
* fixes the bug in function bind_drivers_pass that for
CONFIG_CC_OPTIMIZE_FOR_SIZE=n and no entries in the driver_info list,
i.e. n_ents == 0, the processor steps into the first loop iteration
despite the loop condition being false.
* the Xilinx Zynq-7000 device would eventually hang due to an attempted
access to an invalid memory address
* the bug is fixed by changing the type of idx from uint to int

Board: zynq-zybo
Target: ARM
Compiler: arm-none-eabi-gcc 9.2.1

Signed-off-by: Alexander Preissner <fpga-garage@preissner-muc.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2021-12-02 09:15:43 -07:00
Tom Rini
f89615088f Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net into next
- New Broadcom NetXtreme driver
- Support for socat for netconsole
- Felix switch soft reset fix
2021-12-02 07:16:04 -05:00
Padmarao Begari
0dc0d1e094 i2c: Add Microchip PolarFire SoC I2C driver
Add I2C driver code for the Microchip PolarFire SoC.
This driver supports I2C data transfer and probe for I2C
slave addresses.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-12-02 16:43:51 +08:00
Padmarao Begari
0d914ad10d net: macb: Remove Microchip compatible string
Remove the microchip compatible string and default compatible "cdns,macb"
support both 32-bit and 64-bit DMA access.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-12-02 16:43:51 +08:00
Marek Vasut
3fbd17aadf net: dwc_eth_qos: Enable clock in probe
Enable DWC IP clock in driver probe, so the MII access is possible even
outside of active network transfers. This is particularly useful when
using 'mii' or 'mdio' commands to explore PHY state, neither of which
works with DWMAC currently due to the disabled clock.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-12-02 08:35:44 +02:00
Marek Vasut
8777033722 net: eth-phy: Handle gpio_request_by_name() return value
The gpio_request_by_name() returns zero in case of success, however the
conditional return value check in gpio_request_by_name() checks only for
(ret != -ENOENT) and if the condition is true, returns ret outright.

This leads to a situation where successful gpio_request_by_name() return
leads to immediate successful eth_phy_of_to_plat() return as well, and
to skipped parsing of "reset-assert-us" and "reset-deassert-us", so the
PHY driver operates with valid reset GPIO, but with assert/deassert times
set to default, which is 0, instead of the values from DT. This breaks
PHY reset.

Fix this by checking if return value is non-zero and then for this one
single allowed non-zero return value, -ENOENT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-12-02 08:35:37 +02:00
Bharat Gooty
5a5bba053d net: brcm: netXtreme driver
Broadcom bnxt L2 driver support. Used by the Broadcom
iproc platforms.

Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

Signed-off-by: Roman Bacik <roman.bacik@broadcom.com>
2021-12-02 08:34:01 +02:00
Ramon Fried
6d1857c8d5 driver: net: Makefile: order file alphabetically
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
2021-12-02 08:34:01 +02:00
Radu Bulie
8c1a6957b1 drivers: net: Soft reset felix switch core
It turns out that in custom designs if the system is reset
multiple times in conjunction with a slight increase in external
temperature, the felix  switch starts to behave in a strange way:
packets are no longer received on the ENECT interface connected
to the L2switch internal port (the TX side of internal port stops working
or the packets do not reach there. It is not very clear where
the packets remain blocked. None of the counters points to a disruption
in the L2switch)
The issue is not reproducible on NXP reference designs.

It was observed that by adding the switch core reset, the problem
goes aways, even if intensive testing in temperature chambers
is applied.

The current patch performs soft reset on the switch core to ensure proper
operation of the L2switch.

Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com>
Reviewed-by: Ramon  Fried <rfried.dev@gmail.com>
2021-12-02 08:34:01 +02:00
Michal Simek
b3425a3f4e mtd: spi: Remove SF_DUAL_FLASH symbol from Kconfig
This symbol is not used anywhere in the code. Just enable in couple of
defconfigs but it does nothing that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-12-02 11:33:01 +05:30
Marek Vasut
846d1d9c11 mtd: cqspi: Wait for transfer completion
Wait for the read/write transfer finish bit get actually cleared,
this does not happen immediately on at least SoCFPGA Gen5.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
2021-12-02 11:10:40 +05:30
Patrick Delaunay
af13df7014 dm: add debug message when failed to select the default pinctrl
Add a message on probe in driver model core when the default
pinctrl selection failed.

This message is displayed only when the pinctrl API is
implemented, i.e. when result is not ENOSYS.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-01 13:33:45 -05:00
Tom Rini
c7fad78ec0 Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_BR0_PRELIM
   CONFIG_SYS_OR1_PRELIM
   CONFIG_SYS_BR1_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR2_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR3_PRELIM
   CONFIG_SYS_OR3_PRELIM
   CONFIG_SYS_BR4_PRELIM
   CONFIG_SYS_OR4_PRELIM
   CONFIG_SYS_BR5_PRELIM
   CONFIG_SYS_OR5_PRELIM
   CONFIG_SYS_BR6_PRELIM
   CONFIG_SYS_OR6_PRELIM
   CONFIG_SYS_BR7_PRELIM
   CONFIG_SYS_OR7_PRELIM

This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms
that can set these values do so.  Add the relevant SYS_BRx_PRELIM_BOOL
to platforms that had not been previously migrated.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-01 10:58:10 -05:00
Patrick Delaunay
b2ac9645e6 ram: stm32mp1: remove __maybe_unused on stm32mp1_ddr_setup
Since the commit f42045b2e7 ("stm32mp15: replace CONFIG_TFABOOT when
it is possible") the function stm32mp1_ddr_setup is always called so the
__maybe_unused can be removed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30 16:43:28 +01:00
Patrick Delaunay
d72e7bbe7c ram: stm32mp1: compute DDR size from DDRCTL registers
Compute the DDR size from DDR controller register (mstr and addrmap)
in U-Boot proper as the DDR information are useful only for SPL
but not for U-Boot proper, for example with TFABOOT.

This patch simplify U-Boot DT when several DDR size are supported
and support of next SOC in STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 16:43:28 +01:00
Patrick Delaunay
6cdeb323b8 video: stm32: stm32_ltdc: align framebuffer on 2MB
Align the framebuffer size on MMU_SECTION_SIZE in kernel, = max 2MB for
LPAE for armV7, to avoid issue with the simple frame buffer activation,
when U-Boot add a reserved memory in the kernel device tree to preserve
the splash screen until Linux driver initialization.

See Linux documentation for details:
Documentation/devicetree/bindings/display/simple-framebuffer.yaml

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30 16:43:28 +01:00
Patrick Delaunay
2e2e6d8cac video: Add video_is_active function
Add the helper function video_is_active() to test if one video device
is active.

This function can be used in board code to execute operation
only when the display is probed / really used.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30 16:43:28 +01:00
Patrick Delaunay
b3c29dc9e5 stm32mp1: ram: remove tuning support
Remove the DDR interactive command tuning, as the support of a predefined
DDR PHY tuning is removed for STM32MP1 driver in SPL and in TF-A
and the result of this tuning will be never used.

Moreover this SW tuning procedure can failed on some hardware
configuration (to many BIST errors and no convergence); it will be no
more supported in the next delivery of the DDR utilities included in
the CubeMX tool of STMicroelectronics.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30 16:43:28 +01:00
Patrick Delaunay
9819fe345c stm32mp1: ram: remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.

The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by the CubeMX DDR utilities.

This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
  the optional parameter "st,phy-cal"

After this patch, the built-in calibration is always executed
and the calibration registers are moved in the phy dynamic part;
that allows manual tests.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30 16:43:28 +01:00
Patrick Delaunay
4831ba2903 stm32mp1: ram: add read valid training support
Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.

This training is supported on the PUBL integrated in the STM32MP15x
DDR subsystem and it is not required for DDR3.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30 16:43:28 +01:00
Marek Vasut
8e5266eefd mmc: stm32_sdmmc2: Add support for probing bus voltage level translator
Add support for testing whether bus voltage level translator is present
and operational. This is useful on systems where the bus voltage level
translator is optional, as the translator can be auto-detected by the
driver and the feedback clock functionality can be disabled if it is
not present.

The translator test sets CMD high to avoid interfering with a card, and
then verifies whether signal set on CK is detected on CKIN. If the signal
is detected, translator is present, otherwise the CKIN feedback clock are
disabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Yann Gautier <yann.gautier@foss.st.com>
2021-11-30 16:43:28 +01:00
Tom Rini
4a14bfffd4 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- turris_omnia: enable A385 watchdog before disabling MCU watchdog
  (Pali)
- a37xx: Reset whole UART when changing parent clock from TBG to XTAL
  (Pali)
2021-11-30 08:59:22 -05:00
Heinrich Schuchardt
c3de051c41 tis: fix tpm_tis_remove()
tpm_tis_remove() leads to calling tpm_tis_ready() with the IO region
unmapped and chip->locality == -1 (locality released). This leads to a
crash in mmio_write_bytes().

The patch implements these changes:

tpm_tis_remove(): Unmap the IO region after calling tpm_tis_cleanup().

tpm_tis_cleanup(): Request locality before IO output and releasing
locality.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-30 14:11:05 +02:00
Patrick Delaunay
4c5956086a pinctrl: stmfx: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30 11:20:34 +01:00
Pali Rohár
5db5815e99 serial: a37xx: Reset whole UART when changing parent clock from TBG to XTAL
Sometimes UART stops transmitting characters after UART clock is changed
back to XTAL. In this state UART fifo is always full. Kernel during early
boot wants to print output on UART and is waiting for non-empty UART fifo.
Which leads to CPU hangup without any (debug) output on UART.

Marvell Armada 3700 Functional Specifications says that for programming
fractional divisor registers it is required to disable UART, enable
loopback mode, reset fifos, program registers, disable loopback mode,
release reset of fifos and enable UART.

But these steps do not fix above mentioned issue that UART hangup. Also
gating UART clock does not help. And even resetting UART state machines do
not help.

Experiments showed that UART fifo is unblocked after board is being reset
(during board reset UART HW transmit UART fifo even CPU is not executing
kernel/bootloader anymore).

And another experiments showed that same workaround can be achieved also
by external reset of UART HW (without need to reset board).

So do not implement any of "Marvell recommended" steps from Functional
Specifications as they do not work. And rather prior changing parent clock
back to XTAL, do external reset of UART HW. This operation also resets all
UART registers, so basically it also sets UART clock to default, which is
XTAL. It is unknown why UART hangups and enters such broken state.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-30 08:31:04 +01:00
Tom Rini
2402c93130 Prepare v2022.01-rc3
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Merge tag 'v2022.01-rc3' into next

Prepare v2022.01-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-29 12:00:57 -05:00
Simon Glass
29fe555dec dm: core: Add a way to count the devices in a uclass
Add a function that returns the number of devices in a uclass. This can be
helpful in sizing an array that needs to hold a list of them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28 16:51:51 -07:00
Simon Glass
4b030177b6 dm: core: Allow finding children / uclasses by partial name
In some cases it is useful to search just by a partial name, such as
when looking for a sibling device that has a common name substring. Add
helper functions to handle these requirements.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28 16:51:51 -07:00
Simon Glass
075bfc9575 dm: core: Add a way to obtain a string list
At present we support reading a string list a string at a time. Apart
from being inefficient, this makes it impossible to separate reading of
the devicetree into the of_to_plat() method where it belongs, since any
code which needs access to the string must read it from the devicetree.

Add a function which returns the string property as an array of pointers
to the strings, which is easily used by clients.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28 16:51:51 -07:00
Simon Glass
32c6a8e1f8 dm: core: Fix up string-function documentation
The details for of_property_read_string_helper() and
ofnode_read_string_index() are a little inaccurate. Fix up the comments to
avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28 16:51:51 -07:00
Simon Glass
8044318305 dm: core: Fix handling of uclass pre_unbind method
This method is currently called after the platform data has been freed.
But the pre_unbind() method may wish to access this, e.g. to free some
data structures stored there.

Split the unbinding of devices into two pieces, as is done with removal.
This corrects the problem.

Also tidy a code-style issue in device_remove() while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28 16:51:51 -07:00
Simon Glass
ce34a6653f mmc: Allow for children other than the block device
At present the MMC uclass assumes that the only child it can have is a
block device. Update this so we can add a bootmethod too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28 16:51:51 -07:00
Simon Glass
0bf61aced2 sandbox: mmc: Support a backing file
Provide a way for sandbox MMC to present data from a backing file. This
allows a filesystem to be created on the host and easily served via an
emulated mmc device.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28 16:51:51 -07:00
Etienne Carriere
48108f3a6a firmware: scmi: Add OP-TEE transport
This change implements an SCMI transport for agent interfacing the
OP-TEE SCMI service. OP-TEE provides an SCMI PTA (Pseudo-TA) for
non-secure world to send SCMI messages over an identified channel.
The driver implemented here uses a SMT shared memory for passing
messages between client and server.

The implementation opens and releases channel resources for each
passed SCMI message so that resources allocated (sessions) or
registered (shared memory areas) in OP-TEE firmware are released for
example before relocation as the driver will likely allocate/register
them back when probed after relocation.

The integration of the driver using dedicated config switch
CONFIG_SCMI_AGENT_OPTEE is designed on the model posted to the
U-Boot ML by Patrick Delaunay [1].

Link: [1] https://lore.kernel.org/all/20211028191222.v3.4.Ib2e58ee67f4d023823d8b5404332dc4d7e847277@changeid/
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-23 13:54:43 -05:00
Etienne Carriere
7c1a9b2eb9 tee: optee: remove unused duplicated login Id macros
Remove unused OPTEE_MSG_LOGIN_* ID macros as suitable TEE_LOGIN_* ID
macros are already defined tee.h.

Cc: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2021-11-23 13:53:03 -05:00
Etienne Carriere
32190a959d firmware: scmi: smccc transport: simplify probe sequence
Minor simplification in scmi_smccc_probe() exit sequence.

Cc: Simon Glass <sjg@chromium.org>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-23 13:53:03 -05:00
Etienne Carriere
3de5aef451 firmware: scmi: smccc transport: use plat data, not priv data
Change SCMI smccc transport drivers to use platform data rather
than private data for channel reference since it only stores platform
data retrieved from the DT. Consequently the probe handler is replaced
with a of_to_plat handler.

Cc: Simon Glass <sjg@chromium.org>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-23 13:53:03 -05:00
Etienne Carriere
88a304f864 firmware: scmi: mailbox transport: use plat data, not priv data
Change SCMI mailbox transport drivers to use platform data rather
than private data for channel reference since it only stores platform
data retrieved from the DT. Consequently the probe handler is replaced
with a of_to_plat handler.

Cc: Simon Glass <sjg@chromium.org>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-23 13:53:03 -05:00
Etienne Carriere
7b4993907a firmware: scmi: mailbox transport: fix probe failure implementation
Correct scmi mailbox probe function that can't free the scmi channel
instance since its auto-allocated by the device model framework.

Cc: Simon Glass <sjg@chromium.org>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-23 13:53:03 -05:00
Patrick Delaunay
73ead2bcc5 firmware: scmi: add configs to select the supported agents
Add two configs CONFIG_SCMI_AGENT_MAILBOX and CONFIG_SCMI_AGENT_SMCCC
to select the supported agents as all the agents are not supported.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2021-11-23 13:53:03 -05:00
Patrick Delaunay
d47c4fea8c power: regulator: scmi: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-11-23 13:53:03 -05:00
Patrick Delaunay
31dc56fca5 clk: scmi: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2021-11-23 13:53:03 -05:00
Patrick Delaunay
d96315411c reset: scmi: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2021-11-23 13:53:03 -05:00
Samuel Holland
f11513d997 net: phy: realtek: Add tx/rx delay config for 8211e
Some boards need to change the tx/rx delay config in order for
gigabit Ethernet to work.

In Linux commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
delay config"), Realtek documented the bits for overriding the delays
from the hardware straps.

Copy the logic from linux, so the delay config is set from the PHY's
interface type (the phy-mode property in the device tree).

This removes the need for a one-off workaround for the Pine A64+ board.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:56 +02:00
Dylan Hung
8b41dedd40 drivers: net: add Aspeed MDIO driver
Add a driver for the MDIO interface for Aspeed AST2600 SOC.  The driver
only supports clause 22 for now.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-11-23 09:57:56 +02:00
Bin Meng
10aaefba52 net: tsec: Make redundant_init() static
redundant_init() is only called in the tsec driver. Make it static.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:56 +02:00
Bin Meng
04c350c337 net: fec_mxc: Declare 'promisc' as bool
priv->promisc is used as the parameter of the set_promisc() call
which accepts a bool type instead of char.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:56 +02:00
Peter Hoyes
d5ba6188df cmd: pxe_utils: Check fdtcontroladdr in label_boot
If using OF_CONTROL, fdtcontroladdr is set to the fdt used to configure
U-Boot. When using PXE, if no fdt is defined in the menu file, and
there is no fdt at fdt_addr, add fall back on fdtcontroladdr too.

We are developing board support for the Armv8r64 FVP using
config_distro_bootcmd. We are also using OF_BOARD and would like the
PXE boot option to default to the fdt provided by board_fdt_blob_setup.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:56 +02:00
Vladimir Oltean
7f7e73eee3 net: dsa: sja1105: add support for SGMII
The list of ports which support SGMII depending on switch generation is
available here:
https://www.kernel.org/doc/html/latest/networking/dsa/sja1105.html#port-compatibility-matrix

SGMII can either be used to connect to an external PHY or to the host
port. In the first case, the use of in-band autoneg is expected, in the
last, in-band autoneg is expected to be turned off (fixed-link). So the
driver supports both cases.

SGMII support means configuring the PCS and PMA. The PCS is a Synopsys
Designware XPCS, in Linux this has a separate driver but here it is
embedded within the sja1105 driver. If needed it can be taken out later,
although we would need a UCLASS_PCS for it, which we don't have atm.

Nonetheless, I did go all the way to export an internal MDIO bus for PCS
access, because it is nice to be able to debug the PCS through commands
such as:

=> mdio read ethernet-switch@1-pcs 4 1f.0
Reading from bus ethernet-switch@1-pcs
PHY at address 4:
31.0 - 0x1140

The internal MDIO bus is not registered with DM because there is no
udevice on it, as mentioned. But the XPCS code can still be ripped out,
as needed.

I did not add support for 2500base-x because I do not expect this
interface type to be used as a boot source for anybody, it would just
add unnecessary bloat.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:56 +02:00
Vladimir Oltean
f24b666b22 net: dsa: add driver for NXP SJA1105 L2 switch
The SJA1105 driver is largely reused from Linux. Its programming model
is that it is blank out of reset, and it waits for a static
configuration stream over SPI, which contains all runtime parameters (it
has no notion of "default values").

Keeping a binary array for the configuration stream would have meant
that aspects such as the CPU port and the MAC speeds could have not been
configured easily, and would have been static and board-dependent.
Live-patching the binary array means recalculating the static config
table CRCs, which is not a fun process.

So we create an abstraction over the static config tables, using the
packing API, same as in Linux. The tables are kept as C structures, and
the binary configuration stream is constructed on-the-go, with CRC and
all.

All static config tables instantiated in this driver are mandatory.
The hardware reference manual can be found at:
https://www.nxp.com/docs/en/user-guide/UM10944.pdf

For tagging, a simplified version of tag_8021q from Linux is used. The
VLAN EtherType is the same (0xdadb) but since we don't want switching in
U-Boot, there is no reason to have a TX VLAN and an RX VLAN for each
port. We just need the RX VLANs to act as the unique pvid of each
front-panel port, to decode the switch port number. The RX VLAN is used
for both RX and TX.

The device tree bindings are the same as in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:56 +02:00
Vladimir Oltean
e3789a7262 net: dsa: felix: configure the in-band autoneg property based on OF node info
Instead of trying to guess which operating modes need in-band
negotiation to be active and which ones don't, parse the available
information from the device tree. That will be correct in the cases we
can already guess, and more.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:55 +02:00
Vladimir Oltean
2dd6acb795 net: introduce a helper to determine whether to use in-band autoneg
Certain serial SERDES protocols like 1000base-x, 2500base-x, SGMII,
USXGMII can operate either in a mode where the PHY (be it on-board or
inside an SFP module) passes the link parameters (speed, duplex, pause)
to the MAC through in-band through control words standardized by IEEE
802.3 clause 37, or in a mode where the MAC must configure (force) its
link parameters based on information obtained out-of-band (MDIO reads,
guesswork etc).

In Linux, the OF node property named "managed" is parsed by the phylink
framework, and the convention is that if a driver uses phylink, then the
presence of this property means that in-band autoneg should be enabled,
otherwise it shouldn't.

To be compatible with the OF node bindings of drivers that use phylink
in Linux, introduce parsing support for this property in U-Boot too.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:55 +02:00
Vladimir Oltean
9dcb810b88 net: tsec: add support for promiscuous mode
The Freescale TSEC can be a DSA master, and the ports of the attached
DSA switch can have different MAC addresses compared to the TSEC.
Nonetheless, the TSEC must receive the packets on behalf of those switch
ports. Therefore, implement the promiscuous mode method to allow DSA to
set this.

Note that the init_registers() function called from eth_ops :: start
overwrites this setting. There is no reason why the RCTRL register
should be zero-initialized, so just stop clearing it so that the setting
we applied in eth_ops :: set_promisc sticks.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:55 +02:00
Vladimir Oltean
4a4e52f05f net: phy: mscc: add support for VSC8502 in dual RGMII mode
The VSC8502 is a Microchip (formerly Microsemi, formerly Vitesse)
dual port, gigabit Ethernet copper PHY which supports the MII, GMII and
RGMII MAC-side interfaces.

Of these, I could only test RGMII, and my board needed RGMII delays to
be applied by software, so I am able to confirm that this patch handles
that properly.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:55 +02:00
Tudor Ambarus
7dc48b41f4 spi: atmel-quadspi: Fix QSPI_RD reg name on verbose debug
It was wrongly set to "MR", fix it.

Fixes: 52e2565bfb ("spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2021-11-23 09:36:29 +02:00
Tom Rini
454a97485a - pinctrl: Correct the driver GPIO declaration
- meson64_android: handle errors on boot and run fastboot on boot failure
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Merge tag 'u-boot-amlogic-20211119' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- pinctrl: Correct the driver GPIO declaration
- meson64_android: handle errors on boot and run fastboot on boot failure
2021-11-19 16:33:33 -05:00
Simon Glass
886d36efdb pinctrl: meson: Correct the driver GPIO declaration
This should use the provided U_BOOT_DRIVER() macro so that the driver gets
added to the appropriate linker list. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7c9dcfed50 ("pinctrl: meson: rework gx pmx function")
Reported-by: Tom Rini <trini@konsulko.com>
Tested-by: Tom Rini <trini@konsulko.com> on libretech-cc
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-19 18:15:26 +01:00
Tom Rini
f9bab982ae Revert "nvme: Enable FUA"
Unaddressed review comments.

This reverts commit b6bfb8971d.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-18 20:18:34 -05:00
Tom Rini
8e2a782af3 Revert "nvme: Fix error in nvme_setup_prps"
Dependent commit has unaddressed review comments.

This reverts commit c4eef59faa.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-18 20:18:22 -05:00
Aswath Govindraju
1ac3b72077 usb: cdns3: cdns3-ti: Add compatible for AM64 SoC
Add new compatible for AM64 SoC.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-11-17 17:09:47 -05:00
Aswath Govindraju
82c65587f6 phy: cadence: phy-cadence-torrent: Change the name of subnode searched
Search for "phy" in the subnode names, to syncup with kernel.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-11-17 17:09:47 -05:00
Jon Lin
c4eef59faa nvme: Fix error in nvme_setup_prps
Consulting to "NVM Express® Base Specification, revision 2.0".

If more PRP List pages are required, then the last entry of
the PRP List contains the Page Base Address of the next PRP
List page. The next PRP List page shall be memory page aligned.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
2021-11-17 17:09:47 -05:00
Jon Lin
b6bfb8971d nvme: Enable FUA
Most NVME devcies maintain data in internal cache for an uncertain
times, and u-boot has no method to force NVME to flush cache.
So this patch adds FUA to avoid data loss caused by power off after data
programming.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
2021-11-17 17:09:47 -05:00
Alistair Delva
4f2e228086 RFC: arm: pci: Add PCI cam support to PCI-E ecam driver
When booting U-Boot in crosvm, the virtual machine emulates a PCI cam
device, not the PCI-E 'ecam' device normally seen on e.g. QEMU. This
PCI device can be supported with only trivial changes to the ecam
driver.

Instead of adding a completely new driver which is identical besides the
initialization step, add support for the PCI version to the existing
driver.

Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Cc: Ram Muthiah <rammuthiah@google.com>
2021-11-17 17:09:47 -05:00
Chia-Wei Wang
89c36cca0b crypto: aspeed: Add AST2600 ACRY support
ACRY is designed to accelerate ECC/RSA digital signature
generation and verification.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Chia-Wei Wang
af6451187c clk: ast2600: Add RSACLK control for ACRY
Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine
of ASPEED AST2600 SoCs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Johnny Huang
9fcdd98e54 crypto: aspeed: Add AST2600 HACE support
Hash and Crypto Engine (HACE) is designed to accelerate the
throughput of hash data digest, and symmetric-key encryption.

Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-17 17:05:00 -05:00
Joel Stanley
4080714f5e clk: ast2600: Add YCLK control for HACE
Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Julien Masson
faf5d4d53d mmc: mtk-sd: implement waiting for DAT0 line state
With the recent changes on mmc driver, we saw that the boot is ~5 secs
longer compared to v2021.07 on mediatek platforms.

This regression is seen during mmc_init and caused by the following
patch [1].

Indeed since we did not support poll dat0, we fulfilled the condition
of [1] and a delay of 500 ms was added for every __mmc_switch call.

By adding the support of wait_dat0(), we now don't need to mdelay
during mmc_init anymore.

[1]: https://patchwork.ozlabs.org/project/uboot/patch/1629192034-64056-1-git-send-email-ye.li@nxp.com/

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-11-17 17:04:59 -05:00
Pali Rohár
a4bc38da27 pci: Add standard PCIe ECAM macros
Lot of PCIe controllers are using ECAM addressing. So add common ECAM
macros into U-Boot's pci.h header file which can be suitable for most
PCI controller drivers.

Replace custom ECAM address macros in every PCI controller driver by new
ECAM macros from U-Boot's pci.h header file.

Similar macros are defined also in Linux kernel. There is a small
difference between Linux and these new U-Boot macros.

U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate
arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers
encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is
different than Linux's PCI_SLOT() macro. So having device and function
numbers in separate arguments makes code more straightforward.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-17 17:04:58 -05:00
Mark Kettenis
b814e0007e pinctrl: Add Apple pinctrl driver
This driver supports both pin muxing and GPIO support for the
pin control logic found on Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-11-17 17:04:58 -05:00
Ryan Chen
46220bf017 aspeed: AST2600 Pinctrl Driver
This driver uses Pinctrl framework and is compatible with the Linux
driver for AST2600.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2021-11-17 17:04:58 -05:00
Mathew McBride
4a08dba019 drivers: tpm: atmel_twi: fix printf specifier compile warning
%d was being used as the specifier for size_t, leading to a
compiler warning

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:36 +02:00
Mathew McBride
fb30d99df8 drivers: tpm: atmel_twi: implement get_desc operation
Without get_desc, the tpm command will not provide a
description of the device in 'tpm device' or 'tpm info'.

Due to the characteristics of the Atmel TPM it isn't
possible to determine certain attributes (e.g open/close
status) without using the TPM stack (compare Infineon
and ST TPM drivers), so just print out the chip model
and udevice name as the identifier.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:33 +02:00
Mathew McBride
fdb4a5fcd7 drivers: tpm: atmel_twi: do not use an offset byte
This driver was broken due to an empty offset byte being prepended
at the start of every transmission.

The hardware does not mimic an EEPROM device with registers so
an offset byte is not required.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:31 +02:00
Mathew McBride
02f50d8ebb drivers: tpm: atmel_twi: drop non-DM_I2C compatibility
There are no users of this driver without DM_I2C

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:29 +02:00
Tom Rini
2ffa0e87df Xilinx changes for v2022.01-rc3
sdhci:
 - Fix emmc mini case with missing firmware interface
 
 zynqmp:
 - Restore JTAG interface if required
 - Allow overriding board name
 - Add support for DLC21
 - Fix one fallthrought statement description
 - Use config macro instead of name duplication
 - Save multiboot to variable
 
 firmware:
 - Handle ipi_req errors better
 - Use local buffer in case user doesn't need it instead of NULL/0 location
 
 spi:
 - gqsi: Fix write issue at low frequencies
 
 net:
 - gem: Disable broadcasts
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Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.01-rc3

sdhci:
- Fix emmc mini case with missing firmware interface

zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable

firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location

spi:
- gqsi: Fix write issue at low frequencies

net:
- gem: Disable broadcasts
2021-11-16 09:51:04 -05:00
Samuel Dionne-Riel
f4642e58e0 usb: Make USB_MUSB_PIO_ONLY selected by USB_MUSB_SUNXI
This ensures the USB_MUSB_PIO_ONLY config is set to an apppropriate
value from the changes enabling USB_MUSB_GADGET does.

Namely, USB_MUSB_PIO_ONLY default to =y on USB_MUSB_SUNXI being y.

Signed-off-by: Samuel Dionne-Riel <samuel@dionne-riel.com>
2021-11-15 11:17:39 -05:00
Tom Rini
e035ce4b3b env tidy-ups
test fixes
 binman fixes and ELF enhancements
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Merge tag 'dm-pull-13nov21' of https://source.denx.de/u-boot/custodians/u-boot-dm

env tidy-ups
test fixes
binman fixes and ELF enhancements
2021-11-13 21:14:51 -05:00
Tom Rini
b8a156f54e Pull request for efi-2022-01-rc2-2
UEFI:
 * fix measurement of BootOrder variable for TCG2 protocol
 
 TPM:
 * TIS mmio driver. This driver supports QEMU's emulated TPM.
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Merge tag 'efi-2022-01-rc2-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2022-01-rc2-2

UEFI:
* fix measurement of BootOrder variable for TCG2 protocol

TPM:
* TIS mmio driver. This driver supports QEMU's emulated TPM.
2021-11-13 18:13:35 -05:00
Heinrich Schuchardt
592e2e5929 sandbox: fix sandbox_wdt_expire_now()
With CONFIG_SYSRESET_WATCHDOG=y the sandbox can use a watchdog based system
reset.

To make this work calling sandbox_wdt_expire_now() must lead to a reset.

With this change we can test the development suggested in

  [PATCH 0/4] Improved sysreset/watchdog uclass integration
  https://lists.denx.de/pipermail/u-boot/2021-August/458656.html

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-13 08:16:52 -07:00
Tom Rini
b8475e6aca Convert CONFIG_MACB to Kconfig
This converts the following to Kconfig:
   CONFIG_MACB

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-12 14:18:17 -05:00
Clemens Gruber
6f84e809d9 rtc: ds1337: fix compatible string typo
The driver supports the ds1339 as well, which was probably intended by
the author but prevented by a typo. Fix the typo.

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2021-11-11 19:02:44 -05:00
Tom Rini
1e72ad6b38 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- device-tree sync-up with Linux for ls1028a
- fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc,
  spintable code, configs, qspi node, pci
- enable EFI_SET_TIME support in sl28
- powerpc: Drop -mstring
2021-11-11 09:04:20 -05:00
Ilias Apalodimas
a5c30c26b2 tpm: Use the new API on tpm2 spi driver
Convert our SPI TPM driver and use the newly added API

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10 20:57:54 +01:00
Ilias Apalodimas
e0ff348997 tpm2: Add a TPMv2 MMIO TIS driver
Add support for devices that expose a TPMv2 though MMIO.
Apart from those devices, we can use the driver in our QEMU setups and
test TPM related code which is difficult to achieve using the sandbox
driver (e.g test the EFI TCG2 protocol).

It's worth noting that a previous patch added TPMv2 TIS core functions,
which the current driver is consuming.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10 20:57:54 +01:00
Ilias Apalodimas
2c9626c463 tpm2: Introduce TIS tpm core
There's a lot of code duplication in U-Boot right now.  All the TPM TIS
compatible drivers we have at the moment have their own copy of a TIS
implementation.

So let's create a common layer which implements the core TIS functions.
Any driver added from now own, which is compatible with the TIS spec, will
only have to provide the underlying bus communication mechanisms.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10 20:57:54 +01:00
Ilias Apalodimas
c9e6d9c8e5 tpm: refactor function names for LPC based TPMs
With the upcoming TPM2 API, some of the functions name are part of the new
header file.  So switch conflicting internal function names and defines.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10 20:57:54 +01:00
Ilias Apalodimas
07b6b15bb2 tpm: refactor function names and macros for infineon v1.2 TPM
With the upcoming TPM2 API, some of the functions name are part of the new
header file.  So switch conflicting internal function names and defines.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10 20:57:54 +01:00
Tom Rini
166a77b34b - DHSOM update:
- Remove nWP GPIO hog
    - Increase SF bus frequency to 50Mhz and enable SFDP
    - Disable video output for DHSOM
    - Disable EFI
    - Enable DFU_MTD support
 - Create include file for STM32 gpio driver private data
 - Split board and SOC STM32MP15 configuration
 - Device tree alignement with v5.15-rc6 for STM32MP15
 - Add binman support for STM32MP15x
 - Normalise newlines for stm32prog
 - Update OTP shadow registers in SPL
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Merge tag 'u-boot-stm32-20211110' of https://source.denx.de/u-boot/custodians/u-boot-stm

- DHSOM update:
   - Remove nWP GPIO hog
   - Increase SF bus frequency to 50Mhz and enable SFDP
   - Disable video output for DHSOM
   - Disable EFI
   - Enable DFU_MTD support
- Create include file for STM32 gpio driver private data
- Split board and SOC STM32MP15 configuration
- Device tree alignement with v5.15-rc6 for STM32MP15
- Add binman support for STM32MP15x
- Normalise newlines for stm32prog
- Update OTP shadow registers in SPL
2021-11-10 14:11:30 -05:00
Patrick Delaunay
f42045b2e7 stm32mp15: replace CONFIG_TFABOOT when it is possible
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced
by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC.

This patch also simplifies the code in cpu.c, stm32mp1_ram.c and
clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and
without TFA) is not supported: the associated initialization code is
present only in SPL.

This cleanup patch is a preliminary step to support SPL load of OP-TEE
in secure world, with SPL in secure world and U-Boot in no-secure world.

Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10 17:07:31 +01:00
Patrick Delaunay
56a368f661 gpio: stm32: create include file for driver private data
The stm32 gpio driver private data are not needed in arch include files,
they are not used by code except for stm32 gpio and pincontrol drivers,
using the same IP; the defines for this IP is moved in a new file
"stm32_gpio_priv.h" in driver/gpio.

This patch avoids to have duplicated file gpio.h for each SOC
in MPU directory mach-stm32mp and in each MCU directory arch-stm32*
and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10 17:03:36 +01:00
Tom Rini
6354913def Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvell
- Minor kwboot improvements (Pali)
- Misc kwbimage improvements (Pali)
- pci_mvebu: Use global MBUS_PCI_MEM_SIZE macro (Pali)
2021-11-10 09:15:18 -05:00
Pali Rohár
cbf0d3a56d pci: pci_mvebu: Use global MBUS_PCI_MEM_SIZE macro
Header file mach/cpu.h already defines MBUS_PCI_MEM_SIZE macro which
defines size of MBUS_PCI_MEM_BASE window. So use global MBUS_PCI_MEM_SIZE
macro instead of locally defined PCIE_MEM_SIZE macro. Both macros have same
definition.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-10 12:08:06 +01:00
Heinrich Schuchardt
86798ee0c1 watchdog: don't autostart watchdog on Sunxi boards
The Sunxi boards only support a 16 second watchdog timeout. This is too
short to boot Linux. The UEFI specification requires 300 seconds as
default timeout.

Change the default for CONFIG_WATCHDOG_AUTOSTART for ARCH_SUNXI.

Fixes: b147bd3607 ("sunxi: Enable watchdog timer support by default")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-11-10 01:38:07 +00:00
Hou Zhiqiang
be38416034 pci: layerscape: Fix the LUT and msi-map mismatch issue
In the current code, it doesn't reset the cursors of LUT entry and
StreamID at the beginning of the fixup, so it can result in LUT entry
setup and msi-map mismatch and LUT entries and StreamID leaking
when reload and fixup the DTB.
This patch move the initialization of LUT entry and StreamID cursors
to the beginning of the fixup to resolve the issues.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Rajesh Bhagat
a97a071d10 configs: fsl: migrate FMAN/QE specific defines to Kconfig
Use moveconfig.py script to convert CONFIG_SYS_FMAN_FW_ADDR,
CONFIG_SYS_QE_FW_ADDR and CONFIG_SYS_QE_FMAN_FW_LENGTH to Kconfig and
move these entries to defconfigs.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
2b0b51d0be usb: dwc3: add layerscape support
Add support for the proper dwc3 device tree binding support as specified
in the offical device tree spec.

Initially, add support for the LS1028A support. Other SoCs should be
easy to add by just adding the corresponding compatible string.
Unfortunately, the device trees of all other layerscape SoCs are not
converted and uses a wrong compatible string only known in u-boot.

To maintain backwards compatibility with current u-boot device trees,
add the generic "fsl,layerscape-dwc3" compatible string.

OTG mode is not supported yet. The dr_mode in the devicetree will either
have to be set to peripheral or host.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
f150b8d28b usb: dwc3: Enable undefined length INCR burst type
[backport from linux commit d9612c2f0449e24983a8b689603210486a930c90]

Enable the undefined length INCR burst type and set INCRx.
Different platform may has the different burst size type.
In order to get best performance, we need to tune the burst
size to one special value, instead of the default value.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
d274cbbc1c usb: dwc3: Add frame length adjustment quirk
[backport from linux commit db2be4e9e30c6e43e48c5749d3fc74cee0a6bbb3]

Add adjust_frame_length_quirk for writing to fladj register
which adjusts (micro)frame length to value provided by
"snps,quirk-frame-length-adjustment" property thus avoiding
USB 2.0 devices to time-out over a longer run

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
7f79a2c235 usb: common: silence dubious errors
Both dr_mode and maximum-speed properties are usually optional. Drivers
will still try to fetch the properties nonetheless, which leads to error
messages, although they are no errors. Change pr_err() to pr_debug().

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
e10da1f985 pci: layerscape: add official ls1028a binding support
The official bindind of the PCIe controller of the ls1028a has the
following compatible string:
  compatible = "fsl,ls1028a-pcie";

Additionally, the resource names and count are different. Update the
driver to support this binding and change the entry in the ls1028a
device tree.

Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
8f176eb8ac usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3
The official ls1028a binding of the driver uses the following as
compatibles:
  compatible = "fsl,ls1028a-dwc3", "snps,dwc3";

Change the ls1028a device tree and add this new compatible to the fsl
specific xhci driver, otherwise the generic dwc3 driver will be used
with the compatibles above.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
cde9b147ba scsi: ceva: rename the resource name to match the linux kernel one
The driver will look for a named resource "ecc-addr", but this isn't the
official binding. In fact, the official device tree binding
documentation doesn't mention any resource names at all. But it is safe
to assume that it's the linux ones we have to use if we want to be
compatible with the linux device tree. Thus rename "ecc-addr" to
"sata-ecc" and convert all the users in u-boot.

While at it, also rename "sata-base" to "ahci" although its not used at
all.

This change doesn't affect the SATA controller on the ZynqMP.

Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
c9bf9af9a7 serial: lpuart: add new compatible fsl, ls1028a-lpuart
The official ls1028a binding of the driver uses the following as
compatibles:
  compatible = "fsl,ls1028a-lpuart";

Add the missing compatible to the driver and update the device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
8c58089287 spi: fsl_dspi: rename num-cs to spi-num-chipselects
The official devicetree bindings specifies spi-num-chipselects as the
name. Use it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
765afe7fb3 spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspi
The official ls1028a binding of the driver uses the following as
compatibles:
  compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";

Add the missing compatible to the driver and update the device tree.
We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness
is determined by the little-endian property and not by the compatible
string itself. Further, we won't need and specific details on the DMA
configuration (which is different on the LS1021A). If it's ever needed,
we can later add the more specific "fsl,ls1028a-dspi" compatible to the
driver.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
5709a858c0 watchdog: sp805_wdt: use correct compatible string
According to the linux device tree specification the compatible string
is:
  compatible = "arm,sp805", "arm,primecell";

Fix all users in u-boot.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Maninder Singh
38ce95a1c6 drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issue
Adds check for memory clock variable before calculating caslat_actual.

Set mclk_ps to slowest DIMM supported if mclk_ps is found zero.

Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Cosmin-Florin Aluchenesei
ed06772a60 drivers: net: fsl-mc: add a command which dumps the MC log
Extended fsl_mc command adding an extra option dump_log

Signed-off-by: Cosmin-Florin Aluchenesei <aluchenesei.cosmin-florin@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:06 +05:30
Kshitiz Varshney
bd2a4eb977 board: fsl_validate: Fix Double free Issue
Remove Double free issue from calc_img_key_hash() and
calc_esbchdr_esbc_hash() function.
Verified the secure boot changes using lx2162aqds board.

Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:43:24 +05:30
Priyanka Singh
71b255b657 drivers: ddr: main.c: Fix Bad Shift operator issue
Fix Bad Shift operator issue in step_to_string function
by adding an if check

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:43:24 +05:30
Priyanka Singh
f5a37b02b0 drivers: ddr: fsl_ddr_gen4.c: Fix divide by zero issue
Fix possible divide by zero issue in fsl_ddr_set_memctl_regs
by adding an if check

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:43:24 +05:30
Priyanka Singh
a1932ece70 drivers: ddr: util.c: Fix divide by zero issue
Fix possible divide by zero issue in get_memory_clk_period_ps
by adding a check

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:43:24 +05:30
Minkyu Kang
2b77d9a3ee exynos78x0: pinctrl: set const to structs
to fix following checkpatch warings.
WARNING: struct  should normally be const

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-11-09 14:07:46 +09:00
Simon Glass
dfb8470fd0 exynos: pwm: Deal with a PWM at 100%
At present the counter never hits the comparitor in this case. Add a
special case.

This ensures that the snow backlight works when at full brightness.

Fixes: 76c2ff3e5f video: backlight: fix pwm's duty cycle calculation

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2021-11-09 11:57:22 +09:00
Heinrich Schuchardt
f8d7e6e941 dfu: newline after updating
Currently output of dfu commands ends on a line with leading hash signs
('#'). The succeeding output should be placed on a new line.

After writing updates via dfu print a new line.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-11-07 18:36:56 +01:00
Simon Glass
1834c081d3 efi: Add video support to the app
The current EFI video driver only works when running in the stub. In that
case the stub calls boot services (before jumping to U-Boot proper) and
copies the graphics info over to the efi table. This is necessary because
the stub exits boot services before jumping to U-Boot.

The app maintains access to boot services throughout its life, so does not
need to do this. Update the driver to support calling boot services
directly.

Enable video output for the app. Note that this uses the
EFI_GRAPHICS_OUTPUT_PROTOCOL protocol, even though it mentions vesa.

A sample qemu command-line for this case is:

   qemu-system-x86_64 -bios /usr/share/edk2.git/ovmf-ia32/OVMF-pure-efi.fd
   -drive id=disk,file=try.img,if=none,format=raw -nic none
   -device ahci,id=ahci -device ide-hd,drive=disk,bus=ahci.0

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-07 18:36:55 +01:00
Tom Rini
1616626417 Convert CONFIG_SPL_DRIVERS_MISC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_DRIVERS_MISC
   CONFIG_SPL_ENV_SUPPORT
   CONFIG_SPL_GPIO
   CONFIG_SPL_I2C
   CONFIG_SPL_LDSCRIPT
   CONFIG_SPL_LIBCOMMON_SUPPORT
   CONFIG_SPL_LIBGENERIC_SUPPORT
   CONFIG_SPL_LOAD_FIT_ADDRESS
   CONFIG_SPL_MMC
   CONFIG_SPL_NAND_SUPPORT
   CONFIG_SPL_NO_CPU_SUPPORT
   CONFIG_SPL_OS_BOOT
   CONFIG_SPL_POWER
   CONFIG_SPL_STACK_R
   CONFIG_SPL_STACK_R_ADDR
   CONFIG_SPL_WATCHDOG
   CONFIG_SPL_TEXT_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-05 11:26:29 -04:00
Samuel Holland
a8f63d18bb watchdog: Automatically register device with sysreset
Add an option to automatically register watchdog devices with the
wdt_reboot driver for use with sysreset. This allows sysreset to be a
drop-in replacement for platform-specific watchdog reset code, without
needing any device tree changes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-04 08:57:19 +01:00
Samuel Holland
5544a01142 sysreset: watchdog: Move watchdog reference to plat data
Currently, the wdt_reboot driver always gets its watchdog device
reference from an OF node. This prevents selecting a watchdog at
runtime. Move the watchdog device reference to the plat data, so
the driver can be bound with the reference pre-provided. The
reference will still be acquired from the OF node if it is not
already provided.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-04 08:57:19 +01:00
Samuel Holland
30ba45dbd6 sysreset: Mark driver probe functions as static
These driver probe functions are not (and should not be) called from
outside the respective driver source files. Therefore, the functions
should be marked static.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-04 08:57:19 +01:00
Samuel Holland
6b84217227 sysreset: Add uclass Kconfig dependency to drivers
None of the sysreset drivers do anything beyond providing sysreset
uclass ops. They should depend on the sysreset uclass.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-04 08:57:19 +01:00
Tom Rini
bc18582a14 Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- usb: mtu3: flush cache for the first GPD when allocate GPD ring
2021-11-03 09:42:45 -04:00
Chunfeng Yun
2c4f21763d usb: mtu3: flush cache for the first GPD when allocate GPD ring
When allocate the GPD ring, and tell its address to the controller, then
the driver starts or resumes the QMU, the controller will try to access
the first GPD, so need flush the first one to avoid wrong GPD status.

Reported-by: Xin Lin <Xin.Lin@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2021-11-03 08:47:57 +01:00
Pali Rohár
57fa6fb932 arm: a37xx: pci: Program the data strobe for config read requests
According to the Armada 3720 Functional Specification Data Strobe applies
for both read and write config requests.

Data strobe bits configure which bytes from the start address should be
returned for read request. Set value 0xf (all 4 bits) into Data Strobe
register to read all four bytes from specified 32-bit config space
register. Same value for Data Strobe register is programmed by Linux
pci-aardvark.c driver for config read requests.

Without this patch pci-aardvark driver sets data strobe register only
during config write operations. So any followup config read operations
could result with just partial datai returned (if previous write operation
was not 32-bit wide). This patch fixes it and ensures that config read
operations always read all bytes from requested register.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03 06:45:34 +01:00
Pali Rohár
03a8a5e26a pci: pci_mvebu: Fix comment about driver class name
This is a pci driver, not an eth driver.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03 06:45:26 +01:00
Pali Rohár
2344a76f29 pci: pci_mvebu: Setup PCI controller to Root Complex mode
Root Complex should be the default mode, let's set it explicitly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03 06:45:26 +01:00
Pali Rohár
42ab3b3004 pci: pci_mvebu: Do not automatically enable bus mastering on PCI Bridge
Now that PCI Bridge is working, U-Boot's CONFIG_PCI_PNP code automatically
enables memory access and bus mastering when it is needed. So do not
prematurely enable memory access and bus mastering.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03 06:45:26 +01:00
Pali Rohár
79b4eb21b4 pci: pci_mvebu: Fix place of link up detection
PCI Bridge is always accessible also when link is down. So move detection
of link up from mvebu_pcie_of_to_plat() function to mvebu_pcie_valid_addr()
function which is used when accessing PCI config space.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03 06:45:26 +01:00
Pali Rohár
452f2e73c6 pci: pci_mvebu: Remove unused functions
Functions mvebu_pcie_get_local_bus_nr() and mvebu_pcie_get_local_dev_nr()
are not used, so remove them.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03 06:45:26 +01:00
Pali Rohár
a7b61ab58d pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)
The mysterious "Memory controller" PCI device which is present in PCI
config space is improperly configured and crippled PCI Bridge which acts
as PCIe Root Port for endpoint PCIe card.

This PCI Bridge reports in PCI config space incorrect Class Code (Memory
Controller) and incorrect Header Type (Type 0). It looks like HW bug in
mvebu PCIe controller but apparently it can be changed via mvebu registers
to correct values.

The worst thing is that this PCI Bridge is crippled and its PCI config
registers in range 0x10-0x34 alias access to internal mvebu registers which
have different functionality as PCI Bridge registers. Moreover,
configuration of PCI primary and secondary bus numbers (registers 0x18
and 0x19) is done via totally different mvebu registers via totally strange
method and cannot be done via PCI Bridge config space.

Due to above fact about PCI config range 0x10-0x34, allocate a private
cfgcache[] buffer in the driver, to which PCI config access requests to
the 0x10-0x34 space will be redirected in mvebu_pcie_read_config() and
mvebu_pcie_write_config() functions. Function mvebu_pcie_write_config()
will also catch writes to PCI_PRIMARY_BUS (0x18) and PCI_SECONDARY_BUS
(0x19) registers and set PCI Bridge primary and secondary bus numbers via
mvebu's own method.

Also, Expansion ROM Base Address register (0x38) is available, but at
different offset 0x30. So recalculate register offset before accessing PCI
config space.

After these steps U-Boot sees working PCI Bridge and CONFIG_PCI_PNP code
can finally start enumerating all PCIe devices correctly, even with more
complicated PCI topology. So update also mvebu_pcie_valid_addr() function
to reflect state of the real device topology.

Each PCIe port is de-facto isolated and every PCI Bridge which is part of
PCIe Root Complex is also isolated, so put them on separate PCI buses as
(local) device 0.

U-Boot already supports enumerating separate PCI buses, real (HW) bus
number can be retrieved by "PCI_BUS(bdf) - dev_seq(bus)" code, so update
config read/write functions to properly handle more complicated tree
topologies (e.g. when a PCIe switch with multiple PCI buses is connected
to the PCIe port).

Local bus number and local device number on mvebu are used for determining
which config request type is used (Type 0 vs Type 1). On normal non-broken
PCIe hardware it is done by primary and secondary bus numbers. So correctly
translate settings between these numbers to ensure that correct config
requests are sent over the PCIe bus.

As bus numbers are correctly re-configured, it does not make sense to print
some initial bogus configuration during probe, so remove this debug code.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03 06:45:26 +01:00
Pali Rohár
657177ad8e pci: pci_mvebu: Fix read_config() with PCI_SIZE_8 or PCI_SIZE_16
When reading 8 or 16 bits from config space, use appropriate readb() or
readw() calls. This ensures that PCIe controller does not read more bits
from endpoint card as asked by read_config() function.

Technically there should not be an issue with reading data from config
space which are not later used as there are no clear-by-read registers.
But it is better to use correct read operation based on requested size.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03 06:45:26 +01:00
Pali Rohár
daa9bfdb9c pci: pci_mvebu: Fix write_config() with PCI_SIZE_8 or PCI_SIZE_16
Current implementation of write_config() is broken for PCI_SIZE_8 or
PCI_SIZE_16 as it always uses writel(), which means that write operation
is always 32-bit, so upper 24 bits for PCI_SIZE_8 and upper 16 bits for
PCI_SIZE_16 are cleared.

Fix this by using writeb() and writew(), respectively.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-03 06:45:26 +01:00
Tom Rini
77680d8f85 Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- usb_mass_storage, xhci-brcm bugfixes
2021-10-31 12:48:08 -04:00
Dzmitry Sankouski
69bde0410a SoC: exynos: add support for exynos 78x0
Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets
introduced on March 2017.
Features:
- 8 Cortex A53 cores
- ARM Mali-T830 MP3 GPU
- LTE Cat. 7 (7880) or 6 (7870) modem

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31 11:25:39 -04:00
Dzmitry Sankouski
d8428f73c3 pinctrl: exynos: add support for multiple pin banks
Iterate all pin banks to find a pin

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31 11:25:39 -04:00
Dzmitry Sankouski
85fcf94160 serial: samsung: add support for skip debug init in s5p
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31 11:25:39 -04:00
Dzmitry Sankouski
7964c30541 pinctrl: qcom: add pinctrl and gpio drivers for SDM845 SoC
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephan Gerhold <stephan@gerhold.net>
[trini: Add CONFIG_SDM845 around sdm845_data usage]
2021-10-31 08:46:44 -04:00
Dzmitry Sankouski
f5a2d6b4b0 spmi: msm: add arbiter version 5 support
Currently driver supports only version 1 and 2.
Version 5 has slightly different registers structure

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-10-31 08:46:44 -04:00
Dzmitry Sankouski
324df15a29 serial: qcom: add support for GENI serial driver
Generic Interface (GENI) Serial Engine (SE) based uart
can be found on newer qualcomm SOCs, starting from SDM845.
Tested on Samsung SM-G9600(starqltechn)
by chain-loading u-boot with stock bootloader.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-10-31 08:46:44 -04:00
Mark Kettenis
785cfde5b3 iommu: Add Apple DART driver
The DART is an IOMMU that is used on Apple's M1 SoC.  This driver
configures the DART such that it operates in bypass mode which is
enough to support DMA for the USB3 ports integrated on the SoC.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 08:46:44 -04:00
Mark Kettenis
d520e1fb72 serial: s5p: Add Apple M1 support
Apple M1 SoCs include an S5L UART which is a variant of the S5P
UART.  Add support for this variant and enable it by default
on Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 08:46:44 -04:00
Mark Kettenis
fb57462437 test: Add tests for IOMMU uclass
Add a set of tests for the IOMMU uclass.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 08:46:44 -04:00
Mark Kettenis
40dbf03d7d iommu: Add IOMMU uclass
This uclass is intended to manage IOMMUs on systems where the
IOMMUs are not in bypass mode by default.  In that case U-Boot
cannot ignore the IOMMUs if it wants to use devices that need
to do DMA and sit behind such an IOMMU.

This initial IOMMU uclass implementation does not implement and
device ops and is intended for IOMMUs that have a bypass mode
that does not require address translation.  Support for IOMMUs
that do require address translation is planned and device ops
will be defined when support for such IOMMUs will be added.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 08:46:44 -04:00
Stefan Agner
617e851e3a usb: xhci-brcm: Include header file needed for dev_err
dev_err seems to be moved to different header file. Include
dm/device_compat.h file to compile properly.

Fixes: 69dae8902b ("linux/compat.h: Remove redefinition of dev_xxx macros")
Signed-off-by: Stefan Agner <stefan@agner.ch>
2021-10-30 22:54:57 +02:00
Usama Arif
c95b0297e9 mmc: arm_pl180_mmci: Enable HWFC for specific versions of MCI
There are 4 registers (PERIPHID{0-3}) that contain the ID of MCI.
For MMCs' with peripheral id 0x02041180 and 0x03041180, H/W flow control
needs to be enabled for multi block writes (MMC CMD 18).

Signed-off-by: Usama Arif <usama.arif@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29 18:22:32 +09:00
Kirill Kapranov
44645f87de mmc: Fix mmc_switch excessive timeout
Fix branching to avoid premature falling back on a long timeout instead
of continuation of the initialization attempt.

Clear of the comment to avoid the ambiguity.

Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Ye Li <ye.li@nxp.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29 18:22:32 +09:00
Stephen Carlson
40e6f52454 drivers: mmc: Add wait_dat0 support for sdhci driver
Adds an implementation of the wait_dat0 MMC operation for the DM SDHCI
driver, allowing the driver to continue when the card is ready rather
than waiting for the worst case time on each MMC switch operation.

Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29 18:22:32 +09:00
Stephen Carlson
ee02543561 drivers: mmc: Add wait_dat0 support for Freescale eSDHC driver
Adds an implementation of the wait_dat0 MMC operation for the Freescale
eSHDC driver, allowing the driver to continue when the card is ready
rather than waiting for the worst case time on each MMC switch operation.

Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29 18:22:32 +09:00
Marek Vasut
73d18e352d dfu: Sort Kconfig entries alphabetically
The DFU_MTD Kconfig entry is in the wrong position, move it into the
correct alphabetically sorted position. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-10-26 15:26:45 -04:00