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drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issue

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Adds check for memory clock variable before calculating caslat_actual.

Set mclk_ps to slowest DIMM supported if mclk_ps is found zero.

Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Maninder Singh 2021-10-10 09:12:16 -07:00 committed by Priyanka Jain
parent ed06772a60
commit 38ce95a1c6
1 changed files with 8 additions and 2 deletions
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10
drivers/ddr/fsl/lc_common_dimm_params.c
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@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008-2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP Semiconductor
* Copyright 2017-2021 NXP Semiconductor
*/
#include <common.h>
@ -23,7 +23,7 @@ compute_cas_latency(const unsigned int ctrl_num,
unsigned int caslat_actual;
unsigned int retry = 16;
unsigned int tmp = ~0;
const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#ifdef CONFIG_SYS_FSL_DDR3
const unsigned int taamax = 20000;
#else
@ -37,6 +37,12 @@ compute_cas_latency(const unsigned int ctrl_num,
}
common_caslat = tmp;
if (!mclk_ps) {
printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n",
outpdimm->tckmin_x_ps);
mclk_ps = outpdimm->tckmin_x_ps;
}
/* validate if the memory clk is in the range of dimms */
if (mclk_ps < outpdimm->tckmin_x_ps) {
printf("DDR clock (MCLK cycle %u ps) is faster than "