Commit graph

891 commits

Author SHA1 Message Date
Lei Wen
a03774ed88 mvmfp: add MFP configuration support for PANTHEON
This patch adds the Multiple Function Pin configuration support for
Marvell PANTHEON SoCs

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-02-21 08:30:55 +01:00
Lei Wen
896e2ca912 ARM: Add Support for Marvell Pantheon Familiy SoCs
Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf

SoC versions Supported:
1) PANTHEON920          (TD)
2) PANTHEON910          (TTC)

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-02-21 08:30:55 +01:00
Lei Wen
cf946c6d09 mv: seperate kirkwood and armada from common setting
Since there are lots of difference between kirkwood and armada series,
it is better to seperate them but still keep the most common file
shared by all marvell platform in the mv-common configure file.

This patch move the kirkwood only driver definitoin in mv-common to
the <soc_name>/config.h.

This patch is tested with compilation for armada100 and guruplug.

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-02-21 08:30:55 +01:00
Wolfgang Denk
495df3bad9 ARM: fix write*() I/O accessors
Commit 3c0659b "ARM: Avoid compiler optimization for readb, writeb
and friends." introduced I/O accessors with memory barriers.
Unfortunately the new write*() accessors introduced a bug:

The problem is that the argument "v" gets evaluated twice.  This
breaks code like used here (from "drivers/net/dnet.c"):

	for (i = 0; i < wrsz; i++)
		writel(*bufp++, &dnet->regs->TX_DATA_FIFO);

Use auxiliary variables to avoid such problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Alexander Holler <holler@ahsoftware.de>
Cc: Dirk Behme <dirk.behme@googlemail.com>
2011-02-21 08:30:55 +01:00
Alexander Stein
6087f1a90c arm relocation: Fix calculation of board_init_r
Signed-off-by: Alexander Stein <alexander.stein@informatik.tu-chemnitz.de>
2011-02-21 08:30:55 +01:00
Tom Warren
3f82b1d3ab arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-02-21 08:30:54 +01:00
Michal Simek
518075fc6a microblaze: Fix msr handling in interrupt_handler
Fix ancient code which worked with MSR in a bad way.
Use rtid instruction which enable IRQs and jump.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-02-15 15:13:24 +01:00
Michal Simek
b777a37c29 microblaze: Fix systems with MSR=0
u-boot BSP generates XILINX_USE_MSR_INSTR macro
even for system with MSR=0. That's why explicitly
check that MSR=1.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-02-15 15:13:24 +01:00
Graeme Russ
6002bf03b4 sc520: Release CAR and enable caching 2011-02-12 15:12:12 +11:00
Graeme Russ
e4f78d78d7 x86: Convert board_init_f to use an init_sequence 2011-02-12 15:12:10 +11:00
Graeme Russ
a3824142e7 x86: Rearrange function calls in board_init_f 2011-02-12 15:12:08 +11:00
Graeme Russ
71a5404974 x86: Split board_init_f() into init_fnc_t compatible functions 2011-02-12 15:12:06 +11:00
Graeme Russ
5fed82110d x86: Fix incorrect usage of relocation offset
x86 has always used relocation offset in the opposite sense to the ELF
standard - Fix this
2011-02-12 15:12:05 +11:00
Graeme Russ
0b2378557c x86: Move console initialisation into board_init_f 2011-02-12 15:12:03 +11:00
Graeme Russ
bf6af154a4 x86: Move test for cold boot into init functions 2011-02-12 15:12:01 +11:00
Graeme Russ
c869e2ac46 x86: Move call to dram_init_f into board_init_f 2011-02-12 15:11:59 +11:00
Graeme Russ
fb0029088e x86: Defer setup of final stack 2011-02-12 15:11:58 +11:00
Graeme Russ
96cd66426a sc520: Move RAM sizing code from asm to C 2011-02-12 15:11:54 +11:00
Graeme Russ
ed4cba79d6 x86: Use Cache-As-RAM for initial stack 2011-02-12 15:11:52 +11:00
Graeme Russ
2e2613d2c4 x86: Move initial gd to fixed location 2011-02-12 15:11:50 +11:00
Graeme Russ
6d0cb34954 sc520: Remove printf calls from cpu_init_f
In later patches, cpu_init_f will be called before console has been
initialised and printf will not be legitimately available
2011-02-12 15:11:40 +11:00
Graeme Russ
870847f5c5 sc520: Move board specific settings to board init function 2011-02-12 15:11:38 +11:00
Graeme Russ
c2cbbaf0b4 sc520: Define MMCR address in include file 2011-02-12 15:11:36 +11:00
Graeme Russ
0ea76e92e9 x86: Make cpu init functions weak 2011-02-12 15:11:35 +11:00
Graeme Russ
4e33467d44 x86: Call early_board_init when warm booting
early_board_init has been skipped to avoid SDRAM corruption in the case
that a fully relocatable image has been loaded into SDRAM and is being
executed from SDRAM. x86 is being aligned with other architectures (ARM
and PPC in particlar) and will be using Cache-As-RAM to run a C
environment from Flash (or SRAM if you have some). early_board_init may
be needed to assist in the setup of Cache-As-RAM and the early C
environment
2011-02-12 15:11:33 +11:00
Graeme Russ
0c24c9cc71 x86: Add processor flags header from linux 2011-02-12 15:11:32 +11:00
Graeme Russ
c53fd2bb6d x86: Move Global Descriptor Table defines to processor.h 2011-02-12 15:11:30 +11:00
Graeme Russ
ca56a4ceec x86: Add stack dump to register dump 2011-02-12 15:11:28 +11:00
Graeme Russ
9963a8216e x86: Fix mangled umlauts
git mergetool has a nasty habit of mangling umlats - fix ones that have
been missed in previous submissions
2011-02-12 15:11:26 +11:00
Graeme Russ
0640e40272 sc520: Sort Makefile 2011-02-12 15:11:25 +11:00
Graeme Russ
3a25e94410 x86: Parametize values used in linker script 2011-02-12 15:11:24 +11:00
Graeme Russ
a85f53cd3f x86: Align config.mk and linker scripts with other arches 2011-02-12 15:11:21 +11:00
Graeme Russ
de47cbe686 x86: Fix definition of global_data struct for asm-offsets.c 2011-02-12 15:11:21 +11:00
York Sun
856e4b0d7f powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3
When DDR data rate is higher than 1200MT/s or controller interleaving is
enabled, additional cycle for write-to-read turnaround is needed to satisfy
dynamic ODT timing.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-10 23:40:02 -06:00
Wolfgang Denk
65b57ebb30 Merge branch 'next' of git://git.denx.de/u-boot-nios 2011-02-09 20:54:53 +01:00
Wolfgang Denk
fced09ae38 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2011-02-09 20:50:26 +01:00
Thomas Chou
d8a593c68b nios2: add gpio_is_valid
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2011-02-08 08:29:53 -05:00
Thomas Chou
85debefaf2 nios2: use long for ssize_t
This is consistent with nios2-linux. And resolved the warning,

cmd_nvedit.c: In function `do_env_export':
cmd_nvedit.c:660: warning: size_t format, ssize_t arg (arg 3)

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2011-02-08 08:29:53 -05:00
Thomas Chou
e91d54535f nios2: add gpio_free
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2011-02-08 08:29:53 -05:00
Dirk Eibach
2da0fc0d0f ppc4xx: Add DLVision-10G board support
Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2011-02-07 11:13:16 +01:00
Wolfgang Denk
8d4addc3c3 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2011-02-06 22:41:53 +01:00
Wolfgang Denk
e9e481f74b Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2011-02-06 22:28:34 +01:00
Joakim Tjernlund
26e5f794d3 mpc83xx: Use correct register to calculate clocks.
Use SPMR instead of HRCWL when calculating clocks as HCRWL
may be changed and the CPU will not pick up all changes
until there is a POR. u-boot will think SPMF has changed and get
the clocks wrong.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-02-05 17:06:57 -06:00
Leo Liu
10fa8d7c70 mpc83xx: fix pcie configuration space read/write
This patch fix a problem for the pcie enumeration when the mpc83xx
pcie controller is connected with switch or we use both of the two
pcie controller.

Signed-off-by: Leo Liu <liucai.lfn@gmail.com>

fix codingstyle and compiler warning: 'pcie_priv' defined but not used

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-02-05 17:01:52 -06:00
Kumar Gala
04a641df25 powerpc/8xxx: Fix possible compile issue related to P1013
The P1013 is a single core version of P1022 and thus should use the
p1022_serdes.c code.  It was acciently pointing to p1013_serdes.c which
doesn't exist.

Reported-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-04 14:04:21 -06:00
Wolfgang Denk
4bfa18fb99 Merge branch 'master' of git://git.denx.de/u-boot-sh 2011-02-04 20:38:27 +01:00
York Sun
91671913f7 powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134
Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET
DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
         calibrate to incorrect values

These two workarounds must be implemented together because they touch
common registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:13 -06:00
York Sun
eb0aff77c8 powerpc/85xx: Rename MPC8572 DDR erratum to DDR115
Use unique erratum number instead of platform number.
Enable command that reports errata on MPC8572DS.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:13 -06:00
York Sun
e1df0de493 powerpc/85xx: Remove unnecessary polling loop from DDR init
This polling loop is not required normally, unless specifically stated in
workaround.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:12 -06:00
Kumar Gala
5103a03a0b fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)
Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:12 -06:00
Kumar Gala
6e7f0bc0ce powerpc/85xx: Enable ESDHC111 Erratum on P2010/P2020 SoCs
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:12 -06:00
Wolfgang Denk
d1a24f0618 Minor Coding Style Cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-02-02 22:36:10 +01:00
Yoshihiro Shimoda
8e9c897b21 sh: add support for sh7757lcr board
The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM,
Ethernet, and more.

This patch supports the following functions:
 - 256MB DDR3-SDRAM
 - SPI ROM
 - Ethernet

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-02-02 16:38:41 +09:00
Yoshihiro Shimoda
36781e4897 sh: add support the CONFIG_SYS_LDSCRIPT
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-02-02 16:38:41 +09:00
Minkyu Kang
008a351a8a armv7: add support for S5PC210 SoC
S5PC210 is a 32-bit RISC and Cortex-A9 Dual Core based micro-processor.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-02-02 00:54:45 +01:00
Minkyu Kang
e0617c621d S5P: serial: Use the inline function instead of static value
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-02-02 00:54:45 +01:00
Heiko Schocher
c9ac3ba129 arm926ejs: timer: Replace bss variable by gdr
Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss
values in the arm926ejs timers implementation.

The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets corrupted.

This patch is similiar to the patch Dirk Behme posted
for the armv7/omap-common/timer.c and added suggestions
from Reinhard Meyer.

Tested on the arm926ejs mx27 based magnesium board
Tested on the arm926ejs kirkwood based suen3 board

Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Albert ARIBAUD <albert.aribaud@free.fr>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Stefano Babic <sbabic@denx.de>
cc: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-02-02 00:54:45 +01:00
Jens Scharsig
009b54079e remove (double) LED initialization in arm920t start.s
* remove LED initialization in front of relocation and bss init

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2011-02-02 00:54:45 +01:00
Heiko Schocher
c44bf4e8ac arm1136: timer: Replace bss variable by gd
Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss
values in the arm1136 timer driver for mx31 and omap24xx

The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets corrupted.

This patch is similiar to the patch Dirk Behme posted
for the armv7/omap-common/timer.c

Tested on the mx31 based qong board

Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Albert ARIBAUD <albert.aribaud@free.fr>
Acked-by: Albert ARIBAUD <albert.aribaud@free.fr>
2011-02-02 00:54:44 +01:00
Liu Hui-R64343
386ad72637 ARM: */start.S: code cleanup
Remove the useless code from start.S

Signed-off-by: Jason Liu <r64343@freescale.com>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-02-02 00:54:44 +01:00
Alexander Holler
3c0659b535 ARM: Avoid compiler optimization for readb, writeb and friends.
gcc 4.5.1 seems to ignore (at least some) volatile definitions,
avoid that as done in the kernel.

Reading C99 6.7.3 8 and the comment 114) there, I think it is a bug of that
gcc version to ignore the volatile type qualifier used e.g. in __arch_getl().
Anyway, using a definition as in the kernel headers avoids such optimizations when
gcc 4.5.1 is used.

Maybe the headers as used in the current linux-kernel should be used,
but to avoid large changes, I've just added a small change to the current headers.

Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Alessandro Rubini <rubini-list@gnudd.com>
Tested-by: Thomas Weber <weber@corscience.de>
Acked-by: Alexander Holler <holler@ahsoftware.de>
Tested-by: Alexander Holler <holler@ahsoftware.de>
2011-02-02 00:54:44 +01:00
Minkyu Kang
3c152165c7 armv7: s5pc1xx: don't use function pointer for clock functions
Because of the bss area is cleared after relocation, we've lost pointers.
This patch fixed it.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-02-02 00:54:44 +01:00
Sandeep Paulraj
724bd3c50f DaVinci: Remove incorrect CONFIG option
The option CONFIG_SOC_DM6447 seems to have ended up
in the code by mistake. It is not used anywhere and
there is no chip called DM6447.


Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-02-02 00:54:44 +01:00
Sandeep Paulraj
5342a710c9 DaVinci DM6467: Fix Build Error
This commit fixes build errors on the DM6467 port.


Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-02-02 00:54:44 +01:00
Sandeep Paulraj
b157dd51de DaVinci DM6467: Enhance board Support
Support for DM6467 was incomplete and the build failed
as well. Patches were sent to the list but have not been
added. This enhances the DM6467 support.
Some more patches will need to be sent to bring
it in line with what is available in internal TI
trees


Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-02-02 00:54:44 +01:00
Sandeep Paulraj
04f15b3b1a ARM: Update mach types
This commit updates the mach-types for ARM


Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-02-02 00:54:44 +01:00
Sandeep Paulraj
840f8923a0 DaVinci DM6467: Added ET1011C (LSI) PHY support
Added arch/arm/cpu/arm926ejs/davinci/et1011c.c for handling
ET1011C gigabit phy. which overrides get_link_speed function
from default implementation. This enables output of 125 MHz
reference clock on SYS_CLK pin.

Signed-off-by: Prakash PM <prakash.pm@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-02-02 00:54:44 +01:00
Sandeep Paulraj
57418d2139 Davinci MMCSD Support
Added support for MMC/SD cards for Davinci.  This feature is enabled by
CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC
options. This is tested on DM355 and DM365 EVMs with both the available mmc
controllers.

Signed-off-by: Alagu Sankar <alagusankar@embwise.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-02-02 00:54:44 +01:00
Stefano Babic
a4594e41b9 ARM: fix broken build of ARM
Commit 8aba9dceeb breaks
ARM boards because for ARM the -pie option is used
for partial linking together with -r option.

The patch adds the -pie option to link u-boot.bin only.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <liu.h.jason@gmail.com>
CC: lool@dooz.org
CC: Wolfgang Denk <wd@denx.de>
CC: Albert Aribaud <albert.aribaud@free.fr>
Tested-by: Alexander Holler <holler@ahsoftware.de>
2011-02-02 00:54:43 +01:00
Stefano Babic
db106ef7eb MX5: Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss
The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets corrupted.

This patch is the same as recently applied for arm926js architecture.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
2011-02-02 00:54:43 +01:00
Stefano Babic
ac87c17d34 SPI: mxc_spi: replace fixed offsets with structures
This patch cleans driver code replacing all accesses
to registers with fixed offsets with a corresponding
structure.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-02-02 00:54:43 +01:00
Stefano Babic
b9bb053159 Add support for MX35 processor
The patch adds basic support for the Freescale's i.MX35
(arm1136 based) processor.

The patch adds also a prototype for the initialization
of the FEC(ethernet controller) to netdev.h to avoid
warnings.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-02-02 00:54:42 +01:00
Liu Hui-R64343
595f3e5645 MX5: Add initial support for MX53 processor
Add initial support for Freescale MX53 processor,

- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro

Signed-off-by: Jason Liu  <r64343@freescale.com>
2011-02-02 00:54:41 +01:00
Nobuhiro Iwamatsu
8aba9dceeb Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS
Linker needs to use the proper endian/bfd flags even when doing partial linking.
LDFLAGS_u-boot sets linker option which is called it when U-boot is built
(u-boot final).
LDFLAGS sets necessary option by partial linking (use in cmd_link_o_target).

CC: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-01-25 22:22:30 +01:00
Macpaul Lin
f8ea15f769 ftpmu010: support faraday ftpmu010 driver
Faraday's ftpmu010 is a power managemnet unit which support cpu
sleep and frequency scaling. It has been integrated into many SoC.

This patch also move ftpmu010 to a proper place for later enhancement.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-01-25 22:18:57 +01:00
Wolfgang Denk
5aebe3b072 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2011-01-25 21:13:04 +01:00
Kumar Gala
92966835e9 powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 board
ctrl_regs.c: In function 'set_ddr_sdram_mode_2':
ctrl_regs.c:690:6: warning: unused variable 'i'

'i' is only used by DDR3 code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-24 23:30:23 -06:00
Dipen Dudhat
beba93ed05 powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC
Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that is
related to the LBC.

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:24 -06:00
York Sun
768d5b2baf powerpc/p4080: Fix warning in serdes code from early use of hwconfig
Hwconfig is called before relocating. Use the new hwconfig APIs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:24 -06:00
York Sun
6b06d7dc07 corenet_ds: Extend board specific parameters
Extend board specific parameters to include cpo, write leveling override
Extend write leveling sample to 0xf
Adding rcw overrid for quad-rank RDIMMs

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:24 -06:00
York Sun
fa8d23c0ee mpc85xx: Implement workaround for erratum DDR-A003
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM.
Also adding polling after enabling DDR controller to ensure completion.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:24 -06:00
York Sun
e1fd16b6f5 mpc85xx: Enable unique mode registers and dynamic ODT for DDR3
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.

Enable address parity and RCW by default for RDIMMs.

Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.

Use a formula to calculate rodt_on for timing_cfg_5.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
York Sun
d2a9568c57 mpc85xx: Adding more registers and options
This patch exposes more registers which can be used by the DDR drivers or
interactive debugging. U-boot doesn't use all the registers in DDRC.
When advanced tuning is required, writing to those registers is needed.

Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers
Add options to override rcw, address parity to RDIMMs.
Use array for debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
York Sun
47df8f03f4 mpc8xxx: Enable ECC on/off control in hwconfig
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
ECC can be turned on/off by this switch. If this switch is omitted, it is ON by
default.

Updated hwconfig calls to use local buffer.

Syntax is
hwconfig=fsl_ddr:ecc=on

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
York Sun
dd12768974 mpc8xxx: Display RDIMM if detected
Print a message when a RDIMM is detected.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Kumar Gala
243be8e296 powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headers
Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.

Eventually this should be handled by Kconfig & defconfigs

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-19 22:58:23 -06:00
Kumar Gala
dd50af2515 powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR init
There are several users of the hwconfig APIs (8xxx DDR) before we have
the environment properly setup.  This causes issues because of the
numerous ways the environment might be accessed because of the
non-volatile memory it might be stored in.  Additionally the access
might be so early that memory isn't even properly setup for us.

Towards resolving these issues we provide versions of all the hwconfig
APIs that can be passed in a buffer to parse and leave it to the caller
to determine how to allocate and populate the buffer.

We use the _f naming convention for these new APIs even though they are
perfectly useable after relocation and the environment being ready.

We also now warn if the non-f APIs are called before the environment is
ready to allow users to address the issues.

Finally, we convert the 8xxx DDR code to utilize the new APIs to
hopefully address the issue once and for all.  We have the 8xxx DDR code
create a buffer on the stack and populate it via getenv_f().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-19 22:58:23 -06:00
Kumar Gala
f193e3da98 powerpc/p2040: Add various p2040 specific information
Add P2040 SoC specific information:
* SERDES Table
* Added p2040 to cpu_type_list and SVR list
* Added number of LAWs for p2040
* Set CONFIG_MAX_CPUS to 4 for p2040

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Kumar Gala
1eda59ff6b powerpc/p5020: Add various p5020 specific information
Add P5020 SoC specific information:
* SERDES Table
* LIODN setup
* Portal configuration

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Kumar Gala
d5d2cd4331 powerpc/p3041: Add various p3041 specific information
Add P3041 SoC specific information:
* SERDES Table
* LIODN setup
* Portal configuration

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Poonam Aggrwal
b5debec5b5 powerpc/85xx: Add Support for Freescale P1014 Processor
The P1014 is similar to the P1010 processor with the following differences:

- 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC)
- no eCAN interface. (P1010 has 2 eCAN interfaces)
- Two SGMII interface (P1010 has 3 SGMII)
- No secure boot

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Poonam Aggrwal
b8cdd01462 powerpc/85xx: Add Support for Freescale P1010 Processor
Key Features include of the P1010:
* e500v2 core frequency operation of 500 to 800 MHz
* Power consumption less than 5.0 W at 800 MHz core speed
* Dual SATA 3 Gbps controllers with integrated PHY
* Dual PCI Express controllers
* Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs)
	* TCP/IP acceleration and classification capabilities
	* IEEE 1588 support
	* Lossless flow control
	* RGMII, SGMII
* DDR3 with support for a 32-bit data interface (40 bits including ECC),
  up to 800 MHz data rate 32/16-bit DDR3 memory controller
* Dedicated security engine featuring trusted boot
* TDM interface
* Dual controller area networks (FlexCAN) controller
* SD/MMC card controller supporting booting from Flash cards
* USB 2.0 host and device controller with an on-chip, high-speed PHY
* Integrated Flash controller (IFC)
* Power Management Controller (PMC)
* Four-channel, general-purpose DMA controller
* I2C controller
* Serial peripheral interface (SPI) controller with master and slave support
* System timers including a periodic interrupt timer, real-time clock,
  software watchdog timer, and four general-purpose timers
* Dual DUARTs

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Prabhakar
17028be238 Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR
CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET.
It should be as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2011-01-19 22:58:23 -06:00
Kumar Gala
7a577fda22 powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.h
Rather than defining it config.mk we can set it in config.h and remove
config.mk from several boards that don't need it.

We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for
config.h to set.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-19 22:58:23 -06:00
Haiying Wang
fc0c2b6fc9 8xxx/ddr: add support to only compute the ddr sdram size
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:22 -06:00
Peter Tyser
eddf52b593 Replace "FLASH" strings with "Flash" or "flash"
There's no compelling reason to have the output on bootup or the
"flinfo" command print "flash" in uppercase, so use the proper case
where appropriate.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2011-01-19 00:02:37 +01:00
Kumar Gala
f133796da8 powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)
Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus
monitor timeout.  Set timeout to maximum to avoid.

Based on a patch from Lan Chunhe <b25806@freescale.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Kumar Gala
868da5936e powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)
CoreNet Platform Cache single-bit data error scrubbing will cause data
corruption.  Disable the feature to workaround the issue.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Kumar Gala
1d2c2a62e3 powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)
CoreNet Platform Cache single-bit tag error scrubbing will cause tag
corruption.  Disable the feature to workaround the issue.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Kumar Gala
3dbd5d7d7e powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr code
Move the parsing of hwconfig to determine if to use spd into common code
so we can share it across all boards instead of duplicating it
everywhere.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Roy Zang
ae026ffd1e fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)
False multi-bit ECC errors will be reported by the eSDHC buffer which
can trigger a reset request.

We disable all ECC error checking on SDHC.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Roy Zang
3b4456ec39 fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.

Clear these bits out when we read HOSTCAPBLT.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Jerry Huang
d621da0066 fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)
Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Kumar Gala
5655136208 powerpc/86xx: Enable common SRIO init code
Add the needed defines and code to utilize the common 8xxx srio init
code to setup LAWs and modify device tree if we have SRIO enabled on a
board.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:21 -06:00
Kumar Gala
a09b9b68d4 powerpc/8xxx: Refactor SRIO initialization into common code
Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO.  We mimic what we do with PCIe
controllers for SRIO.

We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.

We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.

Introduced the following standard defines for board config.h:

CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available

(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)

[ These mimic what we have for PCI and PCIe controllers ]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-14 01:32:21 -06:00
Peter Tyser
213ac73e2c fsl_pci: Update PCIe boot ouput
This change does the following:
- Adds printing of negotiated link width.  This information can be
  useful when debugging PCIe issues.
- Makes it optional for boards to implement board_serdes_name().
  Previously boards that did not implement it would print unsightly
  output such as "PCIE1: Connected to <NULL>..."
- Rewords the PCIe boot output to reduce line length and to make it
  clear that the "base address XYZ" value refers to the base address of
  the internal processor PCIe registers and not a standard PCI BAR
  value.
- Changes "PCIE" output to the standard "PCIe"

Before change:
PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 05
PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
PCIE2: Bus 06 - 06

After change:
PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIe1: Bus 00 - 05
PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
PCIe2: Bus 06 - 06

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:21 -06:00
Kumar Gala
a4aafcc990 powerpc/fsl-pci: Add generic code to setup PCIe controllers
Since all the PCIe controllers are connected over SERDES on the SoCs we
can utilize is_serdes_configured() to determine if a controller is
enabled.  After which we can setup the ATMUs and LAWs for the controller
in a common fashion and allow board code to specify what the controller
is connected to for reporting reasons.

We also provide a per controller (rather than all) for some systems that
may have special requirements.

Finally, we refactor the code used by the P1022DS to utilize the new
generic code.

Based on patch by: Li Yang <leoli@freescale.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Kumar Gala
3a0e3c27a5 powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup
Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus.  Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.

Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-14 01:32:19 -06:00
Kumar Gala
45a68135c1 powerpc/85xx: Fix bug in dcache_disable
We set the L1 dache register with a bogus register value.  Need to be
using 'r3' instead of 'r0'.

Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Becky Bruce
7ea3871e06 MPC8xxx DDR: align informational prints
Add spaces to cause the informational prints to line up with
the ones from init_func_ram() in board.c.  Output now looks like
this:

....
DRAM:  Detected 4096 MB of memory
       This U-Boot only supports < 4G of DDR
       You could rebuild it with CONFIG_PHYS_64BIT
       DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off)
....

The prints from lbc_sdram_init() have also been modified to line
line up and changed to start with "LBC SDRAM" instead of the
confusing "SDRAM".

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Becky Bruce
810c442749 85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN
This config option is for an erratum workaround; rename it to be more
clear.  Also, drop it from config files don't need it and were
undefining it.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Becky Bruce
70961ba414 mpc85xx: rename sdram_init() lbc_sdram_init()
sdram_init() is used to initialize sdram on the lbc.  Rename it
accordingly.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Becky Bruce
38dba0c2ff mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts.  Most
of the initdram() functions were identical, with 2 common differences:

1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others.  I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.

2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document.  It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled.  This seems bad.

The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Becky Bruce
6b1ef2a6a5 mpc85xx/tlb.c: Allow platforms to specify wimge bits
Some platforms might want to override the default wimge=0 for
DDR.  Add CONFIG_SYS_PPC_DDR_WIMGE for those platforms to use.
This will initially only be used by TQM85xx, but could be
useful for other boards or testing going forward.  Note that
the name of this define is not 85xx-specific.  WIMGE is a
fairly universal concept, so any ppc platforms that require
different WIMGE settings for DDR can use the same #define.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Kumar Gala
5d27e02c04 powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configured
Now that we have serdes support for all 85xx/86xx/Pxxx chips we can
replace the is_fsl_pci_cfg() code with the is_serdes_configured().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Piergiorgio Beruto
afabe4b94e powerpc/85xx: Fix wrong SVR value for MPC8567 and MPC8567E processors
Signed-off-by: Piergiorgio Beruto <piergiorgio.beruto@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
70ea7f82ed powerpc/85xx: Add is_serdes_configured() support for P1021 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
877a26112d powerpc/85xx: Add is_serdes_configured() support for MPC8544 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
47567c2663 powerpc/85xx: Add is_serdes_configured() support for MPC8569 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
5ba40eec72 powerpc/85xx: Add is_serdes_configured() support for MPC8568 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
bc48d0d503 powerpc/85xx: Add is_serdes_configured() support for MPC8548 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
af87cab677 powerpc/85xx: Add is_serdes_configured() support for MPC8572 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
3818db43de powerpc/85xx: Add is_serdes_configured() support for P2020 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
af04247426 powerpc/86xx: Add SERDES support on MPC8641 & MPC8610
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.  This mimics the code we have in place
for the 85xx platforms.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
c5780a6fe9 powerpc/85xx: Create a SERDES section in Makefile
Created a section in the Makefile for SoC specific SERDES code.  Also
added P1013 SERDES (use P1022 SERDES code).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Kumar Gala
35079aa98c powerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak function
Instead of a #define use a null weak function for fsl_serdes_init

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Wolfgang Denk
c6b734f5ae Merge branch 'master' of git://git.denx.de/u-boot-sh 2011-01-12 23:59:53 +01:00
Wolfgang Denk
d52595f69e Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2011-01-12 23:54:32 +01:00
Stefan Roese
c722c708ef ppc4xx: Fix compilation breakage in miiphy.c
Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced a small
problem in the ppc4xx miiphy.c version. This patch fixes this problem.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-01-11 09:56:28 +01:00
Michal Simek
1020286ef4 microblaze: Fix bd_info pointer
Patch "Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value"
(sha1: 25ddd1fb0a)
introduce GENERATED_GBL_DATA_SIZE which is sizeof aligned gd_t
(currently 0x40).
Microblaze configs used 0x40(128) because this place also contained
board info structure which lies on the top of ram.

U-Boot is placed to the top of the ram (for example 0xd7ffffff)
and bd structure was moved out of ram.

This patch is fixing this scheme with GENERATED_BD_INFO_SIZE
which swap global data and board info structures.

For example:
Current: gd 0xd7ffffc0, bd 0xd8000000
Fixed:   gd 0xd7ffffc0, bd 0xd7ffff90

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-01-10 08:52:32 +01:00
Michal Simek
68e99e54e9 microblaze: Disabling interrupt should return 1 if was enabled
Microblaze implement enable/disable interrupts through MSR
that's why disable_interrupts function should return 1 when interrupt
was enabled. Return 0 when interrupt was disabled.

Signed-off-by: John Linn <john.linn@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-10 08:52:32 +01:00
Mike Frysinger
8ef583a035 miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-01-09 18:06:50 +01:00
Nobuhiro Iwamatsu
45ce6f9e35 sh: Add support zimageboot command for Renesas SH
Curent U-Boot can boot zImage by use the "go" command.
But this is not right method. And this method can not set command-line
to linux kernel.
zimageboot sets command-line in environment of u-boot in linux kernel,
and provides function to boot it.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2011-01-11 21:03:26 +09:00
Nobuhiro Iwamatsu
9980df5616 sh: Divided macro for zImage and add asm/zimage.h
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2011-01-11 21:03:26 +09:00
Nobuhiro Iwamatsu
858e8977eb sh: Delete the function that was not necessary
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2011-01-11 21:03:25 +09:00
Nobuhiro Iwamatsu
efc0ba4395 sh: Remove SCIF/SCI register infomation
The register information of SCIF/SCI was compiled
by drivers/serial/serial_sh.h.
Therefore, these are not necessary.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-01-11 21:03:25 +09:00
Nobuhiro Iwamatsu
c4176c43a1 sh: Add support showing KByte of flash memory size
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-01-11 21:03:25 +09:00
Nobuhiro Iwamatsu
f3a7b9535b sh: Add support SH7706
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-01-11 21:03:25 +09:00
Wolfgang Denk
cdc51c294a Merge branch 'next' of ../next 2010-12-22 21:16:17 +01:00
John Rigby
2956532625 Move DECLARE_GLOBAL_DATA_PTR to file scope
It can be optimised out by the compiler otherwise resulting
in obscure errors like a board not booting.

This has been documented in README since 2006 when these were
first fixed up for GCC 4.x.

Signed-off-by: John Rigby <john.rigby@linaro.org>

Fix some additional places.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-By: Albert ARIBAUD <albert.aribaud@free.fr>
2010-12-21 11:33:36 +01:00
Timur Tabi
96805a529c powerpc: fix register usage in some inline assembly code
In some usages of inline assembly, hard-coded registers were
specified when a scratch register should have been used instead.

Signed-off-by: Timur Tabi <timur@freescale.com>
2010-12-17 21:18:08 +01:00
Peter Tyser
c22a711d24 74xx_7xx/mpc86xx/ppmc7xx: Fix do_reset() declaration
The following commit:

commit 882b7d726f
Author: Mike Frysinger <vapier@gentoo.org>
Date:   Wed Oct 20 03:41:17 2010 -0400

    do_reset: unify duplicate prototypes

missed the 74xx_7xx and mpc86xx arches and the ppmc7xx board do_reset()
functions which resulted in build errors such as:
  cpu.c:128: error: conflicting types for 'do_reset'
  include/command.h:102: error: previous declaration of 'do_reset' was here

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-12-17 20:26:19 +01:00
Joakim Tjernlund
337f5f50f5 PowerPC: Add relocation support for -fpic
By rearranging the linker script we get support for
relocation of -fpic for free.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2010-12-17 20:25:10 +01:00
Wolfgang Denk
2a9a2339a4 Merge branch 'master' of git://git.denx.de/u-boot-arm 2010-12-17 20:02:05 +01:00
Ricardo Ribalda Delgado
d20b999115 xilinx-ppc4xx-generic: Use common u-boot.lds
Use common ppc4xx linker script for xilinx ppc440 and ppc405 related boards.

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-12-17 09:44:40 +01:00
Stefan Roese
f7b548adb5 ppc4xx: Clarify comment about boot chip-select in start.S
Ths old comment was quite screwed up. Replace it with a new version
that should be a bit more descriptive.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-12-17 09:43:36 +01:00
clagix@gmail.com
a138d96aa8 AT91RM9200: fix AT91_PMC_MCKR_MDIV_* defines for this CPU
Signed-off-by: Guido Classen <clagix@gmail.com>
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2010-12-17 09:25:43 +01:00
Prafulla Wadaskar
ce089c04a8 add Multi Function Pin configuration support for ARMADA100
This patch adds the support MFP support for Marvell ARMADA100 SoCs

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-12-16 23:02:47 +01:00
Prafulla Wadaskar
6c08d5dcf8 arm: Add Support for Marvell ARMADA 100 Familiy SoCs
ARMADA 100 Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref: http://www.marvell.com/products/processors/applications/armada_100

SoC versions Supported:
1) ARMADA168/88AP168	(Aspen P)
2) ARMADA166/88AP166	(Aspen M)
3) ARMADA162/88AP162	(Aspen L)

Contributors:
Eric Miao <eric.y.miao@gmail.com>
Lei Wen <leiwen@marvell.com>
Mahavir Jain <mjain@marvell.com>

Signed-off-by: Mahavir Jain <mjain@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-12-16 23:02:36 +01:00
Wolfgang Denk
006915fbb0 Merge branch 'master' of ../master into next 2010-12-16 23:00:53 +01:00