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powerpc/85xx: Add Support for Freescale P1010 Processor
Key Features include of the P1010: * e500v2 core frequency operation of 500 to 800 MHz * Power consumption less than 5.0 W at 800 MHz core speed * Dual SATA 3 Gbps controllers with integrated PHY * Dual PCI Express controllers * Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs) * TCP/IP acceleration and classification capabilities * IEEE 1588 support * Lossless flow control * RGMII, SGMII * DDR3 with support for a 32-bit data interface (40 bits including ECC), up to 800 MHz data rate 32/16-bit DDR3 memory controller * Dedicated security engine featuring trusted boot * TDM interface * Dual controller area networks (FlexCAN) controller * SD/MMC card controller supporting booting from Flash cards * USB 2.0 host and device controller with an on-chip, high-speed PHY * Integrated Flash controller (IFC) * Power Management Controller (PMC) * Four-channel, general-purpose DMA controller * I2C controller * Serial peripheral interface (SPI) controller with master and slave support * System timers including a periodic interrupt timer, real-time clock, software watchdog timer, and four general-purpose timers * Dual DUARTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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17028be238
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5 changed files with 13 additions and 5 deletions
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@ -50,6 +50,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
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COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
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COBJS-$(CONFIG_P1010) += ddr-gen3.o
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COBJS-$(CONFIG_P1011) += ddr-gen3.o
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COBJS-$(CONFIG_P1012) += ddr-gen3.o
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COBJS-$(CONFIG_P1013) += ddr-gen3.o
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@ -1,5 +1,5 @@
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/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
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* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
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@ -64,6 +64,8 @@ struct cpu_type cpu_type_list [] = {
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CPU_TYPE_ENTRY(8569, 8569_E, 1),
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CPU_TYPE_ENTRY(8572, 8572, 2),
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CPU_TYPE_ENTRY(8572, 8572_E, 2),
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CPU_TYPE_ENTRY(P1010, P1010, 1),
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CPU_TYPE_ENTRY(P1010, P1010_E, 1),
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CPU_TYPE_ENTRY(P1011, P1011, 1),
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CPU_TYPE_ENTRY(P1011, P1011_E, 1),
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CPU_TYPE_ENTRY(P1012, P1012, 1),
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@ -1,5 +1,5 @@
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/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -69,14 +69,16 @@
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/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
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#if defined(CONFIG_TSEC_ENET) && \
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(defined(CONFIG_P1020) || defined(CONFIG_P1011))
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(defined(CONFIG_P1010) || \
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defined(CONFIG_P1020) || defined(CONFIG_P1011))
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#define CONFIG_TSECV2
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#endif
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/*
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* SEC (crypto unit) major compatible version determination
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*/
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#if defined(CONFIG_FSL_CORENET)
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#if defined(CONFIG_FSL_CORENET) || \
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defined(CONFIG_P1010)
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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@ -1038,6 +1038,8 @@
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#define SVR_8569_E 0x808800
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#define SVR_8572 0x80E000
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#define SVR_8572_E 0x80E800
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#define SVR_P1010 0x80F100
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#define SVR_P1010_E 0x80F900
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#define SVR_P1011 0x80E500
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#define SVR_P1011_E 0x80ED00
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#define SVR_P1012 0x80E501
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@ -1,5 +1,5 @@
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/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
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defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
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#define FSL_HW_NUM_LAWS 10
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#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
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defined(CONFIG_P1010) || \
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defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
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defined(CONFIG_P1012) || defined(CONFIG_P1021) || \
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defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
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