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powerpc/85xx: Fix bug in dcache_disable

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We set the L1 dache register with a bogus register value.  Need to be
using 'r3' instead of 'r0'.

Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-01-05 10:33:46 -06:00
parent 7ea3871e06
commit 45a68135c1
1 changed files with 2 additions and 2 deletions
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4
arch/powerpc/cpu/mpc85xx/start.S
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@ -1,5 +1,5 @@
/*
* Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
* See file CREDITS for list of people who contributed to this
@ -753,7 +753,7 @@ dcache_disable:
lis r4,0
ori r4,r4,L1CSR0_DCE
andc r3,r3,r4
mtspr L1CSR0,r0
mtspr L1CSR0,r3
isync
blr