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Merge branch 'master' of ../master into next

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This commit is contained in:
Wolfgang Denk 2010-12-16 23:00:53 +01:00
commit 006915fbb0
112 changed files with 1636 additions and 661 deletions
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3
MAINTAINERS
View file

@ -310,10 +310,11 @@ Tirumala Marri <tmarri@apm.com>
bluestone APM821XX
Reinhard Meyer <r.meyer@emk-elektronik.de>
Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP860 MPC860T
TOP5200 MPC5200
TOP9000 ARM926EJS (AT91SAM9xxx SoC)
Tolunay Orkun <torkun@nextio.com>

18
MAKEALL
View file

@ -187,6 +187,7 @@ boards_by_field()
}
boards_by_arch() { boards_by_field 2 "$@" ; }
boards_by_cpu() { boards_by_field 3 "$@" ; }
boards_by_soc() { boards_by_field 6 "$@" ; }
#########################################################################
## MPC5xx Systems
@ -439,11 +440,8 @@ LIST_ARMV7=" \
## AT91 Systems
#########################################################################
LIST_at91=" \
afeb9260 \
at91cap9adk \
at91rm9200dk \
at91rm9200ek \
LIST_at91="$(boards_by_soc at91)\
$(boards_by_soc at91rm9200)\
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
@ -451,19 +449,9 @@ LIST_at91=" \
at91sam9g20ek \
at91sam9m10g45ek \
at91sam9rlek \
cmc_pu2 \
CPUAT91 \
CPU9260 \
CPU9G20 \
csb637 \
eb_cpux9k2 \
kb9202 \
meesc \
mp2usb \
m501sk \
otc570 \
pm9261 \
pm9263 \
pm9g45 \
SBC35_A9G20 \
TNY_A9260 \

3
Makefile
View file

@ -185,9 +185,6 @@ LIBS += lib/lzma/liblzma.o
LIBS += lib/lzo/liblzo.o
LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
"board/$(VENDOR)/common/lib$(VENDOR).o"; fi)
ifdef CONFIG_FSL_DIU_FB
LIBS += board/freescale/common/libfreescale.o
endif
LIBS += $(CPUDIR)/lib$(CPU).o
ifdef SOC
LIBS += $(CPUDIR)/$(SOC)/lib$(SOC).o

23
arch/arm/cpu/arm1136/start.S
View file

@ -160,6 +160,7 @@ next:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
#ifdef CONFIG_NAND_SPL
@ -186,22 +187,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -210,7 +211,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -221,10 +222,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -233,7 +234,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -251,7 +252,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -280,7 +281,7 @@ jump_2_ram:
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

23
arch/arm/cpu/arm1176/start.S
View file

@ -223,6 +223,7 @@ skip_tcmdisable:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -240,22 +241,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -264,7 +265,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -275,10 +276,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -287,7 +288,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -343,7 +344,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -372,7 +373,7 @@ _nand_boot: .word nand_boot
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

23
arch/arm/cpu/arm720t/start.S
View file

@ -138,6 +138,7 @@ reset:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -155,22 +156,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -179,7 +180,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -190,10 +191,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -202,7 +203,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -220,7 +221,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -244,7 +245,7 @@ clbss_l:str r2, [r0] /* clear loop... */
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

8
arch/arm/cpu/arm920t/at91/reset.c
View file

@ -35,7 +35,10 @@
#include <asm/arch/hardware.h>
#include <asm/arch/at91_st.h>
void board_reset(void) __attribute__((__weak__));
void __attribute__((weak)) board_reset(void)
{
/* true empty function for defining weak symbol */
}
void reset_cpu(ulong ignored)
{
@ -45,8 +48,7 @@ void reset_cpu(ulong ignored)
serial_exit();
#endif
if (board_reset)
board_reset();
board_reset();
/* Reset the cpu by setting up the watchdog timer */
writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),

29
arch/arm/cpu/arm920t/at91/timer.c
View file

@ -32,17 +32,16 @@
#include <common.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_tc.h>
#include <asm/arch/at91_pmc.h>
DECLARE_GLOBAL_DATA_PTR;
/* the number of clocks per CONFIG_SYS_HZ */
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
static u32 timestamp;
static u32 lastinc;
int timer_init(void)
{
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
@ -64,8 +63,8 @@ int timer_init(void)
writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
lastinc = 0;
timestamp = 0;
gd->lastinc = 0;
gd->tbl = 0;
return 0;
}
@ -86,7 +85,7 @@ ulong get_timer(ulong base)
void set_timer(ulong t)
{
timestamp = t;
gd->tbl = t;
}
void __udelay(unsigned long usec)
@ -98,8 +97,8 @@ void reset_timer_masked(void)
{
/* reset time */
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
timestamp = 0;
gd->lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
gd->tbl = 0;
}
ulong get_timer_raw(void)
@ -109,16 +108,16 @@ ulong get_timer_raw(void)
now = readl(&tc->tc[0].cv) & 0x0000ffff;
if (now >= lastinc) {
if (now >= gd->lastinc) {
/* normal mode */
timestamp += now - lastinc;
gd->tbl += now - gd->lastinc;
} else {
/* we have an overflow ... */
timestamp += now + TIMER_LOAD_VAL - lastinc;
gd->tbl += now + TIMER_LOAD_VAL - gd->lastinc;
}
lastinc = now;
gd->lastinc = now;
return timestamp;
return gd->tbl;
}
ulong get_timer_masked(void)

23
arch/arm/cpu/arm920t/start.S
View file

@ -184,6 +184,7 @@ copyex:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -201,22 +202,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -225,7 +226,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -236,10 +237,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -248,7 +249,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -266,7 +267,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -297,7 +298,7 @@ _nand_boot_ofs:
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

23
arch/arm/cpu/arm925t/start.S
View file

@ -175,6 +175,7 @@ poll1:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -192,22 +193,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -216,7 +217,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -227,10 +228,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -239,7 +240,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -257,7 +258,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -288,7 +289,7 @@ _nand_boot_ofs:
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

5
arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
View file

@ -204,6 +204,11 @@ void at91_macb_hw_init(void)
#else
at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
#if defined(CONFIG_AT91SAM9G20)
/* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
#endif
#endif
at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
#endif

75
arch/arm/cpu/arm926ejs/davinci/timer.c
View file

@ -40,6 +40,8 @@
#include <common.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
struct davinci_timer {
u_int32_t pid12;
u_int32_t emumgt;
@ -57,11 +59,9 @@ struct davinci_timer {
static struct davinci_timer * const timer =
(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define TIM_CLK_DIV 16
#define TIMER_LOAD_VAL 0xffffffff
static ulong timestamp;
static ulong lastinc;
#define TIM_CLK_DIV 16
int timer_init(void)
{
@ -71,72 +71,51 @@ int timer_init(void)
writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
writel(0x0, &timer->tim34);
writel(TIMER_LOAD_VAL, &timer->prd34);
lastinc = 0;
timestamp = 0;
writel(2 << 22, &timer->tcr);
gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
gd->timer_reset_value = 0;
return(0);
}
void reset_timer(void)
{
writel(0x0, &timer->tcr);
writel(0x0, &timer->tim34);
lastinc = 0;
timestamp = 0;
writel(2 << 22, &timer->tcr);
gd->timer_reset_value = get_ticks();
}
static ulong get_timer_raw(void)
/*
* Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)
{
ulong now = readl(&timer->tim34);
unsigned long now = readl(&timer->tim34);
if (now >= lastinc) {
/* normal mode */
timestamp += now - lastinc;
} else {
/* overflow ... */
timestamp += now + TIMER_LOAD_VAL - lastinc;
}
lastinc = now;
return timestamp;
/* increment tbu if tbl has rolled over */
if (now < gd->tbl)
gd->tbu++;
gd->tbl = now;
return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
}
ulong get_timer(ulong base)
{
return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base);
}
unsigned long long timer_diff;
void set_timer(ulong t)
{
timestamp = t;
timer_diff = get_ticks() - gd->timer_reset_value;
return (timer_diff / (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
}
void __udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
signed long diff;
unsigned long long endtime;
tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= (1000 * TIM_CLK_DIV);
endtime = ((unsigned long long)usec * gd->timer_rate_hz) / 1000000UL;
endtime += get_ticks();
endtime = get_timer_raw() + tmo;
do {
ulong now = get_timer_raw();
diff = endtime - now;
} while (diff >= 0);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return(get_timer(0));
while (get_ticks() < endtime)
;
}
/*

12
arch/arm/cpu/arm926ejs/mx25/generic.c
View file

@ -260,4 +260,16 @@ void mx25_fec_init_pins (void)
writel (outpadctl, &padctl->pad_fec_tdata1);
}
void imx_get_mac_from_fuse(unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif /* CONFIG_FEC_MXC */

12
arch/arm/cpu/arm926ejs/mx27/generic.c
View file

@ -313,6 +313,18 @@ void mx27_fec_init_pins(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
void imx_get_mac_from_fuse(unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MXC_MMC

23
arch/arm/cpu/arm926ejs/start.S
View file

@ -174,6 +174,7 @@ reset:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -191,22 +192,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -215,7 +216,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -226,10 +227,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -238,7 +239,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -256,7 +257,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -287,7 +288,7 @@ _nand_boot_ofs:
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

23
arch/arm/cpu/arm946es/start.S
View file

@ -146,6 +146,7 @@ reset:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -163,22 +164,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -187,7 +188,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -198,10 +199,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -210,7 +211,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -228,7 +229,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -254,7 +255,7 @@ _nand_boot: .word nand_boot
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

23
arch/arm/cpu/arm_intcm/start.S
View file

@ -142,6 +142,7 @@ reset:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -159,22 +160,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -183,7 +184,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -194,10 +195,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -206,7 +207,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -224,7 +225,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -255,7 +256,7 @@ _nand_boot_ofs:
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

14
arch/arm/cpu/armv7/mx5/soc.c
View file

@ -100,6 +100,20 @@ int cpu_eth_init(bd_t *bis)
return rc;
}
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[1];
struct fuse_bank1_regs *fuse =
(struct fuse_bank1_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()

22
arch/arm/cpu/armv7/omap-common/timer.c
View file

@ -35,8 +35,8 @@
#include <common.h>
#include <asm/io.h>
static ulong timestamp;
static ulong lastinc;
DECLARE_GLOBAL_DATA_PTR;
static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
/*
@ -74,7 +74,7 @@ ulong get_timer(ulong base)
void set_timer(ulong t)
{
timestamp = t;
gd->tbl = t;
}
/* delay x useconds */
@ -96,8 +96,8 @@ void __udelay(unsigned long usec)
void reset_timer_masked(void)
{
/* reset time, capture current incrementer value time */
lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
timestamp = 0; /* start "advancing" time stamp from 0 */
gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
gd->tbl = 0; /* start "advancing" time stamp from 0 */
}
ulong get_timer_masked(void)
@ -105,14 +105,14 @@ ulong get_timer_masked(void)
/* current tick value */
ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
if (now >= lastinc) /* normal mode (non roll) */
if (now >= gd->lastinc) /* normal mode (non roll) */
/* move stamp fordward with absoulte diff ticks */
timestamp += (now - lastinc);
gd->tbl += (now - gd->lastinc);
else /* we have rollover of incrementer */
timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
- lastinc) + now;
lastinc = now;
return timestamp;
gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
- gd->lastinc) + now;
gd->lastinc = now;
return gd->tbl;
}
/*

8
arch/arm/cpu/armv7/omap3/emif4.c
View file

@ -29,6 +29,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/emif4.h>
DECLARE_GLOBAL_DATA_PTR;
extern omap3_sysinfo sysinfo;
static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
@ -48,10 +49,11 @@ u32 is_mem_sdr(void)
*/
u32 get_sdr_cs_size(u32 cs)
{
u32 size;
u32 size = 0;
/* TODO: Calculate the size based on EMIF4 configuration */
size = CONFIG_SYS_CS0_SIZE;
if (cs == CS0)
size = CONFIG_SYS_CS0_SIZE;
return size;
}
@ -138,7 +140,6 @@ void do_emif4_init(void)
*/
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
@ -156,7 +157,6 @@ int dram_init(void)
void dram_init_banksize (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);

3
arch/arm/cpu/armv7/omap3/sdrc.c
View file

@ -37,6 +37,7 @@
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
extern omap3_sysinfo sysinfo;
static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
@ -172,7 +173,6 @@ void do_sdrc_init(u32 cs, u32 early)
*/
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
@ -194,7 +194,6 @@ int dram_init(void)
void dram_init_banksize (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);

16
arch/arm/cpu/armv7/s5p-common/timer.c
View file

@ -65,15 +65,12 @@ int timer_init(void)
writel((PRESCALER_1 & 0xff) << 8, &timer->tcfg0);
writel((MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT, &timer->tcfg1);
if (count_value == 0) {
/* reset initial value */
/* count_value = 2085937.5(HZ) (per 1 sec)*/
count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
(MUX_DIV_2 + 1));
/* count_value = 2085937.5(HZ) (per 1 sec)*/
count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
(MUX_DIV_2 + 1));
/* count_value / 100 = 20859.375(HZ) (per 10 msec) */
count_value = count_value / 100;
}
/* count_value / 100 = 20859.375(HZ) (per 10 msec) */
count_value = count_value / 100;
/* set count value */
writel(count_value, &timer->tcntb4);
@ -114,8 +111,11 @@ void set_timer(unsigned long t)
/* delay x useconds */
void __udelay(unsigned long usec)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long tmo, tmp;
count_value = readl(&timer->tcntb4);
if (usec >= 1000) {
/*
* if "big" number, spread normalization

27
arch/arm/cpu/armv7/start.S
View file

@ -142,6 +142,7 @@ next:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -159,24 +160,24 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
#ifndef CONFIG_PRELOADER
cmp r0, r6
beq clear_bss /* skip relocation */
#endif
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
#ifndef CONFIG_PRELOADER
beq jump_2_ram
#endif
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -185,7 +186,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -196,10 +197,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -208,7 +209,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -224,7 +225,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -246,7 +247,7 @@ jump_2_ram:
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

1
arch/arm/cpu/armv7/syslib.c
View file

@ -23,7 +23,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
/************************************************************
* sdelay() - simple spin loop. Will be constant time as

23
arch/arm/cpu/ixp/start.S
View file

@ -268,6 +268,7 @@ reset:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -285,22 +286,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -309,7 +310,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -320,10 +321,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -332,7 +333,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -350,7 +351,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -374,7 +375,7 @@ clbss_l:str r2, [r0] /* clear loop... */
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

23
arch/arm/cpu/lh7a40x/start.S
View file

@ -155,6 +155,7 @@ reset:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -172,22 +173,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -196,7 +197,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -207,10 +208,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -219,7 +220,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -237,7 +238,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -258,7 +259,7 @@ clbss_l:str r2, [r0] /* clear loop... */
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

23
arch/arm/cpu/pxa/start.S
View file

@ -220,6 +220,7 @@ zerojmp:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -237,23 +238,23 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
stmfd sp!, {r0-r12}
copy_loop:
ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
stmia r6!, {r3-r5, r7-r11} /* copy to target address [r1] */
stmia r1!, {r3-r5, r7-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
ldmfd sp!, {r0-r12}
@ -263,7 +264,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -274,10 +275,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -286,7 +287,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -304,7 +305,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -332,7 +333,7 @@ _start_oneboot_ofs
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

23
arch/arm/cpu/s3c44b0/start.S
View file

@ -127,6 +127,7 @@ reset:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -144,22 +145,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -168,7 +169,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -179,10 +180,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -191,7 +192,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -209,7 +210,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -233,7 +234,7 @@ clbss_l:str r2, [r0] /* clear loop... */
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

23
arch/arm/cpu/sa1100/start.S
View file

@ -131,6 +131,7 @@ reset:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@ -148,22 +149,22 @@ relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -172,7 +173,7 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -183,10 +184,10 @@ fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -195,7 +196,7 @@ fixabs:
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
@ -213,7 +214,7 @@ clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -234,7 +235,7 @@ clbss_l:str r2, [r0] /* clear loop... */
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr

19
arch/arm/include/asm/arch-mx25/imx-regs.h
View file

@ -36,6 +36,7 @@
#ifndef __ASSEMBLY__
#ifdef CONFIG_FEC_MXC
extern void mx25_fec_init_pins(void);
extern void imx_get_mac_from_fuse(unsigned char *mac);
#endif
/* Clock Control Module (CCM) registers */
@ -129,12 +130,17 @@ struct iim_regs {
u32 iim_srev;
u32 iim_prog_p;
u32 res1[0x1f5];
u32 iim_bank_area0[0x20];
u32 res2[0xe0];
u32 iim_bank_area1[0x20];
u32 res3[0xe0];
u32 iim_bank_area2[0x20];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
} bank[3];
};
struct fuse_bank0_regs {
u32 fuse0_25[0x1a];
u32 mac_addr[6];
};
#endif
/* AIPS 1 */
@ -312,7 +318,4 @@ struct iim_regs {
#define WSR_UNLOCK1 0x5555
#define WSR_UNLOCK2 0xAAAA
/* FUSE bank offsets */
#define IIM0_MAC 0x1a
#endif /* _IMX_REGS_H */

20
arch/arm/include/asm/arch-mx27/imx-regs.h
View file

@ -34,6 +34,7 @@ extern void mx27_uart_init_pins(void);
#ifdef CONFIG_FEC_MXC
extern void mx27_fec_init_pins(void);
extern void imx_get_mac_from_fuse(unsigned char *mac);
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MXC_MMC
@ -202,9 +203,19 @@ struct iim_regs {
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
u32 res[0x1F0];
u32 iim_bank_area0[0x100];
u32 res[0x1f1];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
} bank[1];
};
struct fuse_bank0_regs {
u32 fuse0_3[5];
u32 mac_addr[6];
u32 fuse10_31[0x16];
};
#endif
#define IMX_IO_BASE 0x10000000
@ -512,9 +523,4 @@ struct iim_regs {
#define IIM_ERR_SNSE (1 << 2)
#define IIM_ERR_PARITYE (1 << 1)
/* Definitions for i.MX27 TO2 */
#define IIM0_MAC 5
#define IIM0_SCC_KEY 11
#define IIM1_SUID 1
#endif /* _IMX_REGS_H */

34
arch/arm/include/asm/arch-mx5/imx-regs.h
View file

@ -205,9 +205,13 @@
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
#define IMX_IIM_BASE (IIM_BASE_ADDR)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
extern void imx_get_mac_from_fuse(unsigned char *mac);
#define __REG(x) (*((volatile u32 *)(x)))
#define __REG16(x) (*((volatile u16 *)(x)))
#define __REG8(x) (*((volatile u8 *)(x)))
@ -275,6 +279,36 @@ struct src {
u32 sisr;
u32 simr;
};
struct iim_regs {
u32 stat;
u32 statm;
u32 err;
u32 emask;
u32 fctl;
u32 ua;
u32 la;
u32 sdat;
u32 prev;
u32 srev;
u32 preg_p;
u32 scs0;
u32 scs1;
u32 scs2;
u32 scs3;
u32 res0[0x1f1];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
} bank[4];
};
struct fuse_bank1_regs {
u32 fuse0_8[9];
u32 mac_addr[6];
u32 fuse15_31[0x11];
};
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MXC_MX51_H__ */

5
arch/arm/include/asm/global_data.h
View file

@ -55,11 +55,14 @@ typedef struct global_data {
unsigned long plla_rate_hz;
unsigned long pllb_rate_hz;
unsigned long at91_pllb_usb_init;
/* "static data" needed by at91's timer.c */
#endif
#ifdef CONFIG_ARM
/* "static data" needed by most of timer.c on ARM platforms */
unsigned long timer_rate_hz;
unsigned long tbl;
unsigned long tbu;
unsigned long long timer_reset_value;
unsigned long lastinc;
#endif
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */

2
arch/arm/lib/board.c
View file

@ -276,7 +276,7 @@ void board_init_f (ulong bootflag)
ulong addr, addr_sp;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_SP_ADDR);
gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");

12
arch/powerpc/cpu/mpc83xx/pcie.c
View file

@ -201,18 +201,18 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
out_le32(&out_win->tarl, 0);
out_le32(&out_win->tarh, 0);
for (i = 0; i < 2; i++, reg++) {
for (i = 0; i < 2; i++) {
u32 ar;
if (reg->size == 0)
if (reg[i].size == 0)
break;
out_win = &pex->bridge.pex_outbound_win[i + 1];
out_le32(&out_win->bar, reg->phys_start);
out_le32(&out_win->tarl, reg->bus_start);
out_le32(&out_win->bar, reg[i].phys_start);
out_le32(&out_win->tarl, reg[i].bus_start);
out_le32(&out_win->tarh, 0);
ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE);
if (reg->flags & PCI_REGION_IO)
ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
if (reg[i].flags & PCI_REGION_IO)
ar |= PEX_OWAR_TYPE_IO;
else
ar |= PEX_OWAR_TYPE_MEM;

8
arch/powerpc/cpu/mpc83xx/start.S
View file

@ -1158,6 +1158,10 @@ map_flash_by_law1:
bne 1b
stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
/* Wait for HW to catch up */
lwz r4, LBLAWAR1(r3)
twi 0,r4,0
isync
blr
/* Though all the LBIU Local Access Windows and LBC Banks will be
@ -1196,5 +1200,9 @@ remap_flash_by_law0:
xor r4, r4, r4
stw r4, LBLAWBAR1(r3)
stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
/* Wait for HW to catch up */
lwz r4, LBLAWAR1(r3)
twi 0,r4,0
isync
blr
#endif /* CONFIG_SYS_FLASHBOOT */

2
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -327,7 +327,7 @@ int cpu_init_r(void)
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
puts("already enabled");
l2srbar = l2cache->l2srbar0;
#ifdef CONFIG_SYS_INIT_L2_ADDR
#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
l2srbar = CONFIG_SYS_INIT_L2_ADDR;

11
arch/powerpc/lib/board.c
View file

@ -645,6 +645,17 @@ void board_init_r (gd_t *id, ulong dest_addr)
gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
#endif
#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
/*
* Some systems need to relocate the env_addr pointer early because the
* location it points to will get invalidated before env_relocate is
* called. One example is on systems that might use a L2 or L3 cache
* in SRAM mode and initialize that cache from SRAM mode back to being
* a cache in cpu_init_r.
*/
gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
#endif
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif

8
arch/sh/cpu/sh2/start.S
View file

@ -26,7 +26,7 @@
.align 2
.global _start
_start:
_sh_start:
.long 0x00000010 /* Ppower ON reset PC*/
.long 0x00000000
.long 0x00000010 /* Manual reset PC */
@ -39,7 +39,7 @@ _init:
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
add #(_start-1b), r5
add #(_sh_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
@ -74,6 +74,6 @@ loop:
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init

8
arch/sh/cpu/sh3/start.S
View file

@ -29,7 +29,7 @@
.align 2
.global _start
_start:
_sh_start:
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
@ -38,7 +38,7 @@ _start:
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
add #(_start-1b), r5
add #(_sh_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
@ -73,6 +73,6 @@ loop:
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init

10
arch/sh/cpu/sh4/start.S
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2007
* (C) Copyright 2007, 2010
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
@ -26,7 +26,7 @@
.align 2
.global _start
_start:
_sh_start:
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
@ -35,7 +35,7 @@ _start:
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
add #(_start-1b), r5
add #(_sh_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
@ -70,6 +70,6 @@ loop:
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init

49
board/amcc/acadia/u-boot-nand.lds
View file

@ -26,34 +26,12 @@ SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text)
arch/powerpc/cpu/ppc4xx/start.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
@ -61,8 +39,7 @@ SECTIONS
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
*(.text)
*(.got1)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
@ -70,9 +47,6 @@ SECTIONS
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
@ -80,23 +54,19 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
*(.got)
KEEP(*(.got))
_GOT2_TABLE_ = .;
*(.got2)
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
*(.fixup)
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
@ -122,9 +92,8 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}

49
board/amcc/kilauea/u-boot-nand.lds
View file

@ -26,34 +26,12 @@ SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text)
arch/powerpc/cpu/ppc4xx/start.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
@ -61,8 +39,7 @@ SECTIONS
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
*(.text)
*(.got1)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
@ -70,9 +47,6 @@ SECTIONS
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
@ -80,23 +54,19 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
*(.got)
KEEP(*(.got))
_GOT2_TABLE_ = .;
*(.got2)
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
*(.fixup)
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
@ -122,9 +92,8 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}

11
board/armltd/vexpress/ca9x4_ct_vxp.c
View file

@ -95,16 +95,19 @@ static void flash__init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
gd->ram_size =
get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[0].size =
get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size(PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->bd->bi_dram[1].size =
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
}
int timer_init(void)
@ -154,7 +157,7 @@ void reset_cpu(ulong addr)
* Delay x useconds AND perserve advance timstamp value
* assumes timer is ticking at 1 msec
*/
void udelay(ulong usec)
void __udelay(ulong usec)
{
ulong tmo, tmp;

3
board/armltd/vexpress/config.mk
View file

@ -19,5 +19,4 @@
#
# Linux-Kernel is expected to be at 0x60008000
#
TEXT_BASE = 0x60800000
LDSCRIPT := $(SRCTREE)/board/armltd/vexpress/u-boot.lds
CONFIG_SYS_TEXT_BASE = 0x60800000

65
board/armltd/vexpress/u-boot.lds
View file

@ -1,65 +0,0 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
arch/arm/cpu/armv7/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata))) }
. = ALIGN(4);
.data : { *(.data)
__datarel_start = .;
*(.data.rel)
__datarelrolocal_start = .;
*(.data.rel.ro.local)
__datarellocal_start = .;
*(.data.rel.local)
__datarelro_start = .;
*(.data.rel.ro)
}
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
__got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

2
board/atmel/at91rm9200ek/config.mk
View file

@ -1,2 +0,0 @@
# currently only NOR flash booting is supported
CONFIG_SYS_TEXT_BASE = 0x10000000

54
board/emk/top9000/Makefile Normal file
View file

@ -0,0 +1,54 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2010
# Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += top9000.o
COBJS-$(CONFIG_ATMEL_SPI) += spi.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

61
board/emk/top9000/spi.c Normal file
View file

@ -0,0 +1,61 @@
/*
* Copyright (C) 2010
* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_spi.h>
#include <asm/arch/gpio.h>
#include <spi.h>
static const struct {
u32 port;
u32 bit;
} cs_to_portbit[2][4] = {
{{AT91_PIO_PORTA, 3}, {AT91_PIO_PORTC, 11},
{AT91_PIO_PORTC, 16}, {AT91_PIO_PORTC, 17} },
{{AT91_PIO_PORTB, 3}, {AT91_PIO_PORTC, 5},
{AT91_PIO_PORTC, 4}, {AT91_PIO_PORTC, 3} }
};
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs);
if (bus < 2 && cs < 4)
return 1;
return 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs);
at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
cs_to_portbit[slave->bus][slave->cs].bit, 0);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs);
at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
cs_to_portbit[slave->bus][slave->cs].bit, 1);
}

290
board/emk/top9000/top9000.c Normal file
View file

@ -0,0 +1,290 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2010
* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <net.h>
#include <netdev.h>
#include <mmc.h>
#include <i2c.h>
#include <spi.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_shdwn.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 |
AT91_SMC_TDF_(2));
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void macb_hw_init(void)
{
/* Enable EMAC clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
/* Initialize EMAC=MACB hardware */
at91_macb_hw_init();
}
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
/* Enable MCI clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI);
/* Initialize MCI hardware */
at91_mci_hw_init();
/* This calls the atmel_mmc_init in gen_atmel_mci.c */
return atmel_mci_init((void *)AT91_BASE_MCI);
}
/* this is a weak define that we are overriding */
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
/*
* the only currently existing use of this function
* (fsl_esdhc.c) suggests this function must return
* *cs = TRUE if a card is NOT detected -> in most
* cases the value of the pin when the detect switch
* closes to GND
*/
*cd = at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0;
return 0;
}
#endif
int board_early_init_f(void)
{
at91_shdwn_t *shdwn = (at91_shdwn_t *)AT91_SHDWN_BASE;
/*
* make sure the board can be powered on by
* any transition on WKUP
*/
writel(AT91_SHDW_MR_WKMODE0H2L | AT91_SHDW_MR_WKMODE0L2H,
&shdwn->mr);
/* Enable clocks for all PIOs */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOB);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
/* set SCL0 and SDA0 to open drain */
at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1);
at91_set_pio_multi_drive(I2C0_PORT, SCL0_PIN, 1);
at91_set_pio_pullup(I2C0_PORT, SCL0_PIN, 1);
at91_set_pio_output(I2C0_PORT, SDA0_PIN, 1);
at91_set_pio_multi_drive(I2C0_PORT, SDA0_PIN, 1);
at91_set_pio_pullup(I2C0_PORT, SDA0_PIN, 1);
/* set SCL1 and SDA1 to open drain */
at91_set_pio_output(I2C1_PORT, SCL1_PIN, 1);
at91_set_pio_multi_drive(I2C1_PORT, SCL1_PIN, 1);
at91_set_pio_pullup(I2C1_PORT, SCL1_PIN, 1);
at91_set_pio_output(I2C1_PORT, SDA1_PIN, 1);
at91_set_pio_multi_drive(I2C1_PORT, SDA1_PIN, 1);
at91_set_pio_pullup(I2C1_PORT, SDA1_PIN, 1);
return 0;
}
int board_init(void)
{
/* arch number of TOP9000 Board */
gd->bd->bi_arch_number = MACH_TYPE_TOP9000;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
at91_serial_hw_init();
#ifdef CONFIG_CMD_NAND
nand_hw_init();
#endif
#ifdef CONFIG_MACB
macb_hw_init();
#endif
#ifdef CONFIG_ATMEL_SPI0
/* (n+4) denotes to use nSPISEL(0) in GPIO mode! */
at91_spi0_hw_init(1 << (FRAM_CS_NUM + 4));
#endif
#ifdef CONFIG_ATMEL_SPI1
at91_spi1_hw_init(1 << (ENC_CS_NUM + 4));
#endif
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
/* read 'factory' part of EEPROM */
read_factory_r();
return 0;
}
#endif
int dram_init(void)
{
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
/*
* Initialize ethernet HW addresses prior to starting Linux,
* needed for nfsroot.
* TODO: We need to investigate if that is really necessary.
*/
eth_init(gd->bd);
}
#endif
int board_eth_init(bd_t *bis)
{
int rc = 0;
int num = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0,
(void *)AT91_EMAC_BASE,
CONFIG_SYS_PHY_ID);
if (!rc)
num++;
#endif
#ifdef CONFIG_ENC28J60
rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM,
ENC_SPI_CLOCK, SPI_MODE_0);
if (!rc)
num++;
# ifdef CONFIG_ENC28J60_2
rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+1,
ENC_SPI_CLOCK, SPI_MODE_0);
if (!rc)
num++;
# ifdef CONFIG_ENC28J60_3
rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+2,
ENC_SPI_CLOCK, SPI_MODE_0);
if (!rc)
num++;
# endif
# endif
#endif
return num;
}
/*
* I2C access functions
*
* Note:
* We need to access Bus 0 before relocation to access the
* environment settings.
* However i2c_get_bus_num() cannot be called before
* relocation.
*/
#ifdef CONFIG_SOFT_I2C
void iic_init(void)
{
/* ports are now initialized in board_early_init_f() */
}
int iic_read(void)
{
switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
case 0:
return at91_get_pio_value(I2C0_PORT, SDA0_PIN);
case 1:
return at91_get_pio_value(I2C1_PORT, SDA1_PIN);
}
return 1;
}
void iic_sda(int bit)
{
switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
case 0:
at91_set_pio_value(I2C0_PORT, SDA0_PIN, bit);
break;
case 1:
at91_set_pio_value(I2C1_PORT, SDA1_PIN, bit);
break;
}
}
void iic_scl(int bit)
{
switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
case 0:
at91_set_pio_value(I2C0_PORT, SCL0_PIN, bit);
break;
case 1:
at91_set_pio_value(I2C1_PORT, SCL1_PIN, bit);
break;
}
}
#endif

1
board/freescale/common/Makefile
View file

@ -31,7 +31,6 @@ LIB = $(obj)libfreescale.o
COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o
COBJS-$(CONFIG_FSL_VIA) += cds_via.o
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o
COBJS-$(CONFIG_FSL_PIXIS) += pixis.o
COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o

3
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View file

@ -60,9 +60,6 @@ int checkboard(void)
return 0;
}
const char *board_hwconfig = "foo:bar=baz";
const char *cpu_hwconfig = "foo:bar=baz";
phys_size_t
initdram(int board_type)
{

67
board/freescale/p1022ds/diu.c
View file

@ -32,6 +32,7 @@
#define PMUXCR_ELBCDIU_MASK 0xc0000000
#define PMUXCR_ELBCDIU_NOR16 0x80000000
#define PMUXCR_ELBCDIU_DIU 0x40000000
/*
* DIU Area Descriptor
@ -131,9 +132,8 @@ int platform_diu_init(unsigned int *xres, unsigned int *yres)
px_brdcfg0 = in_8(lbc_lcs1_ba);
out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
/* Setting PMUXCR to switch to DVI from ELBC */
clrsetbits_be32(&gur->pmuxcr,
PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_NOR16);
/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
pmuxcr = in_be32(&gur->pmuxcr);
return fsl_diu_init(*xres, pixel_format, 0);
@ -161,7 +161,7 @@ static int set_mux_to_lbc(void)
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Switch the muxes only if they're currently set to DIU mode */
if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) ==
if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
PMUXCR_ELBCDIU_NOR16) {
/*
* In DIU mode, the PIXIS can only be accessed indirectly
@ -216,8 +216,17 @@ void flash_write8(u8 value, void *addr)
int sw = set_mux_to_lbc();
__raw_writeb(value, addr);
if (sw)
if (sw) {
/*
* To ensure the post-write is completed to eLBC, software must
* perform a dummy read from one valid address from eLBC space
* before changing the eLBC_DIU from NOR mode to DIU mode.
* set_mux_to_diu() includes a sync that will ensure the
* __raw_readb() completes before it switches the mux.
*/
__raw_readb(addr);
set_mux_to_diu();
}
}
void flash_write16(u16 value, void *addr)
@ -225,8 +234,17 @@ void flash_write16(u16 value, void *addr)
int sw = set_mux_to_lbc();
__raw_writew(value, addr);
if (sw)
if (sw) {
/*
* To ensure the post-write is completed to eLBC, software must
* perform a dummy read from one valid address from eLBC space
* before changing the eLBC_DIU from NOR mode to DIU mode.
* set_mux_to_diu() includes a sync that will ensure the
* __raw_readb() completes before it switches the mux.
*/
__raw_readb(addr);
set_mux_to_diu();
}
}
void flash_write32(u32 value, void *addr)
@ -234,18 +252,47 @@ void flash_write32(u32 value, void *addr)
int sw = set_mux_to_lbc();
__raw_writel(value, addr);
if (sw)
if (sw) {
/*
* To ensure the post-write is completed to eLBC, software must
* perform a dummy read from one valid address from eLBC space
* before changing the eLBC_DIU from NOR mode to DIU mode.
* set_mux_to_diu() includes a sync that will ensure the
* __raw_readb() completes before it switches the mux.
*/
__raw_readb(addr);
set_mux_to_diu();
}
}
void flash_write64(u64 value, void *addr)
{
int sw = set_mux_to_lbc();
uint32_t *p = addr;
/* There is no __raw_writeq(), so do the write manually */
*(volatile u64 *)addr = value;
if (sw)
/*
* There is no __raw_writeq(), so do the write manually. We don't trust
* the compiler, so we use inline assembly.
*/
__asm__ __volatile__(
"stw%U0%X0 %2,%0;\n"
"stw%U1%X1 %3,%1;\n"
: "=m" (*p), "=m" (*(p + 1))
: "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
if (sw) {
/*
* To ensure the post-write is completed to eLBC, software must
* perform a dummy read from one valid address from eLBC space
* before changing the eLBC_DIU from NOR mode to DIU mode. We
* read addr+4 because we just wrote to addr+4, so that's how we
* maintain execution order. set_mux_to_diu() includes a sync
* that will ensure the __raw_readb() completes before it
* switches the mux.
*/
__raw_readb(addr + 4);
set_mux_to_diu();
}
}
u8 flash_read8(void *addr)

3
board/freescale/p2020ds/p2020ds.c
View file

@ -69,9 +69,6 @@ int checkboard(void)
return 0;
}
const char *board_hwconfig = "foo:bar=baz";
const char *cpu_hwconfig = "foo:bar=baz";
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;

2
board/logicpd/am3517evm/config.mk
View file

@ -27,4 +27,4 @@
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x80e80000
CONFIG_SYS_TEXT_BASE = 0x80008000

2
board/logicpd/zoom1/config.mk
View file

@ -30,4 +30,4 @@
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x80e80000
CONFIG_SYS_TEXT_BASE = 0x80008000

2
board/logicpd/zoom2/config.mk
View file

@ -30,4 +30,4 @@
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x80e80000
CONFIG_SYS_TEXT_BASE = 0x80008000

1
board/ronetix/pm9261/config.mk
View file

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x23f00000

9
board/ronetix/pm9261/pm9261.c
View file

@ -280,10 +280,17 @@ int board_eth_init(bd_t *bis)
#endif
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R

1
board/ronetix/pm9263/config.mk
View file

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x23f00000

9
board/ronetix/pm9263/pm9263.c
View file

@ -377,10 +377,17 @@ int board_init(void)
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R

1
board/ronetix/pm9g45/config.mk
View file

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x73f00000

9
board/ronetix/pm9g45/pm9g45.c
View file

@ -158,10 +158,17 @@ int board_init(void)
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R

10
board/samsung/goni/goni.c
View file

@ -42,6 +42,14 @@ int board_init(void)
}
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
PHYS_SDRAM_3_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
@ -49,8 +57,6 @@ int dram_init(void)
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO

10
board/samsung/smdkc100/smdkc100.c
View file

@ -65,13 +65,17 @@ int board_init(void)
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{

2
board/ti/sdp3430/config.mk
View file

@ -30,4 +30,4 @@
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x80e80000
CONFIG_SYS_TEXT_BASE = 0x80008000

11
boards.cfg
View file

@ -48,7 +48,8 @@ lpc2292sodimm arm arm720t - -
SMN42 arm arm720t - siemens lpc2292
evb4510 arm arm720t - - s3c4510b
a320evb arm arm920t - faraday a320
at91rm9200ek arm arm920t - atmel at91
at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek
at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT
eb_cpux9k2 arm arm920t - BuS at91
cmc_pu2 arm arm920t - - at91rm9200
csb637 arm arm920t - - at91rm9200
@ -70,6 +71,8 @@ voiceblue arm arm925t
omap1510inn arm arm925t - ti
afeb9260 arm arm926ejs - - at91
at91cap9adk arm arm926ejs - atmel at91
top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000
top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000
meesc arm arm926ejs - esd at91
otc570 arm arm926ejs - esd at91
pm9261 arm arm926ejs - ronetix at91
@ -407,10 +410,10 @@ vme8349 powerpc mpc83xx vme8349 esd
MPC8308RDB powerpc mpc83xx mpc8308rdb freescale
MPC8313ERDB_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ
MPC8313ERDB_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ
MPC8313ERDB_NAND_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ,NAND_U_BOOT,SYS_TEXT_BASE=0x00100000
MPC8313ERDB_NAND_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ,NAND_U_BOOT,SYS_TEXT_BASE=0x00100000
MPC8313ERDB_NAND_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ,NAND_U_BOOT
MPC8313ERDB_NAND_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ,NAND_U_BOOT
MPC8315ERDB powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB
MPC8315ERDB_NAND powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB:NAND
MPC8315ERDB_NAND powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB:NAND_U_BOOT
MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale
MPC832XEMDS powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:
MPC832XEMDS_ATM powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1

4
common/cmd_onenand.c
View file

@ -293,7 +293,7 @@ static int onenand_dump(struct mtd_info *mtd, ulong off, int only_oob)
addr = (loff_t) off;
memset(&ops, 0, sizeof(ops));
ops.datbuf = datbuf;
ops.oobbuf = oobbuf; /* must exist, but oob data will be appended to ops.datbuf */
ops.oobbuf = oobbuf;
ops.len = mtd->writesize;
ops.ooblen = mtd->oobsize;
ops.retlen = 0;
@ -319,6 +319,8 @@ static int onenand_dump(struct mtd_info *mtd, ulong off, int only_oob)
}
puts("OOB:\n");
i = mtd->oobsize >> 3;
p = oobbuf;
while (i--) {
printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);

15
common/cmd_ubi.c
View file

@ -42,6 +42,11 @@ struct selected_dev {
static struct selected_dev ubi_dev;
#ifdef CONFIG_CMD_UBIFS
int ubifs_is_mounted(void);
void cmd_ubifs_umount(void);
#endif
static void ubi_dump_vol_info(const struct ubi_volume *vol)
{
ubi_msg("volume information dump:");
@ -472,6 +477,16 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
if (argc < 3)
return cmd_usage(cmdtp);
#ifdef CONFIG_CMD_UBIFS
/*
* Automatically unmount UBIFS partition when user
* changes the UBI device. Otherwise the following
* UBIFS commands will crash.
*/
if (ubifs_is_mounted())
cmd_ubifs_umount();
#endif
/* todo: get dev number for NAND... */
ubi_dev.nr = 0;

47
common/cmd_ubifs.c
View file

@ -33,12 +33,17 @@
#include <config.h>
#include <command.h>
#include "../fs/ubifs/ubifs.h"
static int ubifs_initialized;
static int ubifs_mounted;
extern struct super_block *ubifs_sb;
/* Prototypes */
int ubifs_init(void);
int ubifs_mount(char *vol_name);
void ubifs_umount(struct ubifs_info *c);
int ubifs_ls(char *dir_name);
int ubifs_load(char *filename, u32 addr, u32 size);
@ -67,13 +72,47 @@ int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
int ubifs_is_mounted(void)
{
return ubifs_mounted;
}
void cmd_ubifs_umount(void)
{
if (ubifs_sb) {
printf("Unmounting UBIFS volume %s!\n",
((struct ubifs_info *)(ubifs_sb->s_fs_info))->vi.name);
ubifs_umount(ubifs_sb->s_fs_info);
}
ubifs_sb = NULL;
ubifs_mounted = 0;
ubifs_initialized = 0;
}
int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 1)
return cmd_usage(cmdtp);
if (ubifs_initialized == 0) {
printf("No UBIFS volume mounted!\n");
return -1;
}
cmd_ubifs_umount();
return 0;
}
int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *filename = "/";
int ret;
if (!ubifs_mounted) {
printf("UBIFS not mounted, use ubifs mount to mount volume first!\n");
printf("UBIFS not mounted, use ubifsmount to mount volume first!\n");
return -1;
}
@ -131,6 +170,12 @@ U_BOOT_CMD(
" - mount 'volume-name' volume"
);
U_BOOT_CMD(
ubifsumount, 1, 0, do_ubifs_umount,
"unmount UBIFS volume",
" - unmount current volume"
);
U_BOOT_CMD(
ubifsls, 2, 0, do_ubifs_ls,
"list files in a directory",

2
common/env_nand.c
View file

@ -297,7 +297,7 @@ int readenv(size_t offset, u_char * buf)
offset += blocksize;
} else {
char_ptr = &buf[amount_loaded];
if (nand_read(&nand_info[0], offset, &len, char_ptr))
if (nand_read_skip_bad(&nand_info[0], offset, &len, char_ptr))
return 1;
offset += blocksize;
amount_loaded += len;

27
common/hwconfig.c
View file

@ -68,14 +68,14 @@ next:
return NULL;
}
const char *cpu_hwconfig __attribute__((weak));
const char *board_hwconfig __attribute__((weak));
const char cpu_hwconfig[] __attribute__((weak)) = "";
const char board_hwconfig[] __attribute__((weak)) = "";
#define HWCONFIG_PRE_RELOC_BUF_SIZE 128
static const char *__hwconfig(const char *opt, size_t *arglen)
{
const char *env_hwconfig = NULL;
const char *env_hwconfig = NULL, *ret;
char buf[HWCONFIG_PRE_RELOC_BUF_SIZE];
if (gd->flags & GD_FLG_ENV_READY) {
@ -92,19 +92,20 @@ static const char *__hwconfig(const char *opt, size_t *arglen)
env_hwconfig = buf;
}
if (env_hwconfig)
return hwconfig_parse(env_hwconfig, strlen(env_hwconfig),
if (env_hwconfig) {
ret = hwconfig_parse(env_hwconfig, strlen(env_hwconfig),
opt, ";", ':', arglen);
if (ret)
return ret;
}
if (board_hwconfig)
return hwconfig_parse(board_hwconfig, strlen(board_hwconfig),
opt, ";", ':', arglen);
ret = hwconfig_parse(board_hwconfig, strlen(board_hwconfig),
opt, ";", ':', arglen);
if (ret)
return ret;
if (cpu_hwconfig)
return hwconfig_parse(cpu_hwconfig, strlen(cpu_hwconfig),
opt, ";", ':', arglen);
return NULL;
return hwconfig_parse(cpu_hwconfig, strlen(cpu_hwconfig),
opt, ";", ':', arglen);
}
/*

8
drivers/mmc/fsl_esdhc.c
View file

@ -384,10 +384,6 @@ static int esdhc_init(struct mmc *mmc)
int ret = 0;
u8 card_absent;
/* Enable cache snooping */
if (cfg && !cfg->no_snoop)
esdhc_write32(&regs->scr, 0x00000040);
/* Reset the entire host controller */
esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
@ -395,6 +391,10 @@ static int esdhc_init(struct mmc *mmc)
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000);
/* Enable cache snooping */
if (cfg && !cfg->no_snoop)
esdhc_write32(&regs->scr, 0x00000040);
esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
/* Set the initial clock speed */

1
drivers/mmc/gen_atmel_mci.c
View file

@ -308,6 +308,7 @@ static int mci_init(struct mmc *mmc)
writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
/* Initial Time-outs */
writel(0x5f, &mci->dtor);

2
drivers/mtd/nand/fsl_upm.c
View file

@ -21,6 +21,7 @@
static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
{
clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
(void)in_be32(upm->mxmr);
}
static void fsl_upm_end_pattern(struct fsl_upm *upm)
@ -35,6 +36,7 @@ static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
void __iomem *io_addr, u32 mar)
{
out_be32(upm->mar, mar);
(void)in_be32(upm->mar);
switch (width) {
case 8:
out_8(io_addr, 0x0);

12
drivers/mtd/nand/s3c2410_nand.c
View file

@ -133,9 +133,15 @@ int board_nand_init(struct nand_chip *nand)
writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
/* initialize hardware */
twrph0 = 3;
twrph1 = 0;
tacls = 0;
#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
tacls = CONFIG_S3C24XX_TACLS;
twrph0 = CONFIG_S3C24XX_TWRPH0;
twrph1 = CONFIG_S3C24XX_TWRPH1;
#else
tacls = 4;
twrph0 = 8;
twrph1 = 8;
#endif
cfg = S3C2410_NFCONF_EN;
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);

17
drivers/net/fec_mxc.c
View file

@ -312,21 +312,8 @@ static void fec_rbd_clean(int last, struct fec_bd *pRbd)
static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
{
/*
* The MX27 can store the mac address in internal eeprom
* This mechanism is not supported now by MX51 or MX25
*/
#if defined(CONFIG_MX51) || defined(CONFIG_MX25)
return -1;
#else
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
int i;
for (i = 0; i < 6; i++)
mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);
imx_get_mac_from_fuse(mac);
return !is_valid_ether_addr(mac);
#endif
}
static int fec_set_hwaddr(struct eth_device *dev)
@ -754,7 +741,7 @@ static int fec_probe(bd_t *bd)
eth_register(edev);
if (fec_get_hwaddr(edev, ethaddr) == 0) {
printf("got MAC address from EEPROM: %pM\n", ethaddr);
printf("got MAC address from fuse: %pM\n", ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
}

9
drivers/net/tsec.c
View file

@ -5,7 +5,7 @@
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* Copyright 2004-2009 Freescale Semiconductor, Inc.
* Copyright 2004-2010 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
@ -292,13 +292,12 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
#ifndef CONFIG_TSEC_TBICR_SETTINGS
#define TBICR_SETTINGS ( \
#define CONFIG_TSEC_TBICR_SETTINGS ( \
TBICR_PHY_RESET \
| TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
#else
#define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS
#endif /* CONFIG_TSEC_TBICR_SETTINGS */
/* Configure the TBI for SGMII operation */
@ -311,7 +310,7 @@ static void tsec_configure_serdes(struct tsec_private *priv)
tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
TBICON_CLK_SELECT);
tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
TBICR_SETTINGS);
CONFIG_TSEC_TBICR_SETTINGS);
}
/* Discover which PHY is attached to the device, and configure it

1
drivers/video/Makefile
View file

@ -28,6 +28,7 @@ LIB := $(obj)libvideo.o
COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o
COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o

0
board/freescale/common/fsl_diu_fb.c → drivers/video/fsl_diu_fb.c
View file

2
fs/ubifs/super.c
View file

@ -824,7 +824,7 @@ out_free:
* through mounting (error path cleanup function). So it has to make sure the
* resource was actually allocated before freeing it.
*/
static void ubifs_umount(struct ubifs_info *c)
void ubifs_umount(struct ubifs_info *c)
{
dbg_gen("un-mounting UBI device %d, volume %d", c->vi.ubi_num,
c->vi.vol_id);

73
fs/ubifs/ubifs.c
View file

@ -3,7 +3,7 @@
*
* Copyright (C) 2006-2008 Nokia Corporation.
*
* (C) Copyright 2008-2009
* (C) Copyright 2008-2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or modify it
@ -384,6 +384,7 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename)
unsigned long root_inum = 1;
unsigned long inum;
int symlink_count = 0; /* Don't allow symlink recursion */
char link_name[64];
strcpy(fpath, filename);
@ -420,7 +421,6 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename)
ui = ubifs_inode(inode);
if ((inode->i_mode & S_IFMT) == S_IFLNK) {
char link_name[64];
char buf[128];
/* We have some sort of symlink recursion, bail out */
@ -567,7 +567,8 @@ dump:
return -EINVAL;
}
static int do_readpage(struct ubifs_info *c, struct inode *inode, struct page *page)
static int do_readpage(struct ubifs_info *c, struct inode *inode,
struct page *page, int last_block_size)
{
void *addr;
int err = 0, i;
@ -601,17 +602,54 @@ static int do_readpage(struct ubifs_info *c, struct inode *inode, struct page *p
err = -ENOENT;
memset(addr, 0, UBIFS_BLOCK_SIZE);
} else {
ret = read_block(inode, addr, block, dn);
if (ret) {
err = ret;
if (err != -ENOENT)
break;
} else if (block + 1 == beyond) {
int dlen = le32_to_cpu(dn->size);
int ilen = i_size & (UBIFS_BLOCK_SIZE - 1);
/*
* Reading last block? Make sure to not write beyond
* the requested size in the destination buffer.
*/
if (((block + 1) == beyond) || last_block_size) {
void *buff;
int dlen;
if (ilen && ilen < dlen)
memset(addr + ilen, 0, dlen - ilen);
/*
* We need to buffer the data locally for the
* last block. This is to not pad the
* destination area to a multiple of
* UBIFS_BLOCK_SIZE.
*/
buff = malloc(UBIFS_BLOCK_SIZE);
if (!buff) {
printf("%s: Error, malloc fails!\n",
__func__);
err = -ENOMEM;
break;
}
/* Read block-size into temp buffer */
ret = read_block(inode, buff, block, dn);
if (ret) {
err = ret;
if (err != -ENOENT) {
free(buff);
break;
}
}
if (last_block_size)
dlen = last_block_size;
else
dlen = le32_to_cpu(dn->size);
/* Now copy required size back to dest */
memcpy(addr, buff, dlen);
free(buff);
} else {
ret = read_block(inode, addr, block, dn);
if (ret) {
err = ret;
if (err != -ENOENT)
break;
}
}
}
if (++i >= UBIFS_BLOCKS_PER_PAGE)
@ -649,6 +687,7 @@ int ubifs_load(char *filename, u32 addr, u32 size)
int err = 0;
int i;
int count;
int last_block_size = 0;
c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY);
/* ubifs_findfile will resolve symlinks, so we know that we get
@ -684,7 +723,13 @@ int ubifs_load(char *filename, u32 addr, u32 size)
page.index = 0;
page.inode = inode;
for (i = 0; i < count; i++) {
err = do_readpage(c, inode, &page);
/*
* Make sure to not read beyond the requested size
*/
if (((i + 1) == count) && (size < inode->i_size))
last_block_size = size - (i * PAGE_SIZE);
err = do_readpage(c, inode, &page, last_block_size);
if (err)
break;

4
include/configs/MPC8360EMDS.h
View file

@ -296,13 +296,13 @@
/*
* CS4 on Local Bus, to PIB
*/
#define CONFIG_SYS_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
#define CONFIG_SYS_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* CS5 on Local Bus, to PIB
*/
#define CONFIG_SYS_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
#define CONFIG_SYS_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*

5
include/configs/MPC8536DS.h
View file

@ -242,9 +242,10 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif

3
include/configs/MPC8569MDS.h
View file

@ -203,8 +203,9 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif

1
include/configs/MPC8572DS.h
View file

@ -202,6 +202,7 @@
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT

13
include/configs/P1_P2_RDB.h
View file

@ -201,9 +201,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
@ -436,14 +437,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
/* TBI PHY configuration for SGMII mode */
#define CONFIG_TSEC_TBICR_SETTINGS ( \
TBICR_PHY_RESET \
| TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
#endif /* CONFIG_TSEC_ENET */
/*

7
include/configs/am3517_evm.h
View file

@ -163,6 +163,7 @@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
* Board NAND Info.
*/
@ -330,4 +331,10 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

1
include/configs/aria.h
View file

@ -49,7 +49,6 @@
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
#define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */
#define CONFIG_SYS_TEXT_BASE 0xFFF00000

18
include/configs/at91rm9200ek.h
View file

@ -32,6 +32,20 @@
#include <asm/sizes.h>
/*
* set some initial configurations depending on configure target
*
* at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0
* at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
* initialisation was done by some preloader
*/
#ifdef CONFIG_RAMBOOT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0x20100000
#else
#define CONFIG_SYS_TEXT_BASE 0x10000000
#endif
/*
* AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
* AT91C_MAIN_CLOCK is the frequency of PLLA output
@ -57,6 +71,8 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_AT91FAMILY
/*
* Memory Configuration
*/
@ -90,7 +106,7 @@
#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
#define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */

2
include/configs/atngw100.h
View file

@ -104,8 +104,6 @@
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_DOS_PARTITION 1
/*
* Command line configuration.
*/

19
include/configs/davinci_dvevm.h
View file

@ -50,7 +50,7 @@
/*=======*/
#define DV_EVM
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NOR
#define CONFIG_SYS_USE_NAND
#define CONFIG_DISPLAY_CPUINFO
/*===================*/
/* SoC Configuration */
@ -78,6 +78,7 @@
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
/*====================*/
/* Serial Driver info */
@ -228,11 +229,13 @@
#define CONFIG_PREBOOT "usb start"
#endif
#endif
/*=======================*/
/* KGDB support (if any) */
/*=======================*/
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

1
include/configs/igep0030.h
View file

@ -110,6 +110,7 @@
#define CONFIG_MTD_DEVICE
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* nfs */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_IMLS /* List all found images */

2
include/configs/mimc200.h
View file

@ -109,8 +109,6 @@
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_DOS_PARTITION 1
/*
* Command line configuration.
*/

7
include/configs/mx51evk.h
View file

@ -216,8 +216,9 @@
*/
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif

6
include/configs/omap3_evm.h
View file

@ -330,7 +330,11 @@ extern unsigned int boot_flash_type;
* Support for relocation
*/
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* Define the board revision statically

6
include/configs/omap3_sdp3430.h
View file

@ -309,6 +309,12 @@
#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* SDRAM Memory Map
*/

6
include/configs/omap3_zoom1.h
View file

@ -236,6 +236,12 @@
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).

6
include/configs/omap3_zoom2.h
View file

@ -188,6 +188,12 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* Miscellaneous configurable options
*/

1
include/configs/omap4_sdp4430.h
View file

@ -140,6 +140,7 @@
/* Disabled commands */
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMLS /* List all found images */

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