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https://github.com/AsahiLinux/u-boot
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x86: Add processor flags header from linux
This commit is contained in:
Graeme Russ
parent
c53fd2bb6d
commit
0c24c9cc71
6 changed files with 121 additions and 10 deletions
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@ -36,6 +36,7 @@
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/processor-flags.h>
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#include <asm/interrupt.h>
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/* Constructor for a conventional segment GDT (or LDT) entry */
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@ -88,12 +89,16 @@ static void reload_gdt(void)
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int cpu_init_f(void)
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{
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const u32 em_rst = ~X86_CR0_EM;
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const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
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/* initialize FPU, reset EM, set MP and NE */
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asm ("fninit\n" \
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"movl %cr0, %eax\n" \
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"andl $~0x4, %eax\n" \
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"orl $0x22, %eax\n" \
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"movl %eax, %cr0\n" );
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"movl %%cr0, %%eax\n" \
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"andl %0, %%eax\n" \
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"orl %1, %%eax\n" \
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"movl %%eax, %%cr0\n" \
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: : "i" (em_rst), "i" (mp_ne_set) : "eax");
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return 0;
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}
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@ -30,6 +30,7 @@
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#include <common.h>
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#include <asm/interrupt.h>
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#include <asm/io.h>
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#include <asm/processor-flags.h>
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#define DECLARE_INTERRUPT(x) \
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".globl irq_"#x"\n" \
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@ -237,7 +238,7 @@ int disable_interrupts(void)
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asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
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return (flags&0x200); /* IE flags is bit 9 */
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return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */
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}
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/* IRQ Low-Level Service Routine */
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@ -26,6 +26,7 @@
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor-flags.h>
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#include <asm/ic/sc520.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -41,6 +42,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
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void init_sc520(void)
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{
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const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
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/*
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* Set the UARTxCTL register at it's slower,
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* baud clock giving us a 1.8432 MHz reference
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@ -84,8 +87,8 @@ void init_sc520(void)
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/* turn on the cache and disable write through */
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asm("movl %%cr0, %%eax\n"
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"andl $0x9fffffff, %%eax\n"
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"movl %%eax, %%cr0\n" : : : "eax");
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"andl %0, %%eax\n"
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"movl %%eax, %%cr0\n" : : "i" (nw_cd_rst) : "eax");
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}
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unsigned long init_sc520_dram(void)
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@ -26,6 +26,7 @@
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#include <config.h>
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#include <version.h>
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#include <asm/global_data.h>
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#include <asm/processor-flags.h>
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.section .text
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@ -46,7 +47,7 @@ _i386boot_start:
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/* Turn of cache (this might require a 486-class CPU) */
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movl %cr0, %eax
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orl $0x60000000, %eax
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orl $(X86_CR0_NW | X86_CR0_CD), %eax
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movl %eax, %cr0
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wbinvd
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@ -23,6 +23,7 @@
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*/
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#include <asm/global_data.h>
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#include <asm/processor-flags.h>
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#define BOOT_SEG 0xffff0000 /* linear segment of boot code */
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#define a32 .byte 0x67;
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@ -45,7 +46,7 @@ board_init16_ret:
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/* Turn of cache (this might require a 486-class CPU) */
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movl %cr0, %eax
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orl $0x60000000, %eax
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orl $(X86_CR0_NW & X86_CR0_CD), %eax
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movl %eax, %cr0
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wbinvd
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@ -55,7 +56,7 @@ o32 cs lgdt gdt_ptr
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/* Now, we enter protected mode */
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movl %cr0, %eax
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orl $1, %eax
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orl $X86_CR0_PE, %eax
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movl %eax, %cr0
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/* Flush the prefetch queue */
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100
arch/i386/include/asm/processor-flags.h
Normal file
100
arch/i386/include/asm/processor-flags.h
Normal file
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@ -0,0 +1,100 @@
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#ifndef _ASM_X86_PROCESSOR_FLAGS_H
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#define _ASM_X86_PROCESSOR_FLAGS_H
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/* Various flags defined: can be included from assembler. */
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/*
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* EFLAGS bits
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*/
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#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
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#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
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#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
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#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
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#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
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#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
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#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
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#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
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#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
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#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
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#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
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#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
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#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
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#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
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#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
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#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
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#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
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/*
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* Basic CPU control in CR0
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*/
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#define X86_CR0_PE 0x00000001 /* Protection Enable */
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#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */
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#define X86_CR0_EM 0x00000004 /* Emulation */
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#define X86_CR0_TS 0x00000008 /* Task Switched */
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#define X86_CR0_ET 0x00000010 /* Extension Type */
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#define X86_CR0_NE 0x00000020 /* Numeric Error */
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#define X86_CR0_WP 0x00010000 /* Write Protect */
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#define X86_CR0_AM 0x00040000 /* Alignment Mask */
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#define X86_CR0_NW 0x20000000 /* Not Write-through */
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#define X86_CR0_CD 0x40000000 /* Cache Disable */
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#define X86_CR0_PG 0x80000000 /* Paging */
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/*
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* Paging options in CR3
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*/
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#define X86_CR3_PWT 0x00000008 /* Page Write Through */
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#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */
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/*
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* Intel CPU features in CR4
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*/
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#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */
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#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */
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#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */
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#define X86_CR4_DE 0x00000008 /* enable debugging extensions */
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#define X86_CR4_PSE 0x00000010 /* enable page size extensions */
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#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
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#define X86_CR4_MCE 0x00000040 /* Machine check enable */
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#define X86_CR4_PGE 0x00000080 /* enable global pages */
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#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */
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#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */
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#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
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#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */
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#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
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/*
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* x86-64 Task Priority Register, CR8
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*/
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#define X86_CR8_TPR 0x0000000F /* task priority register */
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/*
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* AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
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*/
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/*
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* NSC/Cyrix CPU configuration register indexes
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*/
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#define CX86_PCR0 0x20
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#define CX86_GCR 0xb8
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#define CX86_CCR0 0xc0
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#define CX86_CCR1 0xc1
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#define CX86_CCR2 0xc2
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#define CX86_CCR3 0xc3
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#define CX86_CCR4 0xe8
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#define CX86_CCR5 0xe9
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#define CX86_CCR6 0xea
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#define CX86_CCR7 0xeb
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#define CX86_PCR1 0xf0
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#define CX86_DIR0 0xfe
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#define CX86_DIR1 0xff
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#define CX86_ARR_BASE 0xc4
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#define CX86_RCR_BASE 0xdc
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#ifdef __KERNEL__
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#ifdef CONFIG_VM86
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#define X86_VM_MASK X86_EFLAGS_VM
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#else
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#define X86_VM_MASK 0 /* No VM86 support */
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#endif
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#endif
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#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
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