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arm: Add Support for Marvell ARMADA 100 Familiy SoCs
ARMADA 100 Family processors are highly integrated SoCs based on Sheeva_88SV331x-v5 PJ1 cpu core. Ref: http://www.marvell.com/products/processors/applications/armada_100 SoC versions Supported: 1) ARMADA168/88AP168 (Aspen P) 2) ARMADA166/88AP166 (Aspen M) 3) ARMADA162/88AP162 (Aspen L) Contributors: Eric Miao <eric.y.miao@gmail.com> Lei Wen <leiwen@marvell.com> Mahavir Jain <mjain@marvell.com> Signed-off-by: Mahavir Jain <mjain@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
This commit is contained in:
Prafulla Wadaskar
Wolfgang Denk
parent
006915fbb0
commit
6c08d5dcf8
6 changed files with 650 additions and 0 deletions
46
arch/arm/cpu/arm926ejs/armada100/Makefile
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46
arch/arm/cpu/arm926ejs/armada100/Makefile
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@ -0,0 +1,46 @@
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#
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# (C) Copyright 2010
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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COBJS-y = cpu.o timer.o dram.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
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all: $(obj).depend $(LIB)
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$(LIB): $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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92
arch/arm/cpu/arm926ejs/armada100/cpu.c
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92
arch/arm/cpu/arm926ejs/armada100/cpu.c
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@ -0,0 +1,92 @@
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/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/arch/armada100.h>
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#include <asm/io.h>
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#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
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#define SET_MRVL_ID (1<<8)
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#define L2C_RAM_SEL (1<<4)
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int arch_cpu_init(void)
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{
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u32 val;
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struct armd1cpu_registers *cpuregs =
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(struct armd1cpu_registers *) ARMD1_CPU_BASE;
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struct armd1apb1_registers *apb1clkres =
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(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
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struct armd1mpmu_registers *mpmu =
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(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
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/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
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val = readl(&cpuregs->cpu_conf);
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val = val | SET_MRVL_ID;
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writel(val, &cpuregs->cpu_conf);
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/* Enable Clocks for all hardware units */
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writel(0xFFFFFFFF, &mpmu->acgr);
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/* Turn on AIB and AIB-APB Functional clock */
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writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
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/* ensure L2 cache is not mapped as SRAM */
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val = readl(&cpuregs->cpu_conf);
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val = val & ~(L2C_RAM_SEL);
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writel(val, &cpuregs->cpu_conf);
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/* Enable GPIO clock */
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writel(APBC_APBCLK, &apb1clkres->gpio);
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/*
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* Enable Functional and APB clock at 14.7456MHz
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* for configured UART console
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*/
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#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
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writel(UARTCLK14745KHZ, &apb1clkres->uart3);
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#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
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writel(UARTCLK14745KHZ, &apb1clkres->uart2);
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#else
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writel(UARTCLK14745KHZ, &apb1clkres->uart1);
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#endif
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icache_enable();
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return 0;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u32 id;
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struct armd1cpu_registers *cpuregs =
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(struct armd1cpu_registers *) ARMD1_CPU_BASE;
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id = readl(&cpuregs->chip_id);
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printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
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return 0;
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}
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#endif
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131
arch/arm/cpu/arm926ejs/armada100/dram.c
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131
arch/arm/cpu/arm926ejs/armada100/dram.c
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@ -0,0 +1,131 @@
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/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/arch/armada100.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* ARMADA100 DRAM controller supports upto 8 banks
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* for chip select 0 and 1
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*/
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/*
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* DDR Memory Control Registers
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* Refer Datasheet Appendix A.17
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*/
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struct armd1ddr_map_registers {
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u32 cs; /* Memory Address Map Register -CS */
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u32 pad[3];
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};
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struct armd1ddr_registers {
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u8 pad[0x100 - 0x000];
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struct armd1ddr_map_registers mmap[2];
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};
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/*
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* armd1_sdram_base - reads SDRAM Base Address Register
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*/
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u32 armd1_sdram_base(int chip_sel)
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{
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struct armd1ddr_registers *ddr_regs =
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(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
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u32 result = 0;
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u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
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if (!CS_valid)
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return 0;
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result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
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return result;
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}
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/*
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* armd1_sdram_size - reads SDRAM size
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*/
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u32 armd1_sdram_size(int chip_sel)
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{
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struct armd1ddr_registers *ddr_regs =
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(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
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u32 result = 0;
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u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
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if (!CS_valid)
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return 0;
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result = readl(&ddr_regs->mmap[chip_sel].cs);
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result = (result >> 16) & 0xF;
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if (result < 0x7) {
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printf("Unknown DRAM Size\n");
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return -1;
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} else {
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return ((0x8 << (result - 0x7)) * 1024 * 1024);
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}
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}
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#ifndef CONFIG_SYS_BOARD_DRAM_INIT
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int dram_init(void)
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{
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int i;
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gd->ram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = armd1_sdram_base(i);
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gd->bd->bi_dram[i].size = armd1_sdram_size(i);
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/*
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* It is assumed that all memory banks are consecutive
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* and without gaps.
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* If the gap is found, ram_size will be reported for
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* consecutive memory only
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*/
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if (gd->bd->bi_dram[i].start != gd->ram_size)
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break;
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gd->ram_size += gd->bd->bi_dram[i].size;
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}
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for (; i < CONFIG_NR_DRAM_BANKS; i++) {
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/* If above loop terminated prematurely, we need to set
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* remaining banks' start address & size as 0. Otherwise other
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* u-boot functions and Linux kernel gets wrong values which
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* could result in crash */
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gd->bd->bi_dram[i].start = 0;
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gd->bd->bi_dram[i].size = 0;
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}
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return 0;
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}
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/*
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* If this function is not defined here,
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* board.c alters dram bank zero configuration defined above.
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*/
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void dram_init_banksize(void)
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{
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dram_init();
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}
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#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
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207
arch/arm/cpu/arm926ejs/armada100/timer.c
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207
arch/arm/cpu/arm926ejs/armada100/timer.c
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/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/arch/armada100.h>
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/*
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* Timer registers
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* Refer Section A.6 in Datasheet
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*/
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struct armd1tmr_registers {
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u32 clk_ctrl; /* Timer clk control reg */
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u32 match[9]; /* Timer match registers */
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u32 count[3]; /* Timer count registers */
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u32 status[3];
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u32 ie[3];
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u32 preload[3]; /* Timer preload value */
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u32 preload_ctrl[3];
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u32 wdt_match_en;
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u32 wdt_match_r;
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u32 wdt_val;
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u32 wdt_sts;
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u32 icr[3];
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u32 wdt_icr;
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u32 cer; /* Timer count enable reg */
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u32 cmr;
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u32 ilr[3];
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u32 wcr;
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u32 wfar;
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u32 wsar;
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u32 cvwr;
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};
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#define TIMER 0 /* Use TIMER 0 */
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/* Each timer has 3 match registers */
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#define MATCH_CMP(x) ((3 * TIMER) + x)
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#define TIMER_LOAD_VAL 0xffffffff
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#define COUNT_RD_REQ 0x1
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DECLARE_GLOBAL_DATA_PTR;
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/* Using gd->tbu from timestamp and gd->tbl for lastdec */
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/* For preventing risk of instability in reading counter value,
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* first set read request to register cvwr and then read same
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* register after it captures counter value.
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*/
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ulong read_timer(void)
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{
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struct armd1tmr_registers *armd1timers =
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(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
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volatile int loop=100;
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writel(COUNT_RD_REQ, &armd1timers->cvwr);
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while (loop--);
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return(readl(&armd1timers->cvwr));
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}
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void reset_timer_masked(void)
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{
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/* reset time */
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gd->tbl = read_timer();
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gd->tbu = 0;
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}
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ulong get_timer_masked(void)
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{
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ulong now = read_timer();
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if (now >= gd->tbl) {
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/* normal mode */
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gd->tbu += now - gd->tbl;
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} else {
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/* we have an overflow ... */
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gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
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}
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gd->tbl = now;
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return gd->tbu;
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}
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer(ulong base)
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{
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return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
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base);
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}
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void set_timer(ulong t)
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{
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gd->tbu = t;
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}
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void __udelay(unsigned long usec)
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{
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ulong delayticks;
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ulong endtime;
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delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
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endtime = get_timer_masked() + delayticks;
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while (get_timer_masked() < endtime);
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}
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/*
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* init the Timer
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*/
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int timer_init(void)
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{
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struct armd1apb1_registers *apb1clkres =
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(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
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struct armd1tmr_registers *armd1timers =
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(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
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/* Enable Timer clock at 3.25 MHZ */
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writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
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/* load value into timer */
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writel(0x0, &armd1timers->clk_ctrl);
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/* Use Timer 0 Match Resiger 0 */
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writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
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/* Preload value is 0 */
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writel(0x0, &armd1timers->preload[TIMER]);
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/* Enable match comparator 0 for Timer 0 */
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writel(0x1, &armd1timers->preload_ctrl[TIMER]);
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/* Enable timer 0 */
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writel(0x1, &armd1timers->cer);
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/* init the gd->tbu and gd->tbl value */
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reset_timer_masked();
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return 0;
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}
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#define MPMU_APRR_WDTR (1<<4)
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#define TMR_WFAR 0xbaba /* WDT Register First key */
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#define TMP_WSAR 0xeb10 /* WDT Register Second key */
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/*
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* This function uses internal Watchdog Timer
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* based reset mechanism.
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* Steps to write watchdog registers (protected access)
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* 1. Write key value to TMR_WFAR reg.
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* 2. Write key value to TMP_WSAR reg.
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* 3. Perform write operation.
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*/
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void reset_cpu (unsigned long ignored)
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{
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struct armd1mpmu_registers *mpmu =
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(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
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struct armd1tmr_registers *armd1timers =
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(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
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u32 val;
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|
||||
/* negate hardware reset to the WDT after system reset */
|
||||
val = readl(&mpmu->aprr);
|
||||
val = val | MPMU_APRR_WDTR;
|
||||
writel(val, &mpmu->aprr);
|
||||
|
||||
/* reset/enable WDT clock */
|
||||
writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
|
||||
readl(&mpmu->wdtpcr);
|
||||
writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
|
||||
readl(&mpmu->wdtpcr);
|
||||
|
||||
/* clear previous WDT status */
|
||||
writel(TMR_WFAR, &armd1timers->wfar);
|
||||
writel(TMP_WSAR, &armd1timers->wsar);
|
||||
writel(0, &armd1timers->wdt_sts);
|
||||
|
||||
/* set match counter */
|
||||
writel(TMR_WFAR, &armd1timers->wfar);
|
||||
writel(TMP_WSAR, &armd1timers->wsar);
|
||||
writel(0xf, &armd1timers->wdt_match_r);
|
||||
|
||||
/* enable WDT reset */
|
||||
writel(TMR_WFAR, &armd1timers->wfar);
|
||||
writel(TMP_WSAR, &armd1timers->wsar);
|
||||
writel(0x3, &armd1timers->wdt_match_en);
|
||||
|
||||
while(1);
|
||||
}
|
||||
121
arch/arm/include/asm/arch-armada100/armada100.h
Normal file
121
arch/arm/include/asm/arch-armada100/armada100.h
Normal file
|
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
* Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_ARMADA100_H
|
||||
#define _ASM_ARCH_ARMADA100_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#if defined (CONFIG_ARMADA100)
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
/* Common APB clock register bit definitions */
|
||||
#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
|
||||
#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
|
||||
#define APBC_RST (1<<2) /* Reset Generation */
|
||||
/* Functional Clock Selection Mask */
|
||||
#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
|
||||
|
||||
/* Register Base Addresses */
|
||||
#define ARMD1_DRAM_BASE 0xB0000000
|
||||
#define ARMD1_TIMER_BASE 0xD4014000
|
||||
#define ARMD1_APBC1_BASE 0xD4015000
|
||||
#define ARMD1_APBC2_BASE 0xD4015800
|
||||
#define ARMD1_UART1_BASE 0xD4017000
|
||||
#define ARMD1_UART2_BASE 0xD4018000
|
||||
#define ARMD1_GPIO_BASE 0xD4019000
|
||||
#define ARMD1_SSP1_BASE 0xD401B000
|
||||
#define ARMD1_SSP2_BASE 0xD401C000
|
||||
#define ARMD1_MFPR_BASE 0xD401E000
|
||||
#define ARMD1_SSP3_BASE 0xD401F000
|
||||
#define ARMD1_SSP4_BASE 0xD4020000
|
||||
#define ARMD1_SSP5_BASE 0xD4021000
|
||||
#define ARMD1_UART3_BASE 0xD4026000
|
||||
#define ARMD1_MPMU_BASE 0xD4050000
|
||||
#define ARMD1_APMU_BASE 0xD4282800
|
||||
#define ARMD1_CPU_BASE 0xD4282C00
|
||||
|
||||
/*
|
||||
* Main Power Management (MPMU) Registers
|
||||
* Refer Datasheet Appendix A.8
|
||||
*/
|
||||
struct armd1mpmu_registers {
|
||||
u8 pad0[0x08 - 0x00];
|
||||
u32 fccr; /*0x0008*/
|
||||
u32 pocr; /*0x000c*/
|
||||
u32 posr; /*0x0010*/
|
||||
u32 succr; /*0x0014*/
|
||||
u8 pad1[0x030 - 0x014 - 4];
|
||||
u32 gpcr; /*0x0030*/
|
||||
u8 pad2[0x200 - 0x030 - 4];
|
||||
u32 wdtpcr; /*0x0200*/
|
||||
u8 pad3[0x1000 - 0x200 - 4];
|
||||
u32 apcr; /*0x1000*/
|
||||
u32 apsr; /*0x1004*/
|
||||
u8 pad4[0x1020 - 0x1004 - 4];
|
||||
u32 aprr; /*0x1020*/
|
||||
u32 acgr; /*0x1024*/
|
||||
u32 arsr; /*0x1028*/
|
||||
};
|
||||
|
||||
/*
|
||||
* APB1 Clock Reset/Control Registers
|
||||
* Refer Datasheet Appendix A.10
|
||||
*/
|
||||
struct armd1apb1_registers {
|
||||
u32 uart1; /*0x000*/
|
||||
u32 uart2; /*0x004*/
|
||||
u32 gpio; /*0x008*/
|
||||
u32 pwm1; /*0x00c*/
|
||||
u32 pwm2; /*0x010*/
|
||||
u32 pwm3; /*0x014*/
|
||||
u32 pwm4; /*0x018*/
|
||||
u8 pad0[0x028 - 0x018 - 4];
|
||||
u32 rtc; /*0x028*/
|
||||
u32 twsi0; /*0x02c*/
|
||||
u32 kpc; /*0x030*/
|
||||
u32 timers; /*0x034*/
|
||||
u8 pad1[0x03c - 0x034 - 4];
|
||||
u32 aib; /*0x03c*/
|
||||
u32 sw_jtag; /*0x040*/
|
||||
u32 timer1; /*0x044*/
|
||||
u32 onewire; /*0x048*/
|
||||
u8 pad2[0x050 - 0x048 - 4];
|
||||
u32 asfar; /*0x050 AIB Secure First Access Reg*/
|
||||
u32 assar; /*0x054 AIB Secure Second Access Reg*/
|
||||
u8 pad3[0x06c - 0x054 - 4];
|
||||
u32 twsi1; /*0x06c*/
|
||||
u32 uart3; /*0x070*/
|
||||
u8 pad4[0x07c - 0x070 - 4];
|
||||
u32 timer2; /*0x07C*/
|
||||
u8 pad5[0x084 - 0x07c - 4];
|
||||
u32 ac97; /*0x084*/
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARMADA100 */
|
||||
#endif /* _ASM_ARCH_ARMADA100_H */
|
||||
53
arch/arm/include/asm/arch-armada100/cpu.h
Normal file
53
arch/arm/include/asm/arch-armada100/cpu.h
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _ARMADA100CPU_H
|
||||
#define _ARMADA100CPU_H
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
/*
|
||||
* CPU Interface Registers
|
||||
* Refer Datasheet Appendix A.2
|
||||
*/
|
||||
struct armd1cpu_registers {
|
||||
u32 chip_id; /* Chip Id Reg */
|
||||
u32 pad;
|
||||
u32 cpu_conf; /* CPU Conf Reg */
|
||||
u32 pad1;
|
||||
u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
|
||||
u32 pad2;
|
||||
u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
|
||||
u32 mcb_conf; /* MCB Conf Reg */
|
||||
u32 sys_boot_ctl; /* Sytem Boot Control */
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions
|
||||
*/
|
||||
u32 armd1_sdram_base(int);
|
||||
u32 armd1_sdram_size(int);
|
||||
|
||||
#endif /* _ARMADA100CPU_H */
|
||||
Loading…
Reference in a new issue