This moves all of the current ARM errata from various header files and in to
Kconfig. This allows for a minor amount of cleanup as we had some instances
where both a general common header file was enabling errata as well as the
board config. We now just select these once at the higher level in Kconfig
Signed-off-by: Tom Rini <trini@konsulko.com>
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.
Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This feature seems to be sometimes misunderstood. The intention is:
[1] Bring the slaves into the U-Boot proper image, not SPL (unless
you have a special reason to do otherwise).
[2] The operation must be done in a board (SoC) specific manner
since how to wake the slaves from the Boot ROM is SoC specific.
[3] The slaves must enter U-Boot proper after U-Boot relocates
itself because the "cpu-release-addr" property points to the
relocated memory area.
[2] is already explained in the help. We can make [1] even clearer
by mentioning "U-Boot proper" instead of "U-Boot". [3] is missing,
so I am adding it to the list. Instead, "before the master CPU
jumps to the kernel" is a matter of course, so removed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to
Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if
rev1.1 silicon used, need to fixup the MSI node to match it.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.
The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.
If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.
Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.
The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
By default the SATA IP on the ls208Xa SoCs does not generating
coherent/snoopable transactions. This patch enable it in the
sata axicc register.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Without a prompt in Kconfig, SECURE_BOOT cannot be selected by
defconfig. The option was dropped unintentionally when defconfig
files were cleaned up. Three targets were impacted
ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT,
ls2080aqds_SECURE_BOOT.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.
This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Clear the content to zero and the ECC error bit of OCRAM1/2.
The OCRAM must be initialized to ZERO by the unit of 8-Byte before
accessing it, or else it will generate ECC error. And the IBR has
accessed the OCRAM before this initialization, so the ECC error
status bit should to be cleared.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It is recommended to set forced-order mode in RNI-6,
RNI-20 for performance optimization in LS2088A.
Both LS2080A, LS2088A families has CONFIG_LS2080A define.
As above update is required only for LS2088A, skip this
for LS2080A SoC family.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Using CONFIG_IS_ENABLED() doesn't work in SPL. This patch replaces the only
occurrence of CONFIG_IS_ENABLED() in start.S to a regular #if defined().
It also adds "&& !defined(CONFIG_SPL_BUILD)" to that #if statement because
the spin-table code can't currently work in SPL, and the spin-table file
isn't even compiled in SPL.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Xilinx ATF extending options for passing images from BL2(FSBL)
to BL31. U-Boot SPL is FSBL replacement that's why it should generate
handoff structure the same. Support only one entry which is U-Boot in
EL2 itself. When FIT image is adopted structure generate should be data
driven.
Currently ATF is placing this structure at the beggining of OCM which is
rewriting early parts of ATF which should be unused at that time.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a string description for SYS_VENDOR to allow configuring boards from
other vendors than just "xilinx".
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.
Signed-off-by: York Sun <york.sun@nxp.com>
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun <york.sun@nxp.com>
For prepending some board specific header area to U-Boot images we
were so far including a header file with a macro definition containing
the actual header specification.
This works fine if there are just a few statements and if there is only
one alternative.
However adding more complex code quickly gets messy with this approach,
so let's just drop that intermediate macro and let the #include actually
insert the code directly.
This converts the callers and the callees, but doesn't change anything
at this point.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The boot0 hook we have so far is applied _after_ the initial branch
to the "reset" entry point. An upcoming change requires even this
branch to be changed, so we apply the hook macro at the earliest
point, and have the branch in the hook file as well.
This is no functional change at this point, just refactoring to simplify
upcoming patches.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The sunxi DRAM setup code needs an sdelay() implementation, which
wasn't defined for armv8 so far.
Shamelessly copy the armv7 version and adjust it to work in AArch64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
For boards that call s_init() when the SPL runs, we are expected to
setup an early stack before calling this C function.
Implement the proper AArch64 version of this based on the ARMv7 code.
This allows sunxi boards to setup the basic peripherals even with a
64-bit SPL.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.
ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and
ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here
in Kconfig too.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
implementation in PPA firmware, but this macro naming too generic, so this
patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
which will be added in following patchs.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
Using alternative bootmode field to support automatic secondary boot
modes. It is purely software setting where SW modes are using free
bootmode combinations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
As PSCI and secure monitor firmware framework are enabled, this patch is
to support loading 32-bit OS in such case. The default target exception
level returned to U-Boot is EL2, so the corresponding work to switch to
AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware
together.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.
The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.
Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
But other new SoCs like LS2088A, LS1088A release secondary
cores one by one.
Update code to release secondary cores based on SoC SVR
Add code to release cores one by one for non LS2080A SoCs
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: remove "inline" from declaration of initiator_type]
Reviewed-by: York Sun <york.sun@nxp.com>
The QorIQ LS2088A SoC is built on layerscape architecture.
It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080 SoC and its personalities does not support TZASC
But other new SoCs like LS2088A, LS1088A supports TZASC
Hence, skip initializing TZASC for Ls2080A based on SVR
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES
are 32-bit regsiters.
So while doing register load-store operations, 32-bit intermediate
register, w0 should be used.
Update x0 register to w0 register type.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround
implementing of erratum reusable for more SoCs.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Highlights this time around:
- x86 efi_loader support
- hello world efi test case
- network device name is now representative
- terminal output reports modes correctly
- fix psci reset for ls1043/ls1046
- fix efi_add_runtime_mmio definition for x86
- efi_loader support for ls2080
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJYLa6qAAoJECszeR4D/txgF+4QAKpHJXY/1V+McEsLga2iwePZ
lZu5NuuLeDA9IMH+ufOOGxDIoc/llZCTsqw5l8Vnkaz0JEH6v9svyEy4zC1Nqtj2
r4pOhGLAyVlGAh4O3hFFi/eHNEDyTrMoPO6JCy8ce+fEGE21VBlWed0+/c/KdV7F
85joTg3X+6htFMkLybzKZS1yiJyoROe7zUZdzPrn4ogwDGbazmYbED+P2u09dDzB
WjlpIbmEDWJEska6Cbgl/ee6dBXSVl8Q/SY3V77T5TB554sZozrKDsNUehiUMEbh
ggCT5VzPhsm4gb/7RBpTqqCabBT5ml8iKfB8Y7fwL43sDiMXJ1LgJyVnHuz65sCS
aPPsPjQujBSiqr+k/571yhgFNLVydrs9IYNumZr+Li4UZCvx3xtCjACJVYkbLUd1
SZrpKts0V45nZcE4IoiwDKOUxavUbLEef2SJTOAOppB3DG9L3O0TWkyH00hTkaxR
oDIVNSZPt9wSd4Q7FQ2MYxQ/sk+B6PrN6Gm/NMSfCnvP8DkyTzHo514qrWnEjlhQ
ndVmyJh3hpipNDfFDeF6r5lLtPkTrzNxOVZcsUGQC5jvrvwLWguD+Kuv9Qq4gSDp
uDawZmRwDGEGpR/yJhqj8r6/e7bZ0fOE6nPqbWLlyF+Oc4yFTz+D2CNPGR4CR0iF
DFGQN/lNkYbu+HfyZOFO
=xmR3
-----END PGP SIGNATURE-----
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2016-11-17
Highlights this time around:
- x86 efi_loader support
- hello world efi test case
- network device name is now representative
- terminal output reports modes correctly
- fix psci reset for ls1043/ls1046
- fix efi_add_runtime_mmio definition for x86
- efi_loader support for ls2080
When implementing efi loader support, we can expose runtime services
for payloads. One such service is CPU reset.
This patch implements RTS CPU reset support for layerscape systems.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
The efi loader code has its own memory map, so it needs to be aware where
the spin tables are located, to ensure that no code writes into those
regions.
Signed-off-by: Alexander Graf <agraf@suse.de>
The NXP ls1043 and ls1046 systems do not (yet) have PSCI enablement
for reset. Don't enable generic PSCI reset code on them.
Signed-off-by: Alexander Graf <agraf@suse.de>
Do not setup use_alt bit which copy alternative boot mode to
boot mode. The reason is that this bit is cleared after POR
but not after any software reset which will cause
that after SW reset bootrom will look for different boot image.
This patch setups alternative boot mode selection (purely SW
handling) and extends code to read this alternative boot mode first and
use it if it is setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Zynq/ZynqMP boot.bin file contains a region for register initialization
data. Filling in proper values in this table can reduce boot time
(e.g. about 50ms faster on QSPI boot) and also reduce the size of
the SPL binary.
The table is a simple text file with register+data on each line. Other
lines are simply skipped. The file can be passed to mkimage using the
"-R" parameter.
It is recommended to add reg init file to board folder.
For example:
CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for EFI apps on aarch64. This includes start-up and relocation
code plus a link script.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: add kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
For 64-bit ARM systems we provide just a timer_read_counter()
implementation and rely on the generic non-uclass get_ticks() function
in lib/time.c to call the former.
However this function is actually not 64-bit safe, as it assumes a
"long" to be 32-bit. Beside the fact that the resulting uint64_t
isn't bigger than "long" on 64-bit architectures and thus combining two
counters makes no sense, we get all kind of weird results when we try
to OR in the high value shifted by _32_ bits.
So let's avoid that function at all and provide a straight forward
get_ticks() implementation for ARMv8, which also is in line with ARMv7.
This fixes occasional immediate time-out expiration issues I see on the
Pine64 board. The root cause of this needs to be investigated, but this
fix looks like the right thing anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Compiler attributes are more commonly __foo style tags rather than big
upper case eye sores like EFI_RUNTIME_TEXT.
Simon Glass felt quite strongly about this, so this patch converts our
existing defines over to more eye friendly ones.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that we have generic PSCI reset and shutdown support in place, we can
advertise those as EFI Run Time Services, allowing efi applications and
OSs to reset and shut down systems.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Most armv8 systems have PSCI support enabled in EL3, either through
ARM Trusted Firmware or other firmware.
On these systems, we do not need to implement system reset manually,
but can instead rely on higher level firmware to deal with it.
The exclude list seems excessive right now, but NXP is working on
providing an in-tree PSCI implementation, so that all NXP systems
can eventually use PSCI as well.
Signed-off-by: Alexander Graf <agraf@suse.de>
[agraf: fix meson]
Reviewed-by: Simon Glass <sjg@chromium.org>
Using PSCI you can not only reset the system, you can also shut it down!
This patch exposes a function to do exactly that to whatever code wants
to make use of it.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
All systems that are running on armv8 are running bare metal with firmware
that implements PSCI running in EL3. That means we don't really need to expose
the hypercall variants of them.
This patch leaves the code in, but makes the code explicit enough to have the
compiler optimize it out. With this we don't need to worry about hvc vs smc
calling convention when calling psci helper functions.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
When enabled sec firmware framework, but lack of definition of
the marco SEC_FIRMWARE_FIT_IMAGE, SEC_FIRMEWARE_FIT_CNF_NAME
and SEC_FIRMWARE_TARGET_EL, there will be some build errors,
so give a default definition.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Move DDR3, DDR4 and realted options to Kconfig and clean up existing
uses.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move these options to Kconfig and create a sub-menu to avoid name
conflict with other architectures.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some config options should not have prompt. They are selected by choosing
target.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
SYSCLK is used as a reference clock for USB. When the USB controller
is used, SYSCLK must meet the additional requirement of 100 MHz.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.
Tested on LS2080ARDB and LS1043ARDB.
Signed-off-by: York Sun <york.sun@nxp.com>
The exact SoC revsion number can be recognized from U-Boot log.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Move this config to Kconfig option and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Calvin Johnson <calvin.johnson@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this option to Kconfig and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
CC: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
It should be enough to call low(5us)->high pulse for all cases
to provide proper reset. There is no need to call high->low->high.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mode pins can be used as output for reset. Xilinx boards are using
this feature as additional way how to reset USB phys and also others
chips on the boards.
Mode1 is used on all these boards for this feature.
Let SPL toggle reset on this pin by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
SPL needs to have bigger stack size because of USB.
Simple malloc needs to be disabled because dfu code requires different
allocation functions. There is no space in OCM that's why random place
in DDR is used.
BOOTD must be disabled because it is causing compilation error.
All variables are disabled and used only variables valid for DFU because
they are simple huge. Including automatic variables added by
CONFIG_ENV_VARS_UBOOT_CONFIG.
Hardcode addresses for u-boot, atf, kernel and dtb
just for SPL DFU code.
Enable SPL DFU for zcu100.
Create new usb_dfu_spl variable just to run Linux kernel loaded in SPL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly. Clearing BSS and calling board_init_r() will be done in
crt0_64.S.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Linux stopped the use of keyword 'boolean' in Kconfig.
Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig:
use bool instead of boolean for type definition attributes")
in Linux Kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We create 2 sets of page tables: One for normal operation, one for
emergency (used while modifying the former).
Because the page tables grow dynamically, we have code that checks
for overflow. Unfortunately we didn't adjust the available space
variable while creating the emergency tables, so potentially someone
might run into an overflow there (not seen in real world yet though!).
Fix it by properly adjusting the size as well as the base offset in
emergency page table creation.
Reported-by: York Sun <york.sun@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
MMU bit in SCTLR needs to be set explicitly after tables are
created. It isn't an issue for EL3 becuase this bit is already
set by early MMU setup. But for other exception levels this
bit was not set.
Signed-off-by: York Sun <york.sun@nxp.com>
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Implement a hook to allow boards to save boot-time CPU state for later
use. When U-Boot is chain-loaded by another bootloader, CPU registers may
contain useful information such as system configuration information. This
feature mirrors the equivalent ARMv7 feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Set the enable-method in the cpu node to PSCI, and create device
node for PSCI, when PSCI was enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. Otherwise, change SMP method to spin-table,
and the device node of PSCI will be removed.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Use the secure firmware framework to integrate FSL PPA into U-Boot.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This framework is introduced for ARMv8 secure monitor mode firmware.
The main functions of the framework are, on EL3, verify the firmware,
load it to the secure memory and jump into it, and while it returned
to U-Boot, do some necessary setups at the 'target exception level'
that is determined by the respective secure firmware.
So far, the framework support only FIT format image, and need to define
the name of which config node should be used in 'configurations' and
the name of property for the raw secure firmware image in that config.
The FIT image should be stored in Byte accessing memory, such as NOR
Flash, or else it should be copied to main memory to use this framework.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has turned into another EL.
Define the function mmu_setup() for fsl-layerscape to cover the weak
one.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Drop platform code to create static MMU tables. Use common framework
to create MMU tables on the run. Tested on LS2080ARDB with secure and
non-secure ram scenarios.
Signed-off-by: York Sun <york.sun@nxp.com>
Introduce virtual and physical addresses in the mapping table. This change
have no impact on existing boards because they all use idential mapping.
Signed-off-by: York Sun <york.sun@nxp.com>
When page tables are created, allow later table to be created on
previous block entry. Splitting block feature is already working
with current code. This patch only rearranges the code order and
adds one condition to call split_block().
Signed-off-by: York Sun <york.sun@nxp.com>
Make setup_pgtages() and get_tcr() available for platform code to
customize MMU tables.
Remove unintentional call of create_table().
Signed-off-by: York Sun <york.sun@nxp.com>
Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.
Signed-off-by: York Sun <york.sun@nxp.com>
There are two enable methods supported by ARM64 Linux; psci and
spin-table. The latter is simpler and helpful for quick SoC bring
up. My main motivation for this patch is to improve the spin-table
support, which allows us to boot an ARMv8 system without the ARM
Trusted Firmware.
Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S
and the spin-table is supported in a really ad-hoc way, and I see
some problems:
- We must hard-code CPU_RELEASE_ADDR so that it matches the
"cpu-release-addr" property in the DT that comes from the
kernel tree.
- The Documentation/arm64/booting.txt in Linux requires that
the release address must be zero-initialized, but it is not
cared by the common code in U-Boot. We must do it in a board
function.
- There is no systematic way to protect the spin-table code from
the kernel. We are supposed to do it in a board specific manner,
but it is difficult to predict where the spin-table code will be
located after the relocation. So, it also makes difficult to
hard-code /memreserve/ in the DT of the kernel.
So, here is a patch to solve those problems; the DT is run-time
modified to reserve the spin-table code (+ cpu-release-addr).
Also, the "cpu-release-addr" property is set to an appropriate
address after the relocation, which means we no longer need the
hard-coded CPU_RELEASE_ADDR.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Upon further review this breaks most other platforms as we need to check
what core we're running on before touching it at all.
This reverts commit d73718f323.
Signed-off-by: Tom Rini <trini@konsulko.com>
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.
So append "A" to SoC names.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.
The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
gic_kick_secondary_cpus can directly return to the caller of
smp_kick_all_cpus. We do not have to use x29 register here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The register CLKCNCSR controls the frequency of all cores in the same
cluster.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This errata a008751 is applied on Soc specific file currently.This will be
moved to a file where all the errata implementation will take place for usb
for fsl. This patch removes the errata workaround from soc specific file
for LS2080.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms,
similar to PPC and ARMv7.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Add initial support for NXP's S32V234 SoC and S32V234EVB board.
The S32V230 family is designed to support computation-intensive applications
for image processing. The S32V234, as part of the S32V230 family, is a
high-performance automotive processor designed to support safe
computation-intensive applications in the area of vision and sensor fusion.
Code originally writen by:
Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>
Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
Environment variable mcinitcmd is defined to initiate MC and DPL
deployment from the location where it is stored (NOR, NAND, SD, SATA,
USB) during booting. If this variable is not defined then macro
MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will
not be applied during U-boot booting.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The SP805-WDT module on LS2080A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0)
require a header before the actual U-Boot binary to both check its
validity and to find other data to load. Sometimes this header may
only be a few bytes of information, and sometimes this might simply
be space that needs to be reserved for a post-processing tool.
Introduce a config option to allow assembler preprocessor commands
to be inserted into the code at the appropriate location; typical
assembler preprocessor commands might be:
.space 1000
.word 0x12345678
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Commit Notes:
Please note that the current code:
start.S (arm64) and
vectors.S (arm)
already jumps over some portion of data already, so this option basically
just increases the size of this region (and the resulting binary).
For use with Allwinner's boot0 blob there is a tool called boot0img[1],
which fills the header to allow booting A64 based boards.
For the Pine64 we need a 1536 byte header (including the branch
instruction) at the moment, so we add this to the defconfig.
[1] https://github.com/apritzel/pine64/tree/master/tools
END
Reviewed-by: Tom Rini <trini@konsulko.com>
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc
Also move README.lsch2 and README.lsch3 in same folder.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
‘get_sys_info’:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable ‘rcw_tmp’ [-Wunused-variable]
u32 rcw_tmp;
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
So Avoid LS1043A specific defines in arch/arm
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.
So put SMMU configuration code under SMMU_BASE.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Since 1e6ad55c05 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cache invalidation. So, it is better to not include "flush" in
this routine name.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.
We do not have to waste x16 register here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add a psci_system_reset() which calls the SYSTEM_RESET function of
PSCI 0.2 and can be used by boards that support it to implement
reset_cpu().
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Support RAM and MMC boot mode in SPL also with SPL_FIT images.
In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
-d bl31.bin atf.ub
cp spl/boot.bin <sdcard fat partition>
cp atf.ub <sdcard fat partition>
cp u-boot.bin <sdcard fat partition>
2) Boot flow with full U-Boot(EL3):
cp spl/boot.bin <sdcard>
cp u-boot*.img <sdcard>
3) emmc boot mode
dd if=/dev/zero of=sd.img bs=1024 count=1024
parted sd.img mktable msdos
parted sd.img mkpart p fat32 0% 100%
kpartx -a sd.img
mkfs.vfat /dev/mapper/loop0p1
mount /dev/mapper/loop0p1 /mnt/
cp spl/boot.bin /mnt
cp u-boot.img /mnt
cp u-boot.bin /mnt
cp atf.ub /mnt
umount /dev/mapper/loop0p1
kpartx -d sd.img
cp sd.img /tftpboot/
and program it via u-boot
tftpb 10000 sd.img
mmcinfo
mmc write 10000 0 $filesize
mmc rescan
mmc part
ls mmc 0
psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.
The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
init_early_memctl_regs() is also be called in board_early_init_f().
So remove the duplicated call in spl code.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the issue about the stack will get corrupted when switching between
the early and final mmu tables is fixed by commit 70e21b064, the
workaround to flush dcache is unnecessary and should be removed.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in
order to update the SEC internal version (aka SEC ERA). This patch
adds the same functionality to the ARMv8 SoCs.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Commit 724219a65f "ARM: always perform per-CPU GIC init" removed some
ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
wrong endif was removed. This patch adds back that missing endif, and
adds a new ifdef to match the endif the now-correctly-terminated block
used to match against. Use "git show -U25 724219a65f55" to see enough
context to make the original issue clear.
In practical terms, this makes no difference to runtime behaviour. The
code that was incorrectly compiled into the binary when ifndef MULTIENTRY
is a no-op for other cases, since branch_if_master evaluates to a hard-
coded jump. The only issues were:
- A few extra instructions were added to the binary.
- The comment on the endif at the very end of the function, indicating
which ifdef it matched, were wrong.
An alternative might be to simply fix the comment on that trailing ifdef,
but that only addresses the second point above, not the first.
Fixes: 724219a65f ("ARM: always perform per-CPU GIC init")
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The current code in ARMv8's lowlevel_init() skips the per-CPU GIC
initialization ifndef CONFIG_ARMV8_MULTIENTRY. However, the per-CPU init
should always occur; it's just the one-time init that should only happen
on the master.
Once this consideration is taken into account, the only difference between
the paths when CONFIG_ARMV8_MULTIENTRY is undefined/defined is the use of
branch_if_slave. Naively, any unified code would need to invoke this
conditionally upon ifdef CONFIG_ARMV8_MULTIENTRY. However, branch_if_slave
already checks CONFIG_ARMV8_MULTIENTRY and does nothing if it isn't
defined, so we don't even need that ifdef at the call site.
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
There are ARM SoCs (such as the BCM2837) do not contain an ARM GIC. Fix
the ARMv8 CPU startup code to compile in this case.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This option enable adding new platform suport just by adding defconfig
and DTS file which will target generic configuration for SoC.
Make no sense to extend Kconfig just create a pointer between DTS and
configuration file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.
For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The qspi_cfg register is set by PBI when booting from QSPI. No need
to changing it again.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock frequency value that's calculated for eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The serdes protocol entries in Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.
WRIOP IP is connected to RNI-20 Node.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
With commit 7985cdf we converted all systems except for the Layerscape
SoCs to the generic descriptor table based page table setup.
On the Layerscape SoCs however, we just provide an empty table stub
and do the setup ourselves. To reserve enough memory for the tables,
we need to override the default counting mechanism which would end up
with an empty table because we have no maps.
Fixes: 7985cdf
Reported-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Our current arm64 exception handlers all panic and never return to the
exception triggering code.
But if any handler wanted to continue execution after fixups, it would
need help from the exception handling code to restore all registers.
This patch implements that help. With this code, exception handlers on
aarch64 can successfully return to the place the exception happened (or
somewhere else if they modify elr).
Signed-off-by: Alexander Graf <agraf@suse.de>
After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.
This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.
We could maybe in the future map U-boot environment variables to EFI variables
here.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Now that we have an easy way to describe memory regions and enable the MMU,
there really shouldn't be anything holding people back from running with
caches enabled on AArch64. To make sure people catch early if they're missing
on the caching fun, give them a compile error.
Signed-off-by: Alexander Graf <agraf@suse.de>
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.
To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.
Signed-off-by: Alexander Graf <agraf@suse.de>
Now that we have nice table driven page table creating code that gives
us everything we need, move to that.
Signed-off-by: Alexander Graf <agraf@suse.de>
The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.
Signed-off-by: Alexander Graf <agraf@suse.de>
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.
So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.
With all this in place, there is very little reason to create your
own page tables in board specific files.
Signed-off-by: Alexander Graf <agraf@suse.de>
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).
In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to reduce the chance for pit falls.
Signed-off-by: Alexander Graf <agraf@suse.de>
To make SPL_OF_CONTROL work on ARM64 SoCs, _image_binary_end must be
defined in the linker script.
LD spl/u-boot-spl
lib/built-in.o: In function `fdtdec_setup':
lib/fdtdec.c:1186: undefined reference to `_image_binary_end'
lib/fdtdec.c:1186: undefined reference to `_image_binary_end'
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2
Note:
CONFIG_SPL_SEPARATE_BSS must be defined as well on ARM64 SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.
833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QSPI and IFC are pin-multiplexed on LS1043A. So we use
ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Remove SECURE_IOU option which is not needed. U-Boot itself can detect
which EL level it is on and based on that use do platform setup.
It also simplify usage because one Kconfig entry is gone.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
LS2080A has support for 8 DPMAC ports out of which
only 5 ports can be used at a time.
Enabling all 8 DPMAC ports of LS2080A personality.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SYSCLK frequency is dependent on on-board switch settings. It may
vary as per requirement. boot-loader is aware of board switch
configurations.
So Fixup Linux device tree from boot-loader.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit adds functions issuing calls to secure monitor or
hypervisore. This allows using services such as Power State
Coordination Interface (PSCI) provided by firmware, e.g. ARM
Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the
calling conventions. The clobber list is "x0..x17" because of
this
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.
In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
Signed-off-by: York Sun <yorksun@freescale.com>
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: York Sun <yorksun@freescale.com>
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
GCC 5.x does not like sizeof(array_variable) and errors out. Change these
calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
SERDES_PRCTL_COUNT (the number of array elements).
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
When one core is released, other cores may not have valid entry
address. Those cores are trapped by "wfe" and wait for further
instruction. When their address is set, they need to be kicked
off by "sev".
Signed-off-by: York Sun <yorksun@freescale.com>
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
The global_data pointer (gd) has been set earlier in crt0_64.S.
So there's no need to assign it again. Remove gdata since it is going
away in U-Boot.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.
Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.
Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Put jump trampoline to TCM at 0 and setup R5 reset address to 0.
Jump trampoline ensures that jump to the right location.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In order for noncached_init() to operate correctly, SoCs must set up a
custom page table with fine-grained (2MiB) sections, which can be
configured from noncached_init().
This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c
by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There
are some other reasons for the duplication there though, such as enabling
icache early, and enabling dcaching earlier with a different configuration.
This change makes mmu_setup() a weak implementation, so that the MMU setup
code can be replaced without having to duplicate other code that calls it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1043ARDB Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G port
* QSGMII with 4x 1G ports
* Two RGMII ports
PCIe:
* PCIe2 (Lanes C) to mini-PCIe slot
* PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Pointer 'reg' returned from call to function 'fdt_getprop' may be
NULL, will be passed to function and may be dereferenced there by
passing argument 1 to function 'of_read_number'. So check pointer
'reg' first.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
>From source code comments:
"x0: 0 flush & invalidate, 1 invalidate only"
Current value 0xffff can make invalidate work, since we only judge whether
input value is 0 or not, see following code:
"
tbz w1, #0, 1f
dc isw, x9
b 2f
1: dc cisw, x9 /* clean & invalidate by set/way */
2: subs x6, x6, #1 /* decrement the way */
"
Later we may add "2 clean only" support. So following the comments,
correct value from 0xffff to 1.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
This patch rewrites MMU translation table entries. To start, all table
entries are written as "invalid", then "device-ngnrnr" and "normal" are
written to the entries to enable access to specific addresses.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Every QSGMII SerDes Protocol usage 4 MACs.
So add/repeat QSGMII information for 4 MACs in dpmac_info strucuture.
Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update 0x33 and 0x35 serdes protocol as per updated SoC document
in array serdes1_cfg_tbl.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds a minimal framework for Dickens CCN-504
interconnect configuration - mainly related to adding Clusters/cores
to snoop/DVM domain and setting QoS of the RN-I ports.
LS2085A platform makes use of these configurations to support
better network data performance and to boot a SMP Linux.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Added usb dwc3 driver support for zynqmp
this also supports the DFU and LTHOR to download
the linux images on to RAM and cen be booted from
those linux images.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Based on the patch:
"armv8: caches: Added routine to set non cacheable region"
(sha1: dad17fd510)
it is necessary to add platform specific hook.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
