Commit graph

8543 commits

Author SHA1 Message Date
Tom Rini
9cddb4fe02 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-12-17 07:52:56 -05:00
Mingkai Hu
0d6faf2bd0 armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:18 +08:00
Mingkai Hu
2949ae5212 armv8/fsl_lsch2: fix DCSR_DCFG address
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:18 +08:00
Tom Rini
35065cdd94 Merge git://git.denx.de/u-boot-rockchip 2015-12-16 14:50:03 -05:00
Tom Rini
e6e3faa5c2 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-12-14 20:27:23 -05:00
Tang Yuantian
989c5f0a8f armv8: Add sata support on Layerscape ARMv8 board
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:35 +08:00
Aneesh Bansal
9711f52806 armv8/ls1043ardb: add SECURE BOOT target for NOR
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:35 +08:00
Aneesh Bansal
70f959c3c4 armv8: Make SEC read/write as snoopable for LS1043
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:34 +08:00
Aneesh Bansal
b644d3e932 armv8: define usec2ticks function
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:34 +08:00
York Sun
c04921414c armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:33 +08:00
York Sun
c107c0c05c armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:33 +08:00
Yao Yuan
000f4e7686 move erratum a008336 and a008514 to soc specific file
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:32 +08:00
Yao Yuan
6c4a1eba3f armv7/fsl-ls102xa: Workaround for DDR erratum A008514
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:32 +08:00
Yao Yuan
0b8bc6314e armv7: ls102xa: cci-400: Enable snoop and DVM message requests.
Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:56:53 +08:00
Tom Rini
312db9f75f armv7: omap-common: Rework SPL board_mmc_init()
Since the changes in a1e56cf the way that we had board_mmc_init()
structured for OMAP parts (so that we always report device 0) are no
longer functional.  For now, make the case of booting from the second
device initialize both devices (we have no devices that only have the
second device as MMC).  A further rework and consolidation of the
functions should be done at a later date.

Tested on Beaglebone Black (SD and eMMC boot).

Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-14 13:42:54 -05:00
huang lin
47b4c228b5 rockchip: Add basic support for kylin board
kylin board use rk3036 SOC, 512M sdram, 8G emmc.
This add some basic files required to allow the board
to output serial message and can run command(mmc info etc).

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-13 20:51:50 -07:00
huang lin
e390680015 rockchip: rk3036 sdram setting cs1_row when rank larger than 1
only rank large than 1, we will use cs1_row, so check rank, when
rank larger than 1, we set the cs1_row.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-13 20:51:44 -07:00
Yao Yuan
762b353546 arm: ls102xa: enable all the snoop signal for masters.
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Yao Yuan
7ba0261810 arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Tom Rini
1a33892164 fsl_*_serdes.c: Modify memset call in serdes_init
GCC 5.x does not like sizeof(array_variable) and errors out.  Change these
calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
SERDES_PRCTL_COUNT (the number of array elements).

Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Shaohui Xie
e994dddbbe armv8/ls1043ardb: Add support for >2GB memory
This patch also expose the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Shengzhou Liu
a46b1852de fsl/ddr: updated ddr errata-A008378 for arm and power SoCs
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
Shengzhou Liu
a07bdad749 fsl/errata: move fsl_errata.h to common directory
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
to make it public for both ARM and POWER SoCs.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix soc.h path in fsl_errata.h]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
Shengzhou Liu
0c028a0328 arm: ls102x: add get_svr and IS_SVR_REV helper
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
angelo@sysam.it
6463fd8f95 m68k: add private libgcc
Add private libgcc

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2015-12-13 20:22:00 -05:00
Jeffy Chen
5cc5b901e6 Revert "rockchip: Add max spl size & spl header configs"
This reverts commit 10b4615f9d7e177ec7fe644fbb2616e0e0956f6e

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-13 17:07:06 -07:00
Egli, Samuel
69b918b65d am33xx,ddr3: fix ddr3 sdram configuration
This patch fixes the DDR3 initialization procedure in
order to comply with DDR3 standard. A 500 us delay is specified
between the DDR3 reset and clock enable signal. Until now,
this delay was not respected. Some DDR3 chips don't bother
but the bigger the RAM becomes the more likely it seems that
this delay is needed. We observed that DRAM > 256 MB from
the manufacturer Samsung have an issue when the specification
is not respected.

Changes:

1) Add a 1 ms wait for L3 timeout error trigger

2) Don't delay DDR3 initialization
Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his
suppresses the initialization of DDR3

Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Reviewed-by: James Doublesin <doublesin@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
2015-12-12 15:56:09 -05:00
Kamil Lulko
665624149a stm32: Convert serial driver to DM
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-12 15:56:08 -05:00
Jens Kuske
bb3654629a sunxi: Fix H3 DRAM DQ read delay configuration
The read delays were set incorrectly, leading to reliability
issues at higher DRAM clock speeds. This commit adjusts this
to match the vendor boot0 behaviour.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:48 +01:00
Olliver Schinagl
23baf66f25 sun4i: clock: Cleanup some whitespace errors
Add some spaces around operators.

Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:48 +01:00
Olliver Schinagl
887e2fd9da sunxi: twi: Enable clocks on sun7i
Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC
but forgot to extend the range check in clock_twi_onoff, resulting in
the clock not getting enabled.

The range-check is not needed at all, since clock_twi_onoff only gets
called with such high indexes when CONFIG_I2C3_ENABLE / CONFIG_I2C4_ENABLE
is set and Kconfig already only allows these on sun6i / sun7i.

This commit removes the range-check all together fixing i2c bus 4 and 5
not working on sun7i.

Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
[hdegoede@redhat.com] Remove range check instead of extending it
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:48 +01:00
Hans de Goede
6edf6a2179 sunxi: select SYS_NS16550 from Kconfig
Select SYS_NS16550 from Kconfig instead of setting it in all our
defconfig files.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:48 +01:00
vishnupatekar
086a2509e9 sunxi: Add suport for A83T HomletV2 Board by Allwinner
Add dts and defconfig for h8homletv2 board.

H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
It has UART, ethernet, USB, HDMI, etc ports on it.
A83T patches are tested on this board.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:47 +01:00
vishnupatekar
333d859dcb sunxi: dts: sun8i: Add Allwinner A83T dtsi
Allwinner A83T is new octa-core cortex-a7 SOC.
This adds the basic dtsi, the clocks differs from
earlier sun8i SOCs.

This is not yet included in kernel.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:47 +01:00
vishnupatekar
81f50d93cb sunxi: Add support for Allwinner A83T DRAM
Add support for A83T dram. Register are different from sun8i A33.
init code is similar to A33 dram init.
hope we'll shift duplicate code in dram_sun8i_*
to dram helper in future.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:47 +01:00
vishnupatekar
f542948b1e sunxi: clk: add basic clocks for A83T
Add basic clocks pll1, pll5, and some default values from allwinner u-boot.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 15:45:47 +01:00
vishnupatekar
95ab8fee8a sunxi: power: enabled support for axp818
Enabled support for AXP818 in SPL and u-boot.
DCDC1, DCDC2, DCDC3 and DCSC5 are enabled.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 11:14:22 +01:00
vishnupatekar
d5a3357f1b sunxi: Add support for UART0 in PB pin group on A83T
On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 11:14:21 +01:00
vishnupatekar
762e24a078 sunxi: Add Machine Support for A83T SOC
Allwinner A83T is octa-core cortex-a7 SOC.
This enables support for A83T.

SMP is not yet supported.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 11:14:21 +01:00
Hans de Goede
cbc1a91afb sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.

Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Chen-Yu Tsai <wens@csie.org>
2015-12-10 11:14:16 +01:00
Bin Meng
789fa275b3 x86: Remove HAVE_ACPI_RESUME
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:56 +08:00
Bin Meng
d475d59020 x86: Remove CPU_INTEL_SOCKET_RPGA989
This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:54 +08:00
Bin Meng
efe2d80cca x86: Clean up ivybridge/chrome Kconfig options
There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:52 +08:00
Bin Meng
9bf76c21e0 x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:50 +08:00
Bin Meng
4932443d26 x86: Move i8254_init() to x86_cpu_init_f()
Right now i8254_init() is called from timer_init() in the tsc timer
driver. But actually i8254 and tsc are completely different things.
Since tsc timer has been converted to driver model, we should find
a new place that is appropriate for U-Boot to call i8254_init(),
which is now x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:44 +08:00
Bin Meng
c5c5c201fe x86: Fix PCI UART compatible string for crownbay and galileo
With recent ns16550 driver changes, we only changed the legacy UART
(at I/O port 0x3f8) compatible string, but forgot to change the PCI
UART compatible string. Now fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:41 +08:00
Alexey Brodkin
8555dd88cd axs10x: add support of generic EHCI USB 2.0 controller
This commit adds support of USB 2.0 storage media on AXS10x boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2015-12-08 17:29:56 +03:00
Peng Fan
0c890879fe imx: mx6: fix reg base address when runtime usage
Should use parenthese to wrap the macro definition, otherwise
we will encounter error like the following:

"
if (base_addr != LCDIF1_BASE_ADDR) {
    puts("Wrong LCD interface!\n");
    return -EINVAL;
}
"

Without this patch, we will always encounter "Wrong LCD interface".

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-12-07 15:03:08 +01:00
Jeroen Hofstee
0ff47e590b imx: mx6: add missing return value
cc: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-12-07 14:59:25 +01:00
Tom Rini
dcf4cb068e Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2015-12-07 08:13:02 -05:00
Michal Simek
d9ae52c8f0 zynq: sdhci: Move driver to DM
Move driver to DM

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:29 +01:00
Michal Simek
400434537b zynq: sdhci: Remove zynq_sdhci_of_init()
Prepare for using DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Michal Simek
769afa54c6 ARM: zynq: Remove unused SERIAL macros for serial_zynq
Remove unused macros when driver was moved to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Michal Simek
6889ca7198 net: gem: Move driver to DM
- Enable DM_ETH by default for Zynq and ZynqMP
- Remove board_eth_init code
- Change miiphy_read function to return value instead of error code
  based on DM requirement
- Do not enable EMIO DT support by default

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-07 10:14:22 +01:00
Marek Vasut
1c75596e68 arm: socfpga: Remove cpu_mmc_init()
This function triggers the registration of the dwmmc driver on SoCFPGA,
but this is not needed in case the driver is correctly probed from DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2015-12-07 00:15:59 +01:00
Stefan Roese
ae9996c806 arm: socfpga: Add SoCFPGA SR1500 board
The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
2015-12-07 00:15:59 +01:00
Tom Rini
75507d5d54 am33xx: Update serial pdata
We now want to make sure that we have the platform data for NS16550 when
we do not have OF_CONTROL set.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-06 16:38:05 -05:00
Simon Glass
878a3ed9ad dm: tegra: Provide serial platform data for SPL
At present an incorrect #if term is preventing this data from being compiled
in. All tegra boards use driver model for serial, so we can just drop this.

Fixes: fde7e18938 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
2015-12-05 18:22:38 -05:00
Stephen Warren
dbe6f1eb93 rpi: get rid of BCM2835_BOARD_REV_* macros
There are two numbering schemes for the RPi revision values; old and new
scheme. The values within each scheme overlap. Hence, it doesn't make
sense to have absolute/global names for the revision IDs. Get rid of the
names and just use the raw revision/type values to set up the array of
per-revision data.

This change makes most sense when coupled with the next change. However,
it's split out so that the mechanical cut/paste is separate from the
logic changes for easier review and problem bisection.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2015-12-05 18:22:35 -05:00
Kamil Lulko
5be9356926 Change e-mail address of Kamil Lulko
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
2015-12-05 18:22:32 -05:00
Tom Rini
eada086f85 arch/arm/cpu/arm920t/ep93xx/led.c: Mark inline functions as static inline
With gcc-5.x we get warning about inline non-static functions referring to
static elements.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-05 18:22:28 -05:00
Mugunthan V N
0935df6539 arm: dts: dra7-evm: add chosen node to specify serial console device
Introduce chosen node and specify uart0 to be used as serial console.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-05 18:22:26 -05:00
Mugunthan V N
85cf0e6299 arm: dts: omap: add reg-shift to serial device tree node
With the commit 'c7b9686d5d48 ("ns16550: unify serial_omap")' all
TI platforms are broken with DM/DT boot as ns16550 driver expects
reg-shift from DT which is not populated for TI platforms.
Earlier it worked as it was hard coded to 2 in serial-omap
driver. So adding the reg-shift to serial nodes for dra7, am4372
and am33xx dtsi files. Tested this patch on am437x-sk-evm,
am437x-gp-evm, am335x-boneblack, dra74x-evm and dra72x-evm.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
2015-12-05 18:22:25 -05:00
Peng Fan
bc3c89b130 common: bootm: check return value of strict_strtoul
Before continue, check return value of strict_strtoul.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-05 18:22:12 -05:00
Tom Rini
9eed48c8be Merge branch 'master' of http://git.denx.de/u-boot-sparc 2015-12-04 17:50:34 -05:00
Tom Rini
a85670e40d Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-12-04 08:21:28 -05:00
Francois Retief
7a4fb11b85 sparc: Remove non-generic board init files: board.c, time.c
Remove the board.c and time.c files and all associated non-generic board
initialization code.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:50 +02:00
Daniel Hellstrom
f376c42f3b sparc: leon3: Added busy wait function, made wait_ms() work when IRQ is disabled
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-12-03 13:15:49 +02:00
Daniel Hellstrom
6c4359aa72 sparc: leon3: Added CPU count and frequency detection.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-12-03 13:15:49 +02:00
Daniel Hellstrom
36594a1dfb sparc: Removed USB stop from linux bootm, arch-independent bootm stop USB
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-12-03 13:15:49 +02:00
Francois Retief
4c547754f5 sparc: Add CONFIG_DISPLAY_BOARDINFO variable to all LEON boards
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:49 +02:00
Francois Retief
1e85ccec53 sparc: Update PROM initialization code for generic board
Fixed the prom_relocate() function in start.S file by reserving memory in
the board_init_f sequence and saving the offset to the __prom_start_reloc
variable. This value is used as the destination when relocating the PROM.

Add the prom_init() function to the end of the board_init_r sequence.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:49 +02:00
Francois Retief
c97088c3cf sparc: Update cpu_init.c to use generic timer infrastructure
Introduce the CONFIG_SYS_TIMER_* macros in include/asm/config.h to make use
of the generic timer infrastructure in lib/time.c.

Created a timer_init() function to initialize the timer hardware and update
the #ifdef in board_init_f to allow this function to be called during the
start-up sequence.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:49 +02:00
Francois Retief
c837901bf1 sparc: leon2: Updates for generic board initialization
Reworked the LEON2 start.S code to call board_init_f function at startup.
Also implemented the relocate_code function in assembly to relocate the
monitor and setup the stack pointer before calling relocated board_init_r.

Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON2 boards.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:49 +02:00
Francois Retief
a62bba15b5 sparc: leon3: Updates for generic board initialization
Reworked the LEON3 start.S code to call board_init_f function at startup.
Also implemented the relocate_code function in assembly to relocate the
monitor and setup the stack pointer before calling relocated board_init_r.

Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON3 boards.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:49 +02:00
Daniel Hellstrom
cb31eaa4b3 sparc: leon3: Clear all unused GPTIMER registers.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-12-03 13:15:49 +02:00
Francois Retief
574be25ea1 sparc: leon3: Move ambapp_bus_init() call to arch_cpu_init() function
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:49 +02:00
Francois Retief
d67269ba70 sparc: leon3: Move snoop detection from startup.S to arch_cpu_init()
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:48 +02:00
Francois Retief
e17c5200c7 sparc: Initial ground work for generic board initialization
Initial ground work in preperation for generic board initialization
code for the SPARC architecture.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:48 +02:00
Francois Retief
a5b629a33e sparc: Fix whitespace in cpu/leon2/cpu_init.c
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:48 +02:00
Francois Retief
c2b37a0d55 sparc: leon3: Updated serial driver to use CONFIG_CONS_INDEX
Updated the LEON3 serial driver to make use of the CONFIG_CONS_INDEX
option to select which serial port the console will use.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:48 +02:00
Daniel Hellstrom
ff0b9b77c2 sparc: Serial baud rate register support multiple buses with different frequency
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-12-03 13:15:48 +02:00
Francois Retief
58e5585625 sparc: leon3: Clear GD_FLAG_SERIAL_READY flag on AMBA failure
Clear the GD_FLG_SERIAL_READY flag on AMBA P&P lookup failure so that the
panic function can use DEBUG_UART driver. drivers/serial/serial.c set this
flag before calling this function, preventing DEBUG_UART code from running.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:48 +02:00
Daniel Hellstrom
f33f888d0e sparc: Added function that checks if IRQ is on or off
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-12-03 13:15:48 +02:00
Francois Retief
be7357a6cc sparc: Remove version_string variable from start.S file
Remove the version_string variable from start.S file. A weak variable
is also set in the cmd_version.c file. No need for architecture override.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:48 +02:00
Francois Retief
52789143a2 sparc: Move SYS_SPARC_NWINDOWS to Kconfig
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:48 +02:00
Sjoerd Simons
d76a0119c7 Revert "rockchip: Reconfigure the malloc based to point to system memory"
This patch was merged shortly before the v2015.10 as a minimal fix for
booting on rockchip. Now that the patch series from Hans to do the
relocation in generic code has been merged it can be dropped.

This reverts commit b1f492ca9e.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Ariel D'Alessandro
cd3187d6b2 rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip Kconfig
Commit 1eb0c03c21 added
SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is
evaluated.

Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h
board configs are now incorrect because CONFIG_SPL_BUILD is enabled so
CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE
instead of SYS_MALLOC_SIMPLE.

This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig
option by default in rockchip-mach.

Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Jeffy Chen
6ae5860942 rockchip: Add max spl size & spl header configs
Our chips may have different max spl size and spl header, so
we need to add configs for that.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
Added $(if...) to tools/Makefile to fix widespread build breakage
Signed-off-by: Simon Glass <sjg@chromium.org>

Series-changes: 8
- Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
- Add $(if...) to tools/Makefile to fix widespread build breakage
2015-12-01 08:07:22 -07:00
huang lin
d8b597823b rockchip: Add basic support for evb-rk3036 board
This add some basic files required to allow the board to dispaly
serial message and can run command(mmc info etc)

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Moved board Kconfig fragment from previous patch into this one to fix
build error:
Signed-off-by: Simon Glass <sjg@chromium.org>

Series-changes: 8
- moved board Kconfig fragment from previous patch into this one
2015-12-01 08:07:22 -07:00
huang lin
be1d5e0388 rockchip: rk3036: Add core Soc start-up code
rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <sjg@chromium.org>

Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
2015-12-01 08:07:22 -07:00
huang lin
53c45f0ca2 rockchip: add rk3036 sdram driver
add rk3036 sdram driver so we can set up sdram in SPL

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
07d8d35a61 rockchip: add early uart driver
add early uart driver so we can print debug message in
SPL stage

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
2863724831 rockchip: mmc: get the fifo mode and fifo depth property from dts
rk3036 mmc do not have internal dma, so we use fifo mode when read
and write data, we get the fifo mode and fifo depth property from
dts, pass to dw_mmc driver.

Signed-off-by: Lin Huang <hl@rock-chips.com>
2015-12-01 08:07:22 -07:00
huang lin
0b374c8dc8 rockchip: rk3036: Add a simple syscon driver
Add a driver that provides access to system controllers

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
2bc00e016e rockchip: rk3036: Add Soc reset driver
We can reset the Soc using some CRU (clock/reset unit) register.
Add support for this.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
c17736c02a rockchip: rk3036: Add header files for GRF
GRF is the gereral register file. Add header files with register definitions.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
3f2ef13924 rockchip: rk3036: Add clock driver
Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
fc0fada094 rockchip: Bring in RK3036 device tree file includes and bindings
Since rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases
we need in uboot

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
302d1767b9 rockchip: add config decide whether to build common.c
some rockchips soc will not use uclass in SPL stage,
so define config to decide whether to build common.c

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
5138337b3f rockchip: rename board-spl.c to rk3288-board-spl.c
since different rockchip soc need different spl file,
so rename board-spl.c.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
8117803430 rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig
since different rockchip SOC have different size of SRAM,
So the size SYS_MALLOC_F_LEN may different, so move this
config to rk3288 own Kconfig

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
cc2244b8fa rockchip: add timer driver
some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Michael Heimpold
a6b1e25fc6 ARM: mxs: fix VDDD brownout setting
At the moment, the desired brownout is at 1.0V. However,
this setting cannot be realized by hardware since we have
only 3 bits to represent the voltage difference from the
target value.

Target value is 1500 mV, brownout target is 1000 mV,
voltage steps are 25 mV.

Register content calculation:
  (1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14

  Register takes only 3 bits, that is 0x4.

But 0x4 * 25 [mV] = 100 [mV], that means that actual
brownout level is 1500 [mV] - 100 [mV] = 1.4 V.

Minimum possible BO level is
  1500 [mV] - 0x7 * 25 [mV] = 1315 [mV].

So lets use this value as desired BO value (which is
also the same as FSL bootlets use).

Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-12-01 16:05:24 +01:00
Simon Glass
3ba5f74a54 dm: pci: Disable PCI compatibility functions by default
We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01 06:26:38 -07:00
Simon Glass
e81ca88451 dm: tegra: pci: Convert tegra boards to driver model for PCI
Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01 06:26:36 -07:00
Stephen Warren
15bcc62d53 ARM: tegra: refactor common Kconfig options
This makes it easier to select common options in a single place, rather
than having to add them separately for different SoCs or architectures.

The lists of select statements are now also sorted for easy searching.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:36 -07:00
Bin Meng
7030f27ef3 x86: tsc: Move tsc_timer.c to drivers/timer
To group all dm timer drivers together, move tsc timer to
drivers/timer directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
1d4c83c248 x86: tsc: Remove legacy timer codes
Now that we have converted all x86 boards to use driver model timer,
remove these legacy timer codes in the tsc driver.

Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option,
as it is not needed with driver model.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
80af39842e x86: Convert to use driver model timer
Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
4e51fc2351 x86: tsc: Add driver model timer support
This adds driver model timer support to x86 tsc timer driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
2f80fc5035 x86: tsc: Use notrace from <linux/compiler.h>
Replace __attribute__((no_instrument_function)) with notrace from
<linux/compiler.h>.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
0f3176ed68 x86: Remove MIN_PORT80_KCLOCKS_DELAY
This is not referenced anywhere. Remove it, as well as
tsc_base_kclocks and tsc_prev in the global data.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix 'Reomve' typo:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
f838f12452 timer: sandbox: Use device tree to pass the clock frequency
We should use device tree to pass the clock frequency of the timer
instead of hardcoded in the driver codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Tom Rini
4a421a67b6 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-11-30 18:13:10 -05:00
Wenyou Yang
e4677f1ae2 arm: at91/spl: atmel_sfr: move saic redirect to separate file
To make saic redirect code sharing with other SoCs, move the
saic redirect code from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/atmel_sfr.c

Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each
SoC has its own value.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:55 +01:00
Wenyou Yang
b5665bf246 arm: at91/spl: matrix: use matrix slave id macros
To make matrix initialization code sharing with others,
use the matrix slave id macros, instead of hard-coding.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:54 +01:00
Wenyou Yang
6f0a51aa68 arm: at91/spl: matrix: remove security peripheral select code
Remove the security peripheral select code, keep the default value
in these registers, that is, the peripheral address space is
configured as "Secured" access, it is suitable for SPL.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:54 +01:00
Wenyou Yang
5906d2aa0c arm: at91/spl: matrix: remove matrix write protection code
On processor reset, the matrix write protection is disabled,
so no need to disable/enable write protection when writing
the matrix registers.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:54 +01:00
Wenyou Yang
5cb9dfa031 arm: at91/spl: matrix: move matrix init to separate file
To make the matrix initialization code sharing with other SoCs,
move it from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/matrix.c

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:53 +01:00
Wenyou Yang
75238f2367 arm: atmel: Add SAMA5D2 Xplained board
The board supports following features:
 - Boot media support: SD card/e.MMC/SPI flash,
 - Support LCD display (optional, disabled by default),
 - Support ethernet,
 - Support USB mass storage.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:53 +01:00
Wenyou Yang
2c62c56a86 gpio: atmel: Add the PIO4 driver support
The PIO4 is introduced from SAMA5D2, as a new version
for Atmel PIO controller.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2015-11-30 22:27:52 +01:00
Tom Rini
1670c8c219 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-11-30 15:18:30 -05:00
York Sun
3785f57015 armv8: fsl-layerscape: Fix early MMU table for nand boot
The early MMU table doesn't enable all addresses. Unused addresses
are marked as invalid, as introduced by commit 9979922. An entry
was missing for NAND flash space, causing nand boot failure.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
2015-11-30 09:11:13 -08:00
Prabhakar Kushwaha
b401736463 armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.

Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:12 -08:00
York Sun
1f6236f06b armv8: fsl-layerscape: Fix "cpu release" command
When one core is released, other cores may not have valid entry
address. Those cores are trapped by "wfe" and wait for further
instruction. When their address is set, they need to be kicked
off by "sev".

Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:12 -08:00
Alison Wang
d764129d30 armv8/layerscape: Update MMU table with execute-never bits
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
2015-11-30 09:11:11 -08:00
York Sun
61bd2f75f5 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
7023100971 armv8/ls1043ardb: add USB support
Add support for the third USB controller for LS1043A.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
28752cf83b armv8/ls1043ardb: add DSPI support
Use the U-Boot Driver Model. Just enable Freescale DSPI driver
and set DSPI related parameters in dts file.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
630532f51f armv8/ls1043aqds: dts: add dtb support
Reuse the dts files from ls1043a linux kernel.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Shaohui Xie
02b5d2ed86 armv8/ls1043aqds: add LS1043AQDS board support
LS1043AQDS Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 DIMM
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two RGMII ports
 * XFI 10G port
 * SGMII
 * QSGMII with 4x 1G ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Gong Qianyu
e1cecb4d42 armv8/ls1043ardb: dts: add dtb support
Reuse dts files from ls1043a linux kernel. Some parts in dts files
may not be needed by U-Boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Gong Qianyu
18a0d8eb46 armv8/fsl-layerscape: Remove reference to gdata
The global_data pointer (gd) has been set earlier in crt0_64.S.
So there's no need to assign it again. Remove gdata since it is going
away in U-Boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Mingkai Hu
af523a0d56 pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Prabhakar Kushwaha
06b5301043 armv8: ls2085a: Add support of LS2085A SoC
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:10:47 -08:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Prabhakar Kushwaha
fb4a87a737 driver: net: fsl-mc: Add DPAA2 commands to manage MC
Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.

Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
99e904c1f0 armv8: lsch3: Fix lane protocol parsing logic
Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.

Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Alison Wang
a1399534f1 arm: ls1021a: Ensure Generic Timer disabled before jumping into the OS
This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot,but the problem was mysteriously related to the toolchain
used for building u-boot.Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.This causes the timer compare to fire 344 seconds
after u-boot configures it.Depending on how fast u-boot gets the
kernel booted,this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.

To fix the above issue, the generic physical timer is disabled
before jumping to the OS.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:01 -08:00
Alison Wang
2b714cfad4 arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit
This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot.  Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.  This causes the timer compare to fire 344 seconds
after u-boot configures it.  Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains.  Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:01 -08:00
Tom Rini
2a8696dfc2 Merge git://git.denx.de/u-boot-socfpga 2015-11-30 08:30:14 -05:00
Chin Liang See
271e9ecd72 arm: socfpga: dts: Adding drvsel and smplsel to dts
Adding new node drvsel and smplsel for SDMMC

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2015-11-30 13:30:19 +01:00
Marek Vasut
856b30dae5 arm: socfpga: Repair SoCrates board
This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-30 13:30:19 +01:00
Dinh Nguyen
871c24bc50 ARM: socfpga: rename the cyclone5 and arria5 base address file
When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-11-30 13:30:19 +01:00
Dinh Nguyen
5a7152e4fd ARM: socfpga: arria10: add base address map for Arria10
Add the base address map for Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-30 13:30:19 +01:00
Philipp Rosenberger
8a30e3a73a arm: socfpga: reset: FIX address of tstscratch register
The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset
of the tstscratch register ist 0x54 not 0x24.

Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02
page 3-17 Reset Manager Module Address Map

Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>
2015-11-30 13:30:19 +01:00
Tom Rini
30f56399e7 Merge git://www.denx.de/git/u-boot-ppc4xx 2015-11-30 07:10:49 -05:00
Tom Rini
a71d99ac03 Merge branch 'master' of git://git.denx.de/u-boot-samsung 2015-11-30 07:10:27 -05:00
Wolfgang Denk
6623aee5b6 PPC4xx: Create "liebherr" vendor directory
In preparation of some new Liebherr boards to be added soon, a new
"liebherr" vendor directory gets created, and the "lwmon5" board
directory is moved into this new vendor directory.

cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2015-11-30 12:50:29 +01:00
Stefan Roese
7514037bcd ppc4xx: Remove remnants from ocotea, taishan, ebony and taihu
The removal of some PPC4xx boards did not catch all references to
these boards. This patch now removes all remnants still left.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
2015-11-30 12:44:54 +01:00
Minkyu Kang
225f5eeccd arm: s5pc1xx: move SoC to mach-s5pc1xx
move arm/arm/cpu/armv7/s5pc1xx to arch/arm/mach-s5pc1xx

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-30 17:17:01 +09:00
Gerald Kerma
f1df81c400 arm: kirkwood: add ZyXEL NSA310S device
This patch add ZyXEL NSA310S 1-Bay Media Server

The ZyXEL NSA310S device is a Kirkwood based NAS:

- SoC: Marvell 88F6702 1000Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: 128MB
- 1 Power button
- 1 Power LED (blue)
- 4 Status LED (green)
- 1 Copy/Sync button
- 1 Reset button
- 1 SATA II port
- 2 USB 2.0 ports (front and back)
- Smart fan

Signed-off-by: Gerald Kerma <dreagle@doukki.net>
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Luka Perkov <luka.perkov@sartura.hr>
2015-11-29 22:16:14 +01:00
Stefan Roese
9eb14cc443 arm: mvebu: Configure ARP timeout and retry count
As some MVEBU platforms using the MVNETA driver seem to miss the
first ARP packet, lets reduce the timeout and increase the retry
count. This increases the speed for communication establishment.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
2015-11-29 16:02:44 +01:00
Ye.Li
90447ef03c mx6: clock: Modify GPMI clock to support mx6sx
On mx6sx, the CCM register bits for GPMI are different as other
mx6 platforms. Modify the GPMI clock function to support mx6sx.

Signed-off-by: Ye.Li <B37916@freescale.com>
2015-11-25 11:40:04 +01:00
Otavio Salvador
3c8dcf0eac iomux-v3: Take MX6D in consideration for imx_iomux_v3_setup_pad()
We should also take MX6D option in consideration when defining
imx_iomux_v3_setup_pad().

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-25 09:41:29 +01:00
Otavio Salvador
d7140351c2 cgtqmx6eval: Add SPL support
Congatec has several MX6 boards based on quad, dual, dual-lite and solo.

Add SPL support so that all the variants can be supported

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-25 09:41:29 +01:00
Vignesh R
71cbed31f4 am33xx: Remove serial_init in s_init for QSPI/NOR XIP boot
serial_init() reads global_data, since global_data is not yet
initialized, this can cause unwanted behaviour leading to QSPI XIP boot
hang. Also, since serial_init() is anyways called later from
boar_init_f(), it does not make sense to do the same in s_init().

Tested on AM437x IDK EVM with QSPI XIP boot.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-23 11:01:53 -05:00
Tom Rini
80d307d115 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-11-22 08:20:03 -05:00
Jelle de Jong
aa56cb374d sunxi: Add support for the Lamobo R1 board
The lamobo-r1 board, sometimes called the BPI-R1 but not labelled as such
on the PCB, is meant as a A20 based router board. As such the board comes
with a built-in switch chip giving it 5 gigabit ethernet ports, and it
has a large empty area on the pcb with mounting holes which will fit a
2.5 inch harddisk. To complete its networking features it has a
Realtek RTL8192CU for WiFi 802.11 b/g/n.

The dts file is identical to the one submitted upstream.

Signed-off-by: Jelle de Jong <jelledejong@powercraft.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-11-22 11:43:58 +01:00
Hans de Goede
d6e6d4b3a9 sunxi: Add H3 dts[i] files
These files are based on the current latest upstream kernel work. The
bus_gates bindings may still change, but for u-boot that does not matter
as we do not (yet) use any clock info from devicetree for sunxi u-boot.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-11-22 11:31:00 +01:00
Siarhei Siamashka
52d093112a sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3
The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz
on Allwinner H3 and using PLL6 as the clock source (PLL6/3).
This can be verified by reading the value of the AHB1_APB1_CFG_REG
register via /dev/mem. It always reads as 0x3180 regardless of
the current cpufreq operating point. So this configuration should
be safe for use in U-Boot too.

PLL6 also needs to be configured before it is used as the clock
source, according to the "CCU / Programming Guidelines" section
of the Allwinner manual.

The current low AHB1 clock speed is limiting the USB transfer
speed when booting via FEL. This patch can increase the FEL USB
transfer speed from ~510 KB/s to ~950 KB/s.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-11-22 11:31:00 +01:00
Jens Kuske
0404d53f2f sunxi: Add H3 DRAM initialization support
Based on existing A23/A33 code and the original H3 boot0.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-11-22 11:31:00 +01:00
Jens Kuske
1c27b7dcd0 sunxi: Add basic H3 support
Add initial sun8i H3 support, only uart + mmc are supported for now.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-11-22 11:30:59 +01:00
Thomas Chou
2f3a5fee9e nios2: 10m50: change to ns16550 uart
Change to ns16550 uart for 10m50 devboard based on a new
Altera release.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:18 -05:00
Thomas Chou
9e39003e7f ns16550: move CONFIG_SYS_NS16550 to Kconfig
Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-21 21:50:18 -05:00
Thomas Chou
1874626b2b ns16550: unify serial_tegra
Unify serial_tegra, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:16 -05:00
Thomas Chou
98a51fc3d7 ns16550: unify serial_rockchip
Unify serial_rockchip, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:15 -05:00
Thomas Chou
f27445cbdc ns16550: unify serial_ppc
Unify serial_ppc, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add TODO comment]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-21 21:50:04 -05:00
Thomas Chou
81cd63a991 ns16550: unify serial_x86
Unify serial_x86, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-20 20:41:30 -05:00
Simon Glass
bff1a71ede dm: test: usb: sandbox: Add keyboard tests for sandbox
Add a test that verifies that USB keyboards work correctly on sandbox.
This verifies some additional parts of the USB stack.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:52 -07:00
Simon Glass
d8a26f0300 usb: sandbox: Add a USB emulation driver
Add a simple USB keyboard driver for sandbox. It provides a function to
'load' it with input data, which it will then stream through to the normal
U-Boot input subsystem. When the input data is exhausted, the keyboard stops
providing data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:52 -07:00
Simon Glass
431cbd6d82 dm: test: usb: Add tests for the 'usb tree' command
Add tests that this command produces the right output, even when a rescan
results in a device disappearing from the bus.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:52 -07:00
Simon Glass
9ce8b40206 test: Record and silence console in tests
When running sandbox tests, silence the console to avoid unwanted output.
Also, record the console in case tests want to check it.

The -v option can be used to enable stdout during tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:51 -07:00
Simon Glass
24b852a7a2 Move console definitions into a new console.h file
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:50 -07:00
Simon Glass
9723563aa8 sandbox: Add a way to skip time delays
Some tests are slow due to delays which are unnecessary on sandbox. The
worst offender is USB where we lose two seconds. Add a way to disable time
delays.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:50 -07:00
Bin Meng
b6ff6ce60c x86: qemu: Convert to use driver model keyboard
Convert to use driver model keyboard on QEMU.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:13:42 -07:00
Bin Meng
60fe101873 x86: crownbay: Convert to use driver model keyboard
Convert to use driver model keyboard on Intel Crown Bay.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:13:42 -07:00
Simon Glass
6b44ae6b06 x86: Add an i8042 device for boards that have it
Some boards have an i8042 device. Enable the driver for all x86 boards, and
add a device tree node for those which may have this keyboard.

Also adjust the configuration so that i8042 is always separate from the VGA,
and rename the stdin driver accordingly. With this commit the keyboard will
not work, but it is fixed in the next commit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-19 20:13:41 -07:00
Thomas Chou
9961a0b6fb sandbox: add a sandbox timer and basic test
Add a sandbox timer which get time from host os and a basic
test.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:13:41 -07:00
Simon Glass
1fa4bfde18 dm: cros_ec: Convert cros_ec keyboard driver to driver model
Adjust the cros_ec keyboard driver to support driver model. Make this the
default for all Exynos boards so that those that use a keyboard will build
correctly with this driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:13:40 -07:00
Simon Glass
f77f5e9be7 dm: tegra: Convert keyboard driver to driver model
Adjust the tegra keyboard driver to support driver model, using the new
uclass. Make this the default for all Tegra boards so that those that use
a keyboard will build correctly with this driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:13:40 -07:00
Tom Rini
9ef671c9d4 Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-11-19 13:27:26 -05:00
Tom Rini
aa7077fcee Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2015-11-19 11:25:36 -05:00
Nathan Rossi
e0f21e1cbc microblaze: Fix C99/gnu99 compatiblity for inline functions
'extern inline' is not portable across various C standards. To ensure
compatiblity with various standards/compilers change the functions to
static inline. This is a portable construct and serves as a comparable
definition to 'extern inline' from the gnu90 standard.

Additionally remove the function prototypes as they are not required due
to the functions being declared static and functions are correctly
ordered based on dependence.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-19 13:09:41 +01:00
Nathan Rossi
7cb73730c8 microblaze: Fix style issues in header files
Fix various style issues in MicroBlaze header files. Specifically fixing
style voilations including '__inline__', 'foo * bar' and 'void foo ('.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-19 13:09:41 +01:00
Michal Simek
a7bcd4c32a zynqmp: mp: Add support for booting R5 from any address
Put jump trampoline to TCM at 0 and setup R5 reset address to 0.
Jump trampoline ensures that jump to the right location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-19 10:42:45 +01:00
Nikita Kiryanov
a1e56cf6d4 spl: mmc: add support for BOOT_DEVICE_MMC2
Currently the mmc device that SPL looks at is always mmc0, regardless
of the BOOT_DEVICE_MMCx value. This forces some boards to
implement hacks in order to boot from other mmc devices.

Make SPL take into account the correct mmc device.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-18 14:50:05 -05:00
Nikita Kiryanov
36afd45136 spl: change return values of spl_*_load_image()
Make spl_*_load_image() functions return a value instead of
hanging if a problem is encountered. This enables main spl code
to make the decision whether to hang or not, thus preparing
it to support alternative boot devices.

Some boot devices (namely nand and spi) do not hang on error.
Instead, they return normally and SPL proceeds to boot the
contents of the load address. This is considered a bug and
is rectified by hanging on error for these devices as well.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-18 14:50:02 -05:00
Kipisz, Steven
74cc8b097d board: ti: beagle_x15: Rename to indicate support for TI am57xx evms
BeagleBoard X15 (http://beagleboard.org/x15) support in u-boot does
actually support two different platform configuration offered by
TI. In addition to BeagleBoard X15, it also supports the TMDXEVM5728
(or more commonly known as AM5728-evm).

Information about the TI AM57xx EVM can be found here
http://www.ti.com/tool/tmdxevm5728

The EVM configuration is 1-1 compatible with BeagleBoard X15 with the
additional support for mPCIe, mSATA, LCD, touchscreen, Camera, push
button and TI's wlink8 offering.

Hence, we rename the beagle_x15 directory to am57xx to support TI
EVMs that use the AM57xx processor. By doing this we have common code
reuse. This sets the stage to have a common u-boot image solution for
multiple TI EVMs such as that already done for am335x and am437x. This
sets the stage for upcoming multiple TI EVMs that share the same code
base.

NOTE: Commit eae7ae1853 ("am437x: Add am57xx_evm_defconfig using
CONFIG_DM") introduced DT support for beagle_x15 under am57xx_evm
platform name. However, this ignored the potential confusion arising for
users as a result. To prevent this, existing beagle_x15_defconfig is
renamed as am57xx_evm_nodt_defconfig to denote that this is the "non
device tree" configuration for the same platform. We still retain
am57xx-beagle-x15.dts at this point, since we just require the common
minimum dts.

As a result of this change, users should expect changes in build
procedures('make am57xx_evm_nodt_defconfig' instead of 'make
beagle_x15_defconfig'). Hopefully, this would be a one-time change.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-11-18 08:47:03 -05:00
Thomas Chou
f5b76de440 nios2: zap ioremap
Zap ioremap(), as it is replaced by map_physmem(,,MAP_NOCACHE).

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-18 21:18:30 +08:00
Thomas Chou
7be35ddd20 nios2: dma-mapping.h: change ioremap to map_physmem
Change ioremap() to map_physmem(), as it is more used in u-boot.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-18 21:18:30 +08:00
Tom Rini
fe524569d4 Merge git://git.denx.de/u-boot-marvell 2015-11-17 17:57:32 -05:00
Kevin Smith
490753ace3 arm: mvebu: a38x: serdes specification cleanup
Instead of allocating space in the driver for the serdes
specification table, just allow the board file to set a pointer
to it.  Also, allow the board to only specify the lanes that are
used instead of including unused lanes.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-11-17 23:41:41 +01:00
Kevin Smith
18c202aa54 arm: mvebu: a38x: Add const to some function calls
Functions that do not modify the pointer passed should declare it
as const.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-11-17 23:41:41 +01:00
Kevin Smith
544acb07ec arm: mvebu: a38x: Remove unsupported topologies
A lot of extra configuration information was left over in the
Marvell serdes and DDR3 initialization code for boards that
U-boot does not support.  Remove this extra config information,
and the concept of fixing up board topologies with information
loaded from an EEPROM.  If this needs to be done, it should be
handled in the board file, not in core code.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-11-17 23:41:41 +01:00
Alexey Brodkin
fb2dea60e8 board: axs10x switch serial port and Ethernet to driver model
With this change Synopsys DesignWare SDP board is switched to driver
model for both serial port (serial_dw) and Ethernet (Designware GMAC).

This simplifies include/configs/axs101.h and allows for reuse of Linux's
Device Tree description.

For simplicity Linux's .dts files are not blindly copied but only very
few extracts of them are really used (those that are supported in U-Boot
at the moment).

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-11-18 00:39:22 +03:00
Alexey Brodkin
db1f17f894 arc: add empty asm/processor.h to satisfy compilation of USB code
common/usb.c unconditionally includes <asm/processor.h>
And now to allow USB support on ARC boards we have to have that header.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-11-18 00:39:22 +03:00
Alexey Brodkin
90841dc21e arc: add stubs for map_physmem() and unmap_physmem()
Up until now there was no need in those stubs.

But since following commit compilation of U-Boot on ARC is broken:
------------------------>8----------------------
commit 7861204c9a
Author: Stephen Warren <swarren@wwwdotorg.org>
Date:   Sat Oct 3 13:56:46 2015 -0600

    itest: make memory access work under sandbox

    itest accesses memory, and hence must map/unmap it. Without doing so, it
    accesses invalid addresses and crashes.

    Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
    Reviewed-by: Simon Glass <sjg@chromium.org>
------------------------>8----------------------

That's because CMD_ITEST is enabled by default in common/Kconfig and now
map_physmem()/unmap_physmem() is used there.

So this patch adds missing stubs for ARC.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
2015-11-18 00:38:35 +03:00
Vignesh R
2d13459721 ARM: am43xx: Enable QUAD read and EDMA support for ti_qspi
Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this
increases read performance to 4 MB/s.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-17 23:43:29 +05:30
Tom Rini
98e73c8344 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-11-16 08:35:38 -05:00
Tom Rini
618a51e9ae Merge branch 'series1_v2' of git://git.denx.de/u-boot-sparc 2015-11-13 10:04:34 -05:00
Bin Meng
902ca5bdf3 x86: Remove legacy pci codes
Now that we have converted all x86 boards to use driver model pci,
remove these legacy pci codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:25 -08:00
Bin Meng
aedefb6f79 x86: qemu: Convert to use driver model pci
Move to driver model for pci on QEMU.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:23 -08:00
Bin Meng
487485956b x86: qemu: Move chipset-specific codes from pci.c to qemu.c
Move chipset-specific codes such as PAM init, PCIe ECAM and MP table
from pci.c to qemu.c, to prepare for DM PCI conversion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:22 -08:00
Bin Meng
20cbafa6fa x86: qemu: Remove call to vgabios execution
The call to pci_run_vga_bios() is not needed as this is handled
in the vesa_fb driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:21 -08:00
Bin Meng
e5ffa4bb62 x86: queensbay: Really disable IGD
According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA display controller
class in the PCI configuration space, and should also prevent
it from responding to VGA legacy memory range and I/O addresses.

However test result shows that with just VGA Disable bit set and
a PCIe graphics card connected to one of the PCIe controllers on
the E6xx, accessing the VGA legacy space still causes system hang.
After a number of attempts, it turns out besides VGA Disable bit,
the SDVO (D3:F0) device should be disabled to make it work.

To simplify, use the Function Disable register (offset 0xc4)
to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
two devices will be completely disabled (invisible in the PCI
configuration space) unless a system reset is performed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:20 -08:00
Bin Meng
1eb39a5093 x86: Move CONFIG_8259_PIC and CONFIG_8254_TIMER to Kconfig
Add Kconfig options for 8259 and 8254.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:19 -08:00
Bin Meng
da3fe24759 x86: Rename pcat_ to i8254 and i8259 accordingly
Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c,
to match their header file names (i8254.h and i8259.h).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:18 -08:00
Bin Meng
bffeed0158 x86: Initialize i8254 timer counter 1
Initialize counter 1, used to refresh request signal. This is
required for legacy purpose as some codes like vgabios utilizes
counter 1 to provide delay functionality.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:18 -08:00
Bin Meng
0a2ea02068 x86: Fix cosmetic issues in the i8254 and i8259 codes
This cleans up i8254 and i8259 codes to fix several cosmetic
issues, like coding convention and some comments improvement.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:17 -08:00
Bin Meng
360c3013c8 x86: Remove dead codes wrapped by PARANOID_IRQ_TRIGGERS
PARANOID_IRQ_TRIGGERS is not referenced anywhere in U-Boot.
Remove these dead codes wrapped by it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:16 -08:00
Bin Meng
6c5052716e x86: Rename CONFIG_SYS_NUM_IRQS to SYS_NUM_IRQS
CONFIG_SYS_NUM_IRQS is actually not something we can configure,
but an architecture defined number of ISA IRQs. Move it from
x86-common.h to asm/interrupt.h and rename it to SYS_NUM_IRQS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 06:46:16 -08:00
Francois Retief
e43ce3fca7 sparc: leon3: Add debug_uart support to LEON3 serial driver.
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-11-13 10:23:33 +02:00
Daniel Hellstrom
5786071e4a sparc: ambapp: Removed warning and unnecessary printout.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-11-13 10:23:33 +02:00
Daniel Hellstrom
f2879f5952 sparc: leon3: Moved GRLIB core header files to common include/grlib directory
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-11-13 10:23:33 +02:00
Daniel Hellstrom
cff009ed6f sparc: leon3: Added memory controller initialization using new AMBA PnP routines.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-11-13 10:23:33 +02:00
Daniel Hellstrom
898cc81da3 sparc: leon3: Reimplemented AMBA Plug&Play scanning routines.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-11-13 10:23:32 +02:00
Francois Retief
0070109f68 sparc: Update startup code to take PIC mode into account
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-11-13 10:23:32 +02:00
Francois Retief
a50adb7b4d sparc: Update LEON serial drivers to use readl/writel macros
Update the LEON2/3 serial driver to make use of the readl and writel
macros as well as the WATCHDOG_RESET() macro.

Add readl/writel and friends to the asm/io.h file.

Introduce the gd->arch.uart variable to store register address.

Lastly, remove baudrate scaler macro variables from board config. It
is now calculated in the serial driver using the global data variable.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-11-13 10:23:32 +02:00
Francois Retief
c33759aebd sparc: Add -mcpu= compiler flags for LEON2/LEON3
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-11-13 10:23:32 +02:00
Francois Retief
72bcbd4bfb sparc: Fix broken files during license changes
Fixes broken search and replaced license changes in
files cpu/leon3/start.S and include/asm/winmacro.h
from commit 1a4596601f

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>

Series-to: u-boot
Series-cc: Tom Rini <trini@konsulko.com>
Series-version: 2
Cover-letter:
sparc: Updates to SPARC architecture in preperation for generic board

This patch series is a backlog of preparation work for upcomming
generic board changes.

I first want to get these reviewed and submitted to mainline before
sending out more patches.
END
2015-11-13 10:22:49 +02:00
Tom Rini
bc80109b11 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-11-12 19:32:51 -05:00
Guillaume REMBERT
87da2690ab openrisc: updating build tools naming convention
Dear u-boot community,

I just made a small change on the openrisc-generic platform
configuration to take in account the new naming convention (or1k instead
of or32, so the build process gets fine).

Could you take care to review and approve the following patch, please?

Kind regards,
2015-11-12 18:13:20 -05:00
Dirk Eibach
a3f9d6c779 mpc83xx: Add strider board
The gdsys strider board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.

On board peripherals include:
- 1x 10/100 Mbit/s Ethernet (optional)
- Lattice ECP3 FPGA connected via eLBC

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
[trini: Drop setting CONFIG_SYS_GENERIC_BOARD, this is always true now]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-12 18:03:48 -05:00
Prabhakar Kushwaha
4e4ad6d140 driver: gpio: hikey: Fix pointer conversion warnings for hikey
Fix below compilation warnings-
drivers/gpio/hi6220_gpio.c: In function ‘hi6220_gpio_probe’:
drivers/gpio/hi6220_gpio.c:82:15: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
  bank->base = (u8 *)plat->base;

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2015-11-12 15:58:59 -05:00
Peng Fan
f978559c05 imx: mx7: compile misc.c for mx7
Compile misc.c for mx7, since we need related function for
lcdif and nand.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Sanchayan Maity <maitysanchayan@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-12 17:40:54 +01:00
Peng Fan
623787fd58 imx: imx-common: power down lcdif before boot os
Need to call lcdif_power_down to make lcdif in initial state
before kernel boot. Similar issue for uboot reset with lcdif
enabled, system will hang after serveral times resetting. Need
to let lcdif initial state to make all go well.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-12 17:40:54 +01:00
Peng Fan
eb111bb31d imx: mx6: implement reset_misc
We need to power down lcdif before uboot reset to make reset can pass
stress test.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-11-12 17:40:53 +01:00
Peng Fan
a3c252d6d6 video: mxsfb: introduce lcdif_power_down
Introudce a new function lcdif_power_down.

1. Waits for a VSYNC interrupt to guarantee the reset is done at the
   VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?)
   and helps the LCDIF work normally at the kernel stage.
2. Add power down function to stop lcdif.

The reason to introduce lcdif_power_down is that we want lcdif to be in
initial state when doing uboot reset or before kernel boot to make
system stable, otherwise system may hang.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-11-12 17:40:53 +01:00
Peng Fan
ad153782e0 imx: mx6: add clock api for lcdif
Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video.
The three API can be used to configure lcdif related clock when
CONFIG_VIDEO_MXS enabled.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-11-12 17:40:53 +01:00
Peng Fan
64ffef05e0 imx: mx6: crm_reg: add LCDIF related macros
Add i.MX6UL/SX LCDIF related macros. Discard uneccessary
'#ifdef xxx'.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-11-12 17:40:52 +01:00
Peng Fan
b1ce1fb527 imx: mx6: fix register address
1. Move WDOG3_BASE_ADDR to '#if !(defined(__ASSEMBLY__))'.
2. Add i.MX6UL LCDIF register base address. And Introduce
   LCDIF1_BASE_ADDR to support runtime check.
3. include <asm/imx-common/regs-lcdif.h> for imx-regs.h to avoid
   building error for mxsfb.c, since mxsfb.c use imx-regs.h.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-11-12 17:40:52 +01:00
Peng Fan
8702f5ab5d imx: lcdif: use one register structure for i.MXes
Share one lcdif structure for i.MXes.
1. Discard struct mxs_lcdif_regs from imx-regs.h of i.MX7
2. Add i.MX6SX/6UL/7D support in imx-lcdif.h of imx-common

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-11-12 17:38:09 +01:00
Peng Fan
04acd0e5d9 imx: imx-common: move lcdif structure and macro definition to imx-common
Move 'struct mxs_lcdif_regs' and lcdif related macro definitions to
arch/arm/include/asm/imx-common/regs-lcdif.h.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-11-12 17:38:09 +01:00
Peng Fan
eacb287523 imx: include linux/types.h for regs-common.h
There are uint8_t, uint32_t types in regs-common.h, so include
linux/types.h.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-11-12 17:38:08 +01:00
Peng Fan
6014598f9e mxs: regs-common.h must be wrapped with !__ASSEMBLY__
regs-common.h must be wrapped with #ifndef __ASSEMBLY__

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-11-12 17:38:08 +01:00
Peng Fan
95ae700044 mxs: add parameter base_addr for mxs_set_lcdclk
Change mxs_set_lcdclk prototype to add a new parameter
base_addr. There are two LCD interfaces for i.MX6SX,
we may support LCDIF1 or LCDIF2.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-11-12 17:38:08 +01:00
Peng Fan
7de4703691 mx7: psci: add basic psci support
1. add basic psci support for imx7 chip.
2. support cpu_on and cpu_off.
3. switch to non-secure mode when boot linux kernel.
4. set csu allow accessing all peripherial register in non-secure mode.

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-12 17:31:16 +01:00
Peng Fan
d47cb0b61a arm: discard relocation entries for secure text
The code such as PSCI in section named secure is bundled with
u-boot image, and when bootm, the code will be copied to their
runtime address same to compliation/linking address -
CONFIG_ARMV7_SECURE_BASE.

When compile the PSCI code and link it into the u-boot image,
there will be relocation entries in .rel.dyn section for PSCI.
Actually, we do not needs these relocation entries.

If still keep the relocation entries in .rel.dyn section,
r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid
address which may not support read/write for one SoC.
102         /* relative fix: increase location by offset */
103         add     r0, r0, r4
104         ldr     r1, [r0]
105         add     r1, r1, r4
106         str     r1, [r0]

So discard them to avoid touching the relocation entry in
arch/arm/lib/relocate.S.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-11-12 17:31:02 +01:00
Stephen Warren
e1cf527802 ARM: tegra: note that p2371-2180 is Jetson TX1
p2371-2180 is the engineering board name for the Jetson TX1 developer
kit. Update Kconfig description and help text to make this obvious to
everyone.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:27:16 -07:00
Alexandre Courbot
eca676bd67 ARM: tegra: rename GPU functions
Rename GPU functions to less generic names to avoid potential name
collisions.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:07 -07:00
Alexandre Courbot
d6bf06c0c7 ARM: tegra: simplify GPU setup
Enable the GPU node in the system-wide ft_system_setup() hook instead of
the board-specific ft_board_hook(). This allows us to enable GPU per SoC
generation instead of per-board as we did initially.

Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:07 -07:00
Alexandre Courbot
36e5f7ce1c ARM: tegra: remove vpr_configured() function
There is no justification for this function, especially in exported
form.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:07 -07:00
Stephen Warren
f35cb12511 ARM: tegra: error check Tegra210 XUSB padctl waits
Add code to detect timeouts when waiting for HW events such as PLL
lock done. Any errors are logged and trigger an error return code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:07 -07:00
Stephen Warren
4e4b5574fb ARM: tegra: add lane tables to Tegra210 XUSB padctl
Add the tables defining which pads and mux options exist in the Tegra210
XUSB padctl hardware.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:07 -07:00
Stephen Warren
7a908c7e01 ARM: tegra: switch Tegra210 to common XUSB padctl
This change simply deletes code from the Tegra210 XUSB padctl driver that
is already present in the common XUSB padctl code. Since all the arrays
in tegra210_socdata are empty, this update may leave the Tegra210 XUSB
padctl driver non-functional at run-time. However, (a) this driver is not
used yet so no regression can be observed and (b) the next commit will
immediately fix this up.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:06 -07:00
Stephen Warren
095e65839e ARM: tegra: parameterize common XUSB code
There are some differences between the Tegra124 and Tegra210 XUSB padctl
code. So far, the common XUSB padctl code only supports Tegra124. Add
some parameters etc. so that it can work for both chips.

This also allows moving Tegra124's process_nodes() into the common file;
something that would have requires edits during the move if done in the
previous commit.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:06 -07:00
Stephen Warren
1680d7b6de ARM: tegra: create common XUSB padctl driver file
A fair amount of the XUSB padctl driver will be common between Tegra124
and Tegra210. To avoid cut/paste between the two chips, create a new
file that will contain the common code, and convert the Tegra124 code to
use it. This change doesn't move every last piece of code that can/will be
shared, but rather concentrates on moving code that can be moved with zero
changes, so there are no other diffs mixed in.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:06 -07:00
Stephen Warren
057fd32ffc ARM: tegra: clean up XUSB padctl error() calls
This file defines pr_fmt(), so the individual error() calls don't need to
include the prefix in their format strings. Doing so results in duplicate
text in any error messages. Remove the duplication.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:06 -07:00
Stephen Warren
aae52c000f ARM: tegra: rename dummy XUSB padctl implementation
A future patch will soon move some of the XUSB padctl code into a common
file in arch/arm/mach-tegra. Rename the existing dummy XUSB padctl file
to avoid conflicting with that, or being confusing.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:06 -07:00
Stephen Warren
019bc6259d ARM: tegra: enable PCI support of p2371-2180
p2371-2180 has two PCI ports; a regular x4 slot and a x1 M.2 slot. This
patch adds the relevant DT to enable the PCI controller and configure
the XUSB padctl pin muxing, and code to turn on the PCI power and enable
PCI features in U-Boot. I have only tested the x4 slot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:06 -07:00
Stephen Warren
d0af234130 ARM: tegra: add PCI to Tegra210 SoC DT
Tegra210's PCI controller is largely identical to Tegra124, and hence
shares the same binding. However, it has a unique compatible value due
to the existence of at least one new HW bug that would prevent any driver
for a previous HW version from operating correctly.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:05 -07:00
Stephen Warren
dfa551e49c ARM: tegra210: implement PLLE init procedure from TRM
Implement the procedure that the TRM mandates to initialize PLLREFE and
PLLE. This makes the PLL actually lock.

Note that this section of the TRM is being cleaned up to remove some
confusion. The set of register accesses in this patch should be final,
although the step numbers/descriptions might still change.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12 09:21:04 -07:00
Stefano Babic
5f5620ab26 Merge git://git.denx.de/u-boot 2015-11-12 17:13:26 +01:00
Thomas Chou
5c0f9822e7 nios2: add 10m50 devboard support
Add 10m50 devboard support. It is based on the Golden Hardware
Reference Design (GHRD), available at,

http://rocketboards.org/foswiki/view/Documentation/
AlteraMAX1010M50RevCDevelopmentKitLinuxSetup

Though we supported only one nios2-generic board in the past. Now,
with the removal of the nios2-generic board dir, adding new nios2
boards to u-boot is easier than before. It should be helpful to
add those boards supported in Linux mainline. There are only two
such nios2 boards, the 3c120 devboard and 10m50 devboard. The
nios2-generic is actually 3c120, and should restore the name. The
10m50 is this one.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-12 08:26:59 +08:00
Thomas Chou
207e97b923 nios2: add memcpy_fromio and memcpy_toio
Add memcpy_fromio() and memcpy_toio().

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-12 08:26:58 +08:00
Masahiro Yamada
b375219e73 ARM: uniphier: drop UniPhier specific SMP code
The latest Linux can directly handle SMP operations for UniPhier SoCs
without any help of U-boot.  Drop the relevant code from U-boot.

See commit b1e4006aeda8c8784029de17d47987c21ea75f6d ("ARM: uniphier:
rework SMP operations to use trampoline code") in Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-11 23:35:35 +09:00
Masahiro Yamada
2610b1362b ARM: dts: uniphier: add USB xHCI nodes for PH1-Pro5 and ProXstream2
This makes USB3.0 available on new SoCs/boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-11 23:35:34 +09:00
Masahiro Yamada
57e2c481c7 ARM: dts: uniphier: fix interrupt number of USB core for PH1-Pro4
The IRQ is not used in U-Boot, but this would be useful to sync
device trees between Linux and U-Boot.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-11-11 23:35:26 +09:00
Tom Rini
cad0499071 Merge branch 'master' of git://git.denx.de/u-boot-arm 2015-11-10 13:38:08 -05:00
Stephen Warren
376cb1a453 ARM: tegra: add custom MMU setup on ARMv8
This sets up a fine-grained page table, which is a requirement for
noncached_init() to operate correctly.

MMU setup code currently exists in a number of places:
- A version in the core ARMv8 support code that sets up page tables that
use very large block sizes that CONFIG_SYS_NONCACHED_MEMORY doesn't
support.
- Enhanced versions for fsl-lsch3 and zynmq that set up finer grained
page tables.

Ideally, rather than duplicating the MMU setup code yet again this patch
would instead consolidate all the different routines into the core ARMv8
code so that it supported all use-cases. However, this will require
significant effort since there appear to be a number of discrepancies[1]
between different versions of the code, and between the defines/values by
some copies of the MMU setup code use and the architectural MMU
documentation. Some reverse engineering will be required to determine the
intent of the current code.

[1] For example, in the core ARMv8 MMU setup code, three defines named
TCR_EL[123]_IPS_BITS exist, but only one of them sets the IPS field and
the others set a different field (T1SZ) in the page tables. As far as I
can tell so far, there should be no need to set different values per
exception level nor to modify the T1SZ field at all, since TTBR1 shouldn't
be enabled anyway. Another example is inconsistent values for *_VA_BITS
between the current core ARMv8 MMU setup code and the various SoC-
specific MMU setup code. Another example is that asm/armv8/mmu.h's value
for SECTION_SHIFT doesn't match asm/system.h's MMU_SECTION_SHIFT;
research is needed to determine which code relies on which of those
values and why, and whether fixing the incorrect value will cause any
regression.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-11-10 18:04:19 +01:00
Stephen Warren
3c6af3bad4 armv8: allow custom MMU setup routines on ARMv8
In order for noncached_init() to operate correctly, SoCs must set up a
custom page table with fine-grained (2MiB) sections, which can be
configured from noncached_init().

This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c
by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There
are some other reasons for the duplication there though, such as enabling
icache early, and enabling dcaching earlier with a different configuration.

This change makes mmu_setup() a weak implementation, so that the MMU setup
code can be replaced without having to duplicate other code that calls it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-11-10 18:03:41 +01:00
Stephen Warren
88f965d720 armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
The implementation of noncached_init() uses define MMU_SECTION_SIZE.
Define this on ARM64.

Move the prototype of noncached_{init,alloc}() to a location that
doesn't depend on !defined(CONFIG_ARM64).

Note that noncached_init() calls mmu_set_region_dcache_behaviour() which
relies on something having set up translation tables with 2MB block size.
The core ARMv8 MMU setup code does not do this by default, but currently
relies on SoC specific MMU setup code. Be aware of this before enabling
this feature on your platform!

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-11-10 18:03:31 +01:00
Vadzim Dambrouski
43fb0e3926 arm: stm32f4: fix a bug when a random sector gets erased
Old sector number is not being cleared from FLASH_CR register. For example
when first erased sector was 001 and then you want to erase sector 010,
sector 011 gets erased instead.
This patch clears old sector number from FLASH_CR register before a new
one is written.

Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
2015-11-10 16:48:50 +01:00
Vadzim Dambrouski
4cd3246f2a arm: stm32f4: fix a bug when only first sector gets erased
flash_lock call is inside a for loop, so after the first iteration flash
is locked and no more sectors can be erased.
Move flash_lock out of the loop.

Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
2015-11-10 16:48:47 +01:00
Tom Rini
7ff15aca1a powerpc: Finish updating u-boot*lds scripts for newer binutils
In 522b021 we dropped 'PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4)' lines in
the mpc85xx linker scripts as this is not required and breaks newer
binutils.  This commit cleans up the rest of the powerpc linker scripts.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-10 09:20:29 -05:00
Tom Rini
da58dec866 Various Makefiles: Add SPDX-License-Identifier tags
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-10 09:19:52 -05:00
Albert ARIBAUD
3562936373 Revive OpenRD targets
Revert commit 7a2c1b13 which dropped OpenRD boards.
Assume maintainership of OpenRD.
Remove OpenRD from scrapyard.
Switch OpenRD to generic board.
Switch to Thumb build.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-11-10 15:04:21 +01:00
Albert ARIBAUD
e7de61b3e4 kirkwood: support CONFIG_SYS_THUMB_BUILD
Kirkwood files cpu.c and cache.c cannot build in Thumb state;
force them in ARM state even under CONFIG_SYS_THUMB_BUILD.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-11-10 15:04:01 +01:00
Albert ARIBAUD
62e92077a8 arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD
When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.

This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-11-10 15:03:48 +01:00
Vadzim Dambrouski
7bdf75ca5c arm: fix compile warnings when semihosting is enabled on ARMv7M target.
This patch fixes compile warnings like this:

warning: format '%lu' expects argument of type 'long unsigned int',
         but argument 5 has type 'size_t'

In C99 standard you can use %zu modifier to print size_t values.

Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
2015-11-10 09:45:36 +01:00
Vadzim Dambrouski
432a6241bd arm: add support for semihosting for ARMv7M targets
If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile
error looking like this:

arch/arm/lib/semihosting.c: In function 'smh_read':
{standard input}: Assembler messages:
{standard input}:34: Error: invalid swi expression
{standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0
scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed

The source of the problem is "svc #0x123456" instruction. This instruction
can not be encoded using Thumb2 instruction set used by ARMv7M CPUs.
ARM documentation suggests using "bkpt #0xAB" instruction instead [1].
This patch fixes compile errors and adds support for semihosting for
STM32F429 or any other ARMv7M target.
This change was sested on STM32F429-DISCOVERY board using OpenOCD and
"smhload" u-boot command.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html

Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
2015-11-10 09:45:33 +01:00
Zhenhua Luo
522b021a8a mpc85xx/u-boot*.lds: remove _GLOBAL_OFFSET_TABLE_ definition
In binutils-2.25, the _GLOBAL_OFFSET_TABLE_ symbols defined by PROVIDE in
u-boot.lds overrides the linker built-in symbols
(https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff;
h=b893397a4b1316610f49819344817715e4305de9),
so the linker is treating _GLOBAL_OFFSET_TABLE_ as a definition into the
.reloc section.

To align with the change of binutils-2.25, the _GLOBAL_OFFSET_TABLE_ symbol
should not be defined in sections, and the symbols in linker generated .got
section should be used(https://sourceware.org/ml/binutils/2008-09/
msg00122.html)

Fixed the following build errors with binutils-2.25:
| powerpc-poky-linux-gnuspe-ld.bfd: _GLOBAL_OFFSET_TABLE_ not defined in
linker created .got

Signed-off-by: Zhenhua Luo <zhenhua.luo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2015-11-09 23:21:06 +00:00
Måns Rullgård
44d0677a90 Replace "extern inline" with "static inline"
A number of headers define functions as "extern inline" which is
causing problems with gcc5.  The reason is that starting with
version 5.1, gcc defaults to the standard C99 semantics for the
inline keyword.

Under the traditional GNU inline semantics, an "extern inline"
function would never create an external definition, the same
as inline *without* extern in C99.  In C99, and "extern inline"
definition is simply an external definition with an inline hint.
In short, the meanings of inline with and without extern are
swapped between GNU and C99.

The upshot is that all these definitions in header files create
an external definition wherever those headers are included,
resulting in multiple definition errors at link time.

Changing all these functions to "static inline" fixes the problem
since this works as desired in all gcc versions.  Although the
semantics are slightly different (a static inline definition may
result in an actual function being emitted), it works as intended
in practice.

This patch also removes extern prototype declarations for the
changed functions where they existed.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2015-11-09 18:19:40 -05:00
Michal Simek
e490ad25eb ARM64: zynqmp: Sync zynq_sdhci_init() declaration
This patch fix compilation error:
drivers/mmc/zynq_sdhci.c:16:5: error: conflicting types for
‘zynq_sdhci_init’
 int zynq_sdhci_init(phys_addr_t regbase)
     ^
In file included from drivers/mmc/zynq_sdhci.c:14:0:
./arch/arm/include/asm/arch/sys_proto.h:16:5: note: previous declaration
of ‘zynq_sdhci_init’ was here
 int zynq_sdhci_init(unsigned long regbase);
     ^

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-07 08:17:54 -05:00
Tom Rini
4ca0c3c993 Merge branch 'master' of git://git.denx.de/u-boot-nios 2015-11-06 09:21:33 -05:00
Tom Rini
250ea267d8 Merge branch 'master' of git://git.denx.de/u-boot-mips 2015-11-06 09:17:17 -05:00
Daniel Schwierzeck
347ea94e2a MIPS: bootm: use CONFIG_IS_ENABLED() everywhere
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-06 13:27:28 +01:00
Daniel Schwierzeck
2bb5b63879 MIPS: bootm: rework and fix broken bootm code
The move to 'generic board' as well as changes in the generic
bootm code broke the boot of FIT uImage's. Especially uImage's
with additional initramfs images or FDT's do not work anymore.

Refactor the bootm code to work again with the generic bootm code.

Always relocate ramdisk and FDT in step 'bootm prep' because the
generic bootm code does this only for legacy uImage's.

Move the step 'bootm cmdline' to 'bootm prep' because the Linux
kernel parameters rd_start and rd_size have to be initialized after
the relocation of the ramdisk.

Furthermore support the step 'bootm fake'.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-06 13:27:28 +01:00
Thomas Chou
9208d7eba1 nios2: fix cached mode in clearing the BSS
As the generic board runs in cached mode, it should not use
"stwio" which bypass the cache.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Chin Liang See <clsee@altera.com>
2015-11-06 09:14:12 +08:00
Thomas Chou
65af9f6971 nios2: remove CONFIG_SYS_INIT_SP macro
Remove CONFIG_SYS_INIT_SP macro, as the initial stack is set to
below the u-boot code.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Chin Liang See <clsee@altera.com>
2015-11-06 09:14:12 +08:00
Thomas Chou
2de4823dc0 nios2: change virt_to_phys to use physaddr_mask in global data
As virt_to_phys() is used a lot in DMA transfer, change it
to use physaddr_mask in global data. This will save an "if"
statement and get a little faster.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-11-06 09:14:11 +08:00
Thomas Chou
1cda48f333 nios2: remove the useless parenthesis in asm/io.h
Remove the useless parenthesis in asm/io.h as suggested
by Marek.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-11-06 09:14:11 +08:00
Thomas Chou
1ce61cbbe7 nios2: fix map_physmem to do real cache mapping
Fix the map_physmem() to do real cache mapping.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-11-06 09:14:11 +08:00
Fabio Estevam
2d2f490dd5 powerpc: Remove __ilog2_u64 and ffs4 from bitops
Remove __ilog2_u64 and ffs4 from powerpc bitops to align with the
kernel implementation.

Use the generic __ffs64 instead of a custom powerpc implementation.

Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 16:47:05 -05:00
Fabio Estevam
f8fdb81f6c compat: Remove is_power_of_2() definition
Use the is_power_of_2() definition from log2.h to align with the
kernel implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 16:46:59 -05:00
Fabio Estevam
61a177767c avr32: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-05 10:52:31 -05:00
Fabio Estevam
5d8e66079d arc: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-05 10:52:29 -05:00
Fabio Estevam
b810aa1dd1 mips: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-11-05 10:52:26 -05:00
Fabio Estevam
7a2a091c4a nios2: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:52:23 -05:00
Fabio Estevam
d0a31232f5 nds32: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:52:21 -05:00
Fabio Estevam
85dfd700b6 openrisc: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:52:19 -05:00
Fabio Estevam
a428c9e9ce sparc: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:52:16 -05:00
Fabio Estevam
d308c9efad sandbox: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:52:14 -05:00
Fabio Estevam
e6e7b7c0ab microblaze: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-05 10:52:11 -05:00
Fabio Estevam
f86411b18d sh: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2015-11-05 10:52:09 -05:00
Fabio Estevam
9b0e3fd1c8 blackfin: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:52:06 -05:00
Fabio Estevam
d67154523c m68k: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:52:04 -05:00
Fabio Estevam
6c2f758cee x86: Use the generic bitops headers
Use the generic bitops and also add custom __ffs() implementation
as per the kernel.

Also align the ffs() implementation with the kernel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 10:52:01 -05:00