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https://github.com/AsahiLinux/u-boot
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nios2: add 10m50 devboard support
Add 10m50 devboard support. It is based on the Golden Hardware Reference Design (GHRD), available at, http://rocketboards.org/foswiki/view/Documentation/ AlteraMAX1010M50RevCDevelopmentKitLinuxSetup Though we supported only one nios2-generic board in the past. Now, with the removal of the nios2-generic board dir, adding new nios2 boards to u-boot is easier than before. It should be helpful to add those boards supported in Linux mainline. There are only two such nios2 boards, the 3c120 devboard and 10m50 devboard. The nios2-generic is actually 3c120, and should restore the name. The 10m50 is this one. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Thomas Chou
parent
e3e872604d
commit
5c0f9822e7
3 changed files with 396 additions and 0 deletions
267
arch/nios2/dts/10m50_devboard.dts
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267
arch/nios2/dts/10m50_devboard.dts
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/*
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* Copyright (C) 2015 Altera Corporation
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*
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* This file is generated by sopc2dts.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/ {
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model = "Altera NiosII Max10";
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compatible = "altr,niosii-max10";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "altr,nios2-1.1";
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reg = <0x00000000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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altr,exception-addr = <0xc8000120>;
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altr,fast-tlb-miss-addr = <0xc0000100>;
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altr,has-div = <1>;
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altr,has-initda = <1>;
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altr,has-mmu = <1>;
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altr,has-mul = <1>;
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altr,implementation = "fast";
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altr,pid-num-bits = <8>;
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altr,reset-addr = <0xd4000000>;
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altr,tlb-num-entries = <256>;
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altr,tlb-num-ways = <16>;
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altr,tlb-ptr-sz = <8>;
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clock-frequency = <75000000>;
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dcache-line-size = <32>;
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dcache-size = <32768>;
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icache-line-size = <32>;
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icache-size = <32768>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x08000000 0x08000000>,
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<0x00000000 0x00000400>;
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};
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sopc0: sopc@0 {
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device_type = "soc";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "altr,avalon", "simple-bus";
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bus-frequency = <75000000>;
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jtag_uart: serial@18001530 {
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compatible = "altr,juart-1.0";
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reg = <0x18001530 0x00000008>;
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interrupt-parent = <&cpu>;
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interrupts = <7>;
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};
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a_16550_uart_0: serial@18001600 {
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compatible = "altr,16550-FIFO32", "ns16550a";
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reg = <0x18001600 0x00000200>;
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interrupt-parent = <&cpu>;
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interrupts = <1>;
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auto-flow-control = <1>;
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clock-frequency = <50000000>;
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fifo-size = <32>;
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reg-io-width = <4>;
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reg-shift = <2>;
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};
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ext_flash: quadspi@0x180014a0 {
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compatible = "altr,quadspi-1.0";
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reg = <0x180014a0 0x00000020>,
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<0x14000000 0x04000000>;
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reg-names = "avl_csr", "avl_mem";
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interrupt-parent = <&cpu>;
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interrupts = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash0: nor0@0 {
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compatible = "micron,n25q512a";
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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sysid: sysid@18001528 {
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compatible = "altr,sysid-1.0";
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reg = <0x18001528 0x00000008>;
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};
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rgmii_0_eth_tse_0: ethernet@400 {
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compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0";
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reg = <0x00000400 0x00000400>,
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<0x00000820 0x00000020>,
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<0x00000800 0x00000020>,
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<0x000008c0 0x00000008>,
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<0x00000840 0x00000020>,
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<0x00000860 0x00000020>;
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reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp",
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"tx_csr", "tx_desc";
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interrupt-parent = <&cpu>;
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interrupts = <2 3>;
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interrupt-names = "rx_irq", "tx_irq";
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rx-fifo-depth = <8192>;
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tx-fifo-depth = <8192>;
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address-bits = <48>;
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max-frame-size = <1518>;
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local-mac-address = [00 00 00 00 00 00];
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altr,has-supplementary-unicast;
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altr,enable-sup-addr = <1>;
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altr,has-hash-multicast-filter;
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altr,enable-hash = <1>;
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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rgmii_0_eth_tse_0_mdio: mdio {
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compatible = "altr,tse-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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device_type = "ethernet-phy";
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};
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};
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};
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enet_pll: clock@0 {
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compatible = "altr,pll-1.0";
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#clock-cells = <1>;
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enet_pll_c0: enet_pll_c0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "enet_pll-c0";
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};
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enet_pll_c1: enet_pll_c1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "enet_pll-c1";
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};
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enet_pll_c2: enet_pll_c2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <2500000>;
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clock-output-names = "enet_pll-c2";
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};
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};
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sys_pll: clock@1 {
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compatible = "altr,pll-1.0";
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#clock-cells = <1>;
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sys_pll_c0: sys_pll_c0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sys_pll-c0";
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};
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sys_pll_c1: sys_pll_c1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "sys_pll-c1";
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};
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sys_pll_c2: sys_pll_c2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <75000000>;
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clock-output-names = "sys_pll-c2";
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};
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};
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sys_clk_timer: timer@18001440 {
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compatible = "altr,timer-1.0";
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reg = <0x18001440 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <0>;
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clock-frequency = <75000000>;
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};
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led_pio: gpio@180014d0 {
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compatible = "altr,pio-1.0";
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reg = <0x180014d0 0x00000010>;
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altr,gpio-bank-width = <4>;
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resetvalue = <15>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "led";
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};
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uart_0: serial@0x18001420 {
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compatible = "altr,uart-1.0";
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reg = <0x18001420 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <1>;
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clock-frequency = <75000000>;
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current-speed = <115200>;
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};
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button_pio: gpio@180014c0 {
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compatible = "altr,pio-1.0";
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reg = <0x180014c0 0x00000010>;
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interrupt-parent = <&cpu>;
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interrupts = <6>;
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altr,gpio-bank-width = <3>;
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altr,interrupt-type = <2>;
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edge_type = <1>;
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level_trigger = <0>;
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resetvalue = <0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "button";
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};
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sys_clk_timer_1: timer@880 {
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compatible = "altr,timer-1.0";
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reg = <0x00000880 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <5>;
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clock-frequency = <75000000>;
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};
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fpga_leds: leds {
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compatible = "gpio-leds";
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led_fpga0: fpga0 {
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label = "fpga_led0";
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gpios = <&led_pio 0 1>;
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};
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led_fpga1: fpga1 {
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label = "fpga_led1";
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gpios = <&led_pio 1 1>;
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};
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led_fpga2: fpga2 {
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label = "fpga_led2";
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gpios = <&led_pio 2 1>;
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};
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led_fpga3: fpga3 {
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label = "fpga_led3";
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gpios = <&led_pio 3 1>;
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};
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};
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};
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chosen {
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bootargs = "debug console=ttyS0,115200";
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stdout-path = &uart_0;
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};
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};
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26
configs/10m50_defconfig
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26
configs/10m50_defconfig
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CONFIG_NIOS2=y
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CONFIG_SYS_CONFIG_NAME="10m50_devboard"
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CONFIG_DM_SERIAL=y
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_CPU=y
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# CONFIG_CMD_BOOTD is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_FPGA is not set
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# CONFIG_CMD_ITEST is not set
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CONFIG_CMD_DHCP=y
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_PING=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_ALTERA_PIO=y
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CONFIG_MISC=y
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CONFIG_ALTERA_SYSID=y
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CONFIG_MTD=y
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CONFIG_ALTERA_QSPI=y
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CONFIG_DM_ETH=y
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CONFIG_ALTERA_TSE=y
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CONFIG_ALTERA_UART=y
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CONFIG_TIMER=y
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CONFIG_ALTERA_TIMER=y
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103
include/configs/10m50_devboard.h
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103
include/configs/10m50_devboard.h
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/*
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* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* BOARD/CPU
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*/
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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/*
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* SERIAL
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*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */
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/*
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* Flash
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 1024
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#define CONFIG_MTD_DEVICE
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/*
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* NET options
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*/
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#define CONFIG_SYS_RX_ETH_BUFFER 0
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#define CONFIG_CMD_MII
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#define CONFIG_PHY_GIGE
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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#define CONFIG_PHY_MARVELL
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* FDT options
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*/
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_LMB
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/*
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* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
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* CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
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* reset address, no? This will keep the environment in user region
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* of flash. NOTE: the monitor length must be multiple of sector size
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* (which is common practice).
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
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#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
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#define CONFIG_ENV_ADDR 0xf4040000
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/*
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* MEMORY ORGANIZATION
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* -Monitor at top of sdram.
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* -The heap is placed below the monitor
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* -The stack is placed below the heap (&grows down).
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*/
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#define CONFIG_SYS_SDRAM_BASE 0xc8000000
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_MONITOR_IS_IN_RAM
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#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
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CONFIG_SYS_SDRAM_SIZE - \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_MALLOC_LEN 0x20000
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/*
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* MISC
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*/
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#define CONFIG_SYS_LONGHELP /* Provide extended help */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
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#define CONFIG_SYS_MAXARGS 16 /* Max command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + \
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16) /* Print buf size */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
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CONFIG_ENV_SIZE - \
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CONFIG_SYS_MALLOC_LEN - \
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0x10000)
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_CMD_GPIO
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#endif /* __CONFIG_H */
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