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imx: lcdif: use one register structure for i.MXes
Share one lcdif structure for i.MXes. 1. Discard struct mxs_lcdif_regs from imx-regs.h of i.MX7 2. Add i.MX6SX/6UL/7D support in imx-lcdif.h of imx-common Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
04acd0e5d9
commit
8702f5ab5d
2 changed files with 22 additions and 102 deletions
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@ -217,6 +217,7 @@
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#define SNVS_LPGPR 0x68
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/imx-common/regs-lcdif.h>
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#include <asm/types.h>
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extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
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@ -1032,101 +1033,6 @@ struct rdc_sema_regs {
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u16 rstgt; /* Reset Gate */
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};
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/* eLCDIF controller registers */
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struct mxs_lcdif_regs {
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u32 hw_lcdif_ctrl; /* 0x00 */
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u32 hw_lcdif_ctrl_set;
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u32 hw_lcdif_ctrl_clr;
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u32 hw_lcdif_ctrl_tog;
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u32 hw_lcdif_ctrl1; /* 0x10 */
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u32 hw_lcdif_ctrl1_set;
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u32 hw_lcdif_ctrl1_clr;
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u32 hw_lcdif_ctrl1_tog;
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u32 hw_lcdif_ctrl2; /* 0x20 */
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u32 hw_lcdif_ctrl2_set;
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u32 hw_lcdif_ctrl2_clr;
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u32 hw_lcdif_ctrl2_tog;
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u32 hw_lcdif_transfer_count; /* 0x30 */
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u32 reserved1[3];
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u32 hw_lcdif_cur_buf; /* 0x40 */
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u32 reserved2[3];
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u32 hw_lcdif_next_buf; /* 0x50 */
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u32 reserved3[3];
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u32 hw_lcdif_timing; /* 0x60 */
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u32 reserved4[3];
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u32 hw_lcdif_vdctrl0; /* 0x70 */
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u32 hw_lcdif_vdctrl0_set;
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u32 hw_lcdif_vdctrl0_clr;
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u32 hw_lcdif_vdctrl0_tog;
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u32 hw_lcdif_vdctrl1; /* 0x80 */
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u32 reserved5[3];
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u32 hw_lcdif_vdctrl2; /* 0x90 */
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u32 reserved6[3];
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u32 hw_lcdif_vdctrl3; /* 0xa0 */
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u32 reserved7[3];
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u32 hw_lcdif_vdctrl4; /* 0xb0 */
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u32 reserved8[3];
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u32 hw_lcdif_dvictrl0; /* 0xc0 */
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u32 reserved9[3];
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u32 hw_lcdif_dvictrl1; /* 0xd0 */
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u32 reserved10[3];
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u32 hw_lcdif_dvictrl2; /* 0xe0 */
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u32 reserved11[3];
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u32 hw_lcdif_dvictrl3; /* 0xf0 */
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u32 reserved12[3];
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u32 hw_lcdif_dvictrl4; /* 0x100 */
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u32 reserved13[3];
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u32 hw_lcdif_csc_coeffctrl0; /* 0x110 */
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u32 reserved14[3];
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u32 hw_lcdif_csc_coeffctrl1; /* 0x120 */
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u32 reserved15[3];
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u32 hw_lcdif_csc_coeffctrl2; /* 0x130 */
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u32 reserved16[3];
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u32 hw_lcdif_csc_coeffctrl3; /* 0x140 */
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u32 reserved17[3];
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u32 hw_lcdif_csc_coeffctrl4; /* 0x150 */
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u32 reserved18[3];
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u32 hw_lcdif_csc_offset; /* 0x160 */
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u32 reserved19[3];
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u32 hw_lcdif_csc_limit; /* 0x170 */
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u32 reserved20[3];
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u32 hw_lcdif_data; /* 0x180 */
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u32 reserved21[3];
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u32 hw_lcdif_bm_error_stat; /* 0x190 */
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u32 reserved22[3];
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u32 hw_lcdif_crc_stat; /* 0x1a0 */
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u32 reserved23[3];
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u32 hw_lcdif_lcdif_stat; /* 0x1b0 */
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u32 reserved24[3];
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u32 hw_lcdif_version; /* 0x1c0 */
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u32 reserved25[3];
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u32 hw_lcdif_debug0; /* 0x1d0 */
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u32 reserved26[3];
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u32 hw_lcdif_debug1; /* 0x1e0 */
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u32 reserved27[3];
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u32 hw_lcdif_debug2; /* 0x1f0 */
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u32 reserved28[3];
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u32 hw_lcdif_thres; /* 0x200 */
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u32 reserved29[3];
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u32 hw_lcdif_as_ctrl; /* 0x210 */
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u32 reserved30[3];
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u32 hw_lcdif_as_buf; /* 0x220 */
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u32 reserved31[3];
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u32 hw_lcdif_as_next_buf; /* 0x230 */
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u32 reserved32[3];
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u32 hw_lcdif_as_clrkeylow; /* 0x240 */
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u32 reserved33[3];
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u32 hw_lcdif_as_clrkeyhigh; /* 0x250 */
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u32 reserved34[3];
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u32 hw_lcdif_as_sync_delay; /* 0x260 */
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u32 reserved35[3];
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u32 hw_lcdif_as_debug3; /* 0x270 */
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u32 reserved36[3];
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u32 hw_lcdif_as_debug4; /* 0x280 */
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u32 reserved37[3];
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u32 hw_lcdif_as_debug5; /* 0x290 */
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};
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#define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
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#define LCDIF_CTRL_SFTRST (1 << 31)
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@ -1,5 +1,5 @@
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/*
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* Freescale i.MX28 LCDIF Register Definitions
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* Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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@ -10,8 +10,8 @@
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX28_REGS_LCDIF_H__
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#define __MX28_REGS_LCDIF_H__
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#ifndef __IMX_REGS_LCDIF_H__
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#define __IMX_REGS_LCDIF_H__
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#ifndef __ASSEMBLY__
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#include <asm/imx-common/regs-common.h>
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@ -19,7 +19,8 @@
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struct mxs_lcdif_regs {
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mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
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mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
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#if defined(CONFIG_MX28)
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#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
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defined(CONFIG_MX7)
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mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
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#endif
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mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
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@ -54,7 +55,8 @@ struct mxs_lcdif_regs {
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#endif
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mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
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mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
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#if defined(CONFIG_MX28)
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#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
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defined(CONFIG_MX7)
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mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
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#endif
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mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
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@ -62,6 +64,18 @@ struct mxs_lcdif_regs {
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mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
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mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
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mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
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#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7)
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mxs_reg_32(hw_lcdif_thres)
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mxs_reg_32(hw_lcdif_as_ctrl)
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mxs_reg_32(hw_lcdif_as_buf)
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mxs_reg_32(hw_lcdif_as_next_buf)
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mxs_reg_32(hw_lcdif_as_clrkeylow)
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mxs_reg_32(hw_lcdif_as_clrkeyhigh)
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mxs_reg_32(hw_lcdif_as_sync_delay)
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mxs_reg_32(hw_lcdif_as_debug3)
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mxs_reg_32(hw_lcdif_as_debug4)
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mxs_reg_32(hw_lcdif_as_debug5)
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#endif
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};
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#endif
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@ -194,7 +208,7 @@ struct mxs_lcdif_regs {
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#if defined(CONFIG_MX23)
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#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
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#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
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#elif defined(CONFIG_MX28)
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#else
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#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
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#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
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#endif
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@ -214,4 +228,4 @@ struct mxs_lcdif_regs {
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#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
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#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
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#endif /* __MX28_REGS_LCDIF_H__ */
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#endif /* __IMX_REGS_LCDIF_H__ */
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