Commit graph

251 commits

Author SHA1 Message Date
Peng Fan
e2748b4167 imx: mx6: correct enable_fec_anatop_clock
We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock,
otherwise we may overridden configuration before enable_fec_anatop_clock.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-02 10:42:31 +02:00
Peng Fan
ada5771f09 imx: mx6 discard 'select CPU_V7' for different targets
Discard the 'select CPU_V7' from Kconfig in arch/arm/cpu/armv7/mx6
for different targets, because ARCH_MX6 selects CPU_V7.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-13 10:38:48 +02:00
Peng Fan
d9cbb264e8 imx: mx6ul: support mx6ul 9x9 evk board
This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk,
the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are:
1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC.
2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk
   supports 512MB DDR3
3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package.

This patch add the following:
1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size()
2. Introduce a macro is_mx6ul_9x9_evk using
   CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL
   part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work,
   so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with
   mx6ul_14x14_evk. And we have no way to dymaically checking this chip
   is 9x9 or 14x14.
3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations.
   POWER related configurations also effect for mx6ul_14x14_evk. But
   power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to
   do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk.
4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM
   configurations.
5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file
   according to board_rev and board_name.
6. Add TARGET_MX6UL_9X9_EVK Kconfig entry

Boot Log:
U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53)
reading u-boot.img
reading u-boot.img

U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 41C
Reset cause: POR
Board: MX6UL 9x9 EVK
I2C:   ready
DRAM:  256 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:   FEC1
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-13 10:32:44 +02:00
Peng Fan
0eca9f6f0d Revert "imx: mx6: ddr correct tRFC and tXS"
This reverts commit 059323fb6a8f21637bb617919715c2427f24777c.

This commit 059323fb6a8f21637bb617919715c2427f24777c use JESD79-3E which
is not the newest spec. Should use JESD79-3F in which tRFC is 260ns for
4Gb chip.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2015-09-13 10:26:45 +02:00
Adrian Alonso
648539c906 arm: imx-common: init: rework wdog settings for imx6/imx7
Rework imx_set_wdog_powerdown to be reused by imx6 and imx7

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:54 +02:00
Adrian Alonso
50a082a88c arm: imx: imx-common: init: move arch init common setup
Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:53 +02:00
Adrian Alonso
ab09e72866 arm: imx: common rework cache settings for imx6
Rework cache settings for imx6, move cache configuration
to imx-common/cache.c so it can be reused for newer SoC

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:53 +02:00
Adrian Alonso
1368f99346 thermal: imx_thermal: rework driver to be reused
Rework imx_thermal driver to be used across i.MX
processor that support thermal sensor

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-09-13 10:11:53 +02:00
Heiko Schocher
9627084c23 arm, imx6: add aristainetos 2b board version
there is a 2b board version of the aristainetos2
board. Differences to the v2:

- spi cs for the nor flash and display controller
  changed
- some pinmux changes
- LED gpio settings changed

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-09-02 15:38:16 +02:00
Peng Fan
d5b2112e75 imx: mx6ul_14x14_evk select MX6UL
There is no need to expose SoC choice to user, we already got
the SoC according to the build target. So default "select MX6UL"
for MX6UL_14x14_EVK target.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:13 +02:00
Peng Fan
e7d3b21bb7 imx: mx6slevk: add SPL support
Add SPL boot support for mx6slevk board.
1. Introduce a configuration file mx6slevk_spl_defconfig.
2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE.
3. Include imx6_spl.h and related SPL macro in mx6slevk.h.
4. select SUPPORT_SPL for TARGET_MX6SLEVK.
5. Add SPL board code to do related initialization.

Boot Log:

U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000)

CPU:   Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 50C
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:13 +02:00
Peng Fan
eb796cbb69 imx: mx6: ddr: add LPDDR2 support
Add LPDDR2 support:
1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2.
2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to
   mx6_ddr3_cfg, but still keep it a single one for easy to choose
   parameters for LPDDR2.
3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC.
4. Update comments.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2015-09-02 15:34:12 +02:00
Peng Fan
f2ff834365 imx: mx6: ddr init MMDC according to ddr_type
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.

Initialize ddr_type for different boards which enable SPL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
1b811e285c imx: mx6: ddr add dram io configuration and header file for i.MX6SL
Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs.
Add a new function mx6sl_dram_iocfg to configure dram io.
Add header file to define macros for register address.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
2cd8cd06bb imx: mx6: ddr correct tRFC and tXS
To Chip density 4Gb, tRFC should be 300ns, see
"Table 61 — Refresh parameters by device density" of JESD79-3E.
tXS(min) is max(5nCK, tRFC(min) + 10ns).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
24139754f5 imx: mx6: ddr no support MMDC1 for i.MX6SL
i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-09-02 15:34:12 +02:00
Soeren Moch
c3f871c176 tbs2910: use full name in Kconfig board selection
Signed-off-by: Soeren Moch <smoch@web.de>
2015-09-02 15:34:11 +02:00
Peng Fan
6d97dc10a8 imx: clock support enet2 anatop clock support
To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
   To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:29:14 +02:00
Peng Fan
21782828f9 imx: mx6 move TARGET_xx Kconfig option to mx6 specific Kconfig file
Move TARGET_xx Kconfig option based on mx6 to arch/arm/cpu/armv7/mx6/Kconfig.
Add enable "CONFIG_ARCH_MX6" for boards based on mx6.
Then we can choose target boards using "make ARCH=arm menuconfig"
with ARCH_MX6 defined.

If using original way, we have no chance to enable ARCH_MX6 when
"make menuconfig". Even define CONFIG_ARCH_MX6=y in xx_defconfig,
kconfig will complains "arch/../configs/platinum_titanium_defconfig:3:
warning: override: TARGET_PLATINUM_TITANIUM changes choice state"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Soeren Moch <smoch@web.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Soeren Moch <smoch@web.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-09-02 15:29:14 +02:00
Peng Fan
a462c34602 imx:mx6ul add dram spl configuration and header file
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
   only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
   runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
   IO configuration.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:09 +02:00
Peng Fan
db1c217c85 imx: mx6ul update soc related settings
1.Update WDOG settings.
2.No need to gate/ungate all PFDs for i.MX6UL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
2015-08-02 11:05:08 +02:00
Peng Fan
a2c74aaf51 imx: mx6ul select SYS_L2CACHE_OFF
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:08 +02:00
Peng Fan
43cb127b75 imx:mx6ul add clock support
1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
   MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
   but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
   sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
   || defined....", only need one CONFIG_PCIE_IMX in header file.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:07 +02:00
Nikita Kiryanov
09a096992b arm: mx6: kconfig: don't select CPU_V7 per board
CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again
by boards that depend on ARCH_MX6.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2015-08-02 10:51:38 +02:00
Nikita Kiryanov
81f5598b2d arm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6
cm-fx6 is an MX6 based board, and the menuconfig hierarchy should
reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2015-08-02 10:51:38 +02:00
Peng Fan
8d7794615c imx: mx6qp Enable PRG clock for IPU
The i.MX6DQP has a PRG module, need to enable its clock for using IPU.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Brown Oliver <B37094@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:46:34 +02:00
Ye.Li
ec0f9530b1 imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QP
Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround
for i.MX6QP.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:45:41 +02:00
Peng Fan
e1c2d68b39 imx: mx6: ccm: Change the clock settings for i.MX6QP
Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.

In c files, use runtime check and discard #ifdef.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:43:45 +02:00
Peng Fan
d0acd99334 imx: add cpu type for i.MX6QP/DP
Add cpu type for i.MX6QP/DP.

This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:42:48 +02:00
Ulises Cardenas
29067abfaf iMX: adding parsing to hab_status command
hab_status command returns a memory dump of the hab event log. But the
raw data is not human-readable. Parsing such data into readable event
will help to minimize debbuging time.

Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
2015-07-10 10:00:14 +02:00
Peng Fan
19c6ec70c5 imx: mx6 add i2c4 clock support for i.MX6SX
Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.

Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-07-10 09:36:16 +02:00
Peng Fan
2d59acc70f imx: mx6 remove duplicated enable_cspi_clock
enable_spi_clock does the same thing with enable_cspi_clock, so
remove enable_cspi_clock.
Remove enable_cspi_clock prototype in header file
convert cm_fx6/spl.c to use enable_spi_clk

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-07-10 09:35:53 +02:00
Peng Fan
dfd4861c22 imx: mx6 correct get_cpu_rev
The DIGPROG register map:
23 ------- 16 | 15 ------ 8 | 7 --- 0 |
 Major upper  | Major Lower |  Minor  |

We also need to account for Major Lower.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-06-27 18:18:40 +02:00
Markus Niebel
51f6c4280f arm: mx6: tqma6: CPU type selection via Kconfig
This is the first patch to remove the
CONFIG_SYS_EXTRA_OPTIONS.

This patch implements CPU type selection from Kconfig.
Further Kconfig stuff is added later.

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2015-06-27 17:52:20 +02:00
Heiko Schocher
21a26940f9 arm, imx6, i2c: add I2C4 for MX6DL
add I2C4 modul for MX6DL based boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-05-26 14:16:54 +02:00
Tim Harvey
f0e8e8944d imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.

Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.

This has been tested with IMX6 Automative and Industrial parts.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-05-19 15:31:40 +02:00
Tim Harvey
9b9449c3e2 imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTP
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.

Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.

These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-05-19 15:31:25 +02:00
Tim Harvey
3625fd64ef arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specified
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.

Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-05-19 15:22:53 +02:00
Nikolay Dimitrov
b68a5b17f9 arm: mx6: ddr3: Remove dead code
imx6 mmdc supports data rates up to 1066 MT/s, so remove the code handling
higher data rates.

Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
2015-05-15 19:21:24 +02:00
Fabio Estevam
b4ed9f86df mx6: Set shared override bit in PL310 AUX_CTRL register
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
2015-05-15 19:21:24 +02:00
Nikolay Dimitrov
8a2bd215a2 arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.

Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which
doesn't take into account DDR3 memory limitations.

Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
2015-05-15 19:20:46 +02:00
Joe Hershberger
a26cd04920 arch: Make board selection choices optional
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
2015-05-12 18:10:02 -04:00
Tim Harvey
78c5a18087 arm: mx6: ddr: add pd_fast_exit flag to system information
DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit.

In slow-exit mode the DLL is off but in some quiescent state that makes it easy
to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK).
In fast-exist mode the DLL is maintained such that it is ready again in about
3tCK.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:35:35 +02:00
Boris BREZILLON
058d231687 board/seco: Add mx6q-uq7 basic board support
Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported).
It also adds a Kconfig skeleton to later add more SECO board (supporting
SoC and board variants).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-03-23 13:19:18 +01:00
Boris BREZILLON
89ebc82137 ARM: mx6: move to a standard arch/board approach
Freescale boards are currently all defined in arch/arm/Kconfig, which
makes them hard to detect.
Moreover the MX6 SoC variant (Q, D, DL, S, SL) selection is currently
done via the SYS_EXTRA_OPTIONS option which marked as deprecated.

Move to a more standard way to select sub-architecture and board by
creating a Kconfig under arch/arm/cpu/armv7/mx6 and a new ARCH_MX6
option.

Existing MX6 board definitions should be moved in this new Kconfig in
choice menu, and new boards should be directly declared in this menu.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-03-23 13:18:01 +01:00
Dirk Behme
9d16c52f62 mx6: soc: Switch to cold reset
Disable the warm reset and enable the cold reset for a more reliable
restart ('reset'). This is taken from the Linux kernel, see imx_src_init()
in arch/arm/mach-imx/src.c.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
2015-03-13 13:29:42 +01:00
Peng Fan
0c1842a01f imx:mx6 remove duplicated includes
There is no need to include asm/bootm.h twice, so remove one.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-03-13 13:28:04 +01:00
Peng Fan
83dd1dd91c ARM: imx6 Add WDOG3 for i.MX6SX
There are three wdogs for i.MX 6SoloX. Add wdog3 support
in function imx_set_wdog_powerdown.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-02-17 10:42:53 +01:00
Peng Fan
1f516faa45 ARM: imx6: disable bandgap self-bias after boot
The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should
be disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
2015-02-17 10:42:53 +01:00
Ye.Li
e8cdeefc22 imx: mx6: Fixed AIPS3 base address issue
Should use AIPS3 configuration address 0x0227C000 to set AIPS3,
not the AIPS3 base address.
Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with
AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem.

Signed-off-by: Ye.Li <B37916@freescale.com>
2015-02-10 12:48:49 +01:00
Peng Fan
d9efd47c03 imx:mx6sx add dram io configure for mx6sx
Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs.
Add a new function mx6sx_dram_iocfg to configure dram io.

Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1
to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1
effects as "mmdc1->entry=value".

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-01-22 09:55:47 +01:00
Tom Rini
b4a0b4006f Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-02 07:42:58 -05:00
Peng Fan
b93ab2ee75 arm:mx6sx add QSPI support
Add QSPI support for mx6solox.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Peng Fan
eb412d79e4 imx:mx6 fix return value of mxc_get_clock
mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0xffffffff', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.

Also include an err message when unsupported mxc_clock type is passed
to mxc_get_clock.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-19 10:43:04 +01:00
Stefan Roese
7731745c13 arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)
As checkpatch complaines about these camel-case defines, lets change
them to only use upper-case characters.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-01 10:20:20 +01:00
Nikita Kiryanov
8d29cef588 arm: mx6: introduce disable_sata_clock
Implement disable_sata_clock for mx6 SoCs.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
2014-11-24 11:59:59 +01:00
Ye.Li
7a26416847 mx6: thermal: Check cpu temperature via thermal sensor
Add imx6 thermal device to mx6 soc file. Read the cpu temperature
using this device to access onchip thermal sensor.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
2014-11-21 15:30:12 +01:00
Nitin Garg
cf202d268b mx6: clock: Add thermal clock enable function
Add api to check and enable pll3 as required
for thermal sensor driver.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
2014-11-21 15:18:47 +01:00
Nikita Kiryanov
f2863ff3f4 arm: imx: make bmode command work with SPL/U-Boot combo
The bmode command forces the SoC to use a specific boot device
by writing its boot mode into SRC_GPR9, and notifying the SoC of
the change using SRC_GPR10[28] bit: if the bit is on, bootROM
uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine
the boot device.

SPL on the other hand is oblivious to this distinction, so once
the bootROM loads SPL from the device configured in SRC_GPR10,
SPL will attempt to load U-Boot from the device configured in
SRC_SMBR1, which is not updated by the bootROM to the value in
SRC_GPR9.

The result is that the selected boot device is not used across all
the boot stages.

Update spl_boot_device() to look at gpr9 when necessary.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
2014-11-12 09:03:54 +01:00
Tom Rini
625509ab0e Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-11-05 12:48:09 -05:00
Ye.Li
0f8ec145ba imx: mx6sl: Set the preclk clock source to OSC 24Mhz
For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the
preclk setting with kernel.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-03 11:21:49 +01:00
Ye.Li
e68661a32e imx: mx6: Change the get_ipg_per_clk for OSC 24Mhz source
For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix
the get_ipg_per_clk function to support it.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-03 11:21:49 +01:00
Tom Rini
0ce4af99c0 Merge branch 'master' of git://git.denx.de/u-boot-imx 2014-10-27 09:08:42 -04:00
Jeroen Hofstee
5624c6bd4e imx: add missing includes
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 15:27:35 -04:00
Eric Nelson
f6d48b29cb ARM: i.MX6: include prototype for get_board_rev()
Include <asm/bootm.h> to see the prototype for get_board_rev()
and prevent warning "Should it be static?" with "make C=1".

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2014-10-21 10:47:14 +02:00
Albert ARIBAUD
4b19b7448e Merge remote-tracking branch 'u-boot-imx/master'
The single file conflict below is actually trivial.

Conflicts:
	board/boundary/nitrogen6x/nitrogen6x.c
2014-10-08 21:20:49 +02:00
Ye.Li
9293d7fd50 imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset
Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR
register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source,
do not reset this PFD to avoid system hang. Customers may set this
in DDR script or use BT_FREQ to select low freq boot.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-29 10:24:07 +02:00
Masahiro Yamada
c79cba37b3 cosmetic: replace MIN, MAX with min, max
The macro MIN, MAX is defined as the aliase of min, max,
respectively.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-24 18:30:29 -04:00
Nitin Garg
36c1ca4d46 imx: Support i.MX6 High Assurance Boot authentication
When CONFIG_SECURE_BOOT is enabled, the signed images
like kernel and dtb can be authenticated using iMX6 CAAM.
The added command hab_auth_img can be used for HAB
authentication of images. The command takes the image
DDR location, IVT (Image Vector Table) offset inside
image as parameters. Detailed info about signing images
can be found in Freescale AppNote AN4581.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
2014-09-22 16:21:04 +02:00
Stefano Babic
3d8f1798ba imx: Fix build of mx6sxsabresd
Commit 224beb833e add clock
enabling function for FEC, but the masks are not available
for SX processor and the mx6sxsabresd cannot be built clean.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-11 10:13:44 +02:00
Fabio Estevam
1b8ad74a6f pcie_imx: Add mx6solox support
Let PCI on mx6solox also be supported.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 17:24:49 +02:00
Nikolay Dimitrov
2d59e3ecd2 mx6: Fix ECSPI typo in soc_boot_modes
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2014-09-09 16:47:43 +02:00
Ye.Li
4aa7ac30a7 iMX6: Disable the L2 before chaning the PL310 latency
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.

Signed-off-by: Ye.Li <Ye.Li@freescale.com>
2014-09-09 16:30:40 +02:00
Nikita Kiryanov
07ee927d2c arm: mx6: ddr: fix cs0_end calculation
Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.

This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.

Refactor the calculation.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:35:00 +02:00
Nikita Kiryanov
08155289a4 arm: mx6: ddr: configure MMDC for slow_pd
According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).

Configure MMDC for slow pd.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 15:35:00 +02:00
Nikita Kiryanov
06a51b8cc8 arm: mx6: ddr: do not write into reserved bit
Bit 16 in mapsr register is in a reserved field. Don't write to it.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:35:00 +02:00
Nikita Kiryanov
3368918f71 arm: mx6: ddr: cleanup
No functional changes.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:33:39 +02:00
Nikita Kiryanov
224beb833e mx6: add clock enabling functions
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:32:32 +02:00
Fabio Estevam
5c045cddaa mx6sx: Adjust enable_fec_anatop_clock() for mx6solox
Configure and enable the ethernet clock for mx6solox.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:14:09 +02:00
Marek Vasut
b299ab7435 ARM: mx6: Handle the MMDCx_MDCTL COL field caprices
The COL field value cannot be easily calculated from the desired
column number. Instead, there are special cases for that, see the
datasheet, MMDCx_MDCTL field description, field COL . Cater for
those special cases.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20 12:22:52 +02:00
Gabriel Huau
a76df70908 mx6: add support of multi-processor command
This allows u-boot to load different OS or Bare Metal application on
different cores of the i.MX6 SoC.
For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-20 11:52:54 +02:00
Heiko Schocher
a0ae0091d7 i.MX6: add enable_spi_clk()
add enable_spi_clk(), so board code can enable spi clocks.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:42 +02:00
Fabio Estevam
a3df99b50f mx6: soc: Do not apply the PFD erratum for mx6solox
The PFD issue is not present on mx6solox, so skip it in this case.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-23 12:25:40 +02:00
Fabio Estevam
d95b6ab87c mx6: clock: Do not enable sata and ipu clocks
mx6sx does not have sata nor ipu blocks, so do not handle such clocks.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Fabio Estevam
05d54b827f mx6: Add support for the mx6solox variant
mx6solox is the newest member of the mx6 family.

Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual Gigabit Ethernet

Add the initial support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Fabio Estevam
157f45da91 mx6: soc: Update the comments of set_ldo_voltage()
Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces
set_ldo_voltage() function that can be used to set the voltages
of any of the three LDO regulators controlled by the PMU_REG_CORE register.

Prior to this commit there was a single set_vddsoc() which only configured the
VDDSOC regulator.

Update the comments to align with the new set_ldo_voltage() implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-09 15:10:10 +02:00
Andre Renaud
2eb268f6fd MX6: Correct calculation of PLL_SYS
DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
the shift after the multiply to avoid rounding errors

Signed-off-by: Andre Renaud <andre@bluewatersys.com>
2014-07-09 14:55:30 +02:00
Stefano Babic
f2f07e8553 imx: correct HAB status for new chip TO
According to:

http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0

ENGR00287268 mx6: fix the secure boot issue on the new tapout chip
commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b

newer i.MX6 silicon revisions have an updated ROM and HAB API table.
Please see also:

i.MX Applications Processors Documentation
Engineering Bulletins
EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison

With this change the secure boot status is correctly displayed

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-06-17 17:45:09 +02:00
Tim Harvey
fe0f7f7842 mx6: add mmdc configuration for MX6Q/MX6DL
- add function for configuring iomux based on board-specific regs
- add function for configuring mmdc based on board-specific and
  chip-specific data

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-06-06 10:07:26 +02:00
Markus Niebel
adadc915b3 ARM: imx6: fix wrong fec clk
imx_get_fecclk() returns enet_ref instead of ipg.
Since the clock is used to calculate the prescaler
for the MDIO interface wrong values can be calculated.

Tested on a custom MX6S board with 100MBit interface

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
2014-02-11 11:31:52 +01:00
Fabio Estevam
6d73c23410 mx6: Enable L2 cache support
Add L2 cache support and enable it by default.

Configure the L2 cache in the same way as done by FSL kernel:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-02-11 11:24:12 +01:00
Fabio Estevam
94db665579 mx6: Distinguish mx6dual from mx6quad
Currently when we boot a mx6dual U-boot reports that it is a mx6quad.

Report it as MX6D instead:

CPU:   Freescale i.MX6D rev1.2 at 792 MHz

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2014-02-11 11:24:12 +01:00
Anson Huang
16197bb8ba imx6: make sure MMDC_CHx_MASK is clear to avoid warm reset failure
Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2),
it will cause warm reset fail, need to clear this MMDC_CHx_MASK field
to make sure all the i.MX6 series SOCs reset function work. Otherwise,
uboot "reset" command will fail, tested on i.MX6SL EVK board with TO1.2.

Signed-off-by: Anson Huang <b20788@freescale.com>
2014-02-11 11:24:01 +01:00
Anson Huang
5c92edc21c imx6: ensure AHB clock is 132MHz in low freq boot mode
For low freq boot mode(ARM boot up with 396MHz), ROM
will not set AHB clock to 132MHz, and the reset value of
AHB divider is incorrect which will lead to wrong AHB
rate, need to correct it. To enable low freq boot mode,
need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
SabreSD board and i.MX6SL EVK board.

Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
2014-02-11 11:17:10 +01:00
Marek Vasut
7981449280 ARM: mx6: Add PCI express clock configuration
Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
this code into separate function. Moreover, add the PCIe clock
enabling code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-01-26 12:41:20 +01:00
Fabio Estevam
be2a3bb39a mx6: Revert "mx6: soc: Disable VDDPU regulator"
Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang
for people using FSL kernel 3.0.35 and 3.10, so revert it for now.

Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Reported-by: Pierre Aubert <p.aubert@staubli.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-17 10:16:48 +01:00
Fabio Estevam
5f98d0b5d3 mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency
that will be generated.

No changes are made to mx6slevk, which uses the default 50MHz fec clock.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-15 10:33:25 +01:00
Christian Gmeiner
5a66016987 imx6: make use of lldiv(..)
Commit 762a88ccf8 introduces
a 64-bit division without using the lldiv() function,
which pulls in previously unused libgcc stuff.

Signed-off-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-13 11:52:28 +01:00
Otavio Salvador
c655b816e5 ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6
The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-03 15:44:05 +01:00
Fabio Estevam
0222982780 mx6: soc: Disable VDDPU regulator
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:51 +01:00
Fabio Estevam
39f0ac9347 mx6: soc: Add the required LDO ramp up delay
When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:51 +01:00
Fabio Estevam
3d622b78bd mx6: soc: Introduce set_ldo_voltage()
Introduce set_ldo_voltage() so that all three LDO regulators can be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:51 +01:00
Fabio Estevam
7e5e8c94a9 mx6: soc: Set the VDDSOC at 1.175 V
mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.

This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Fabio Estevam
e113fd1972 mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages
Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:

00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Fabio Estevam
fc740648bd mx6: soc: Staticize set_vddsoc()
set_vddsoc() is not used anywhere else, so make it static.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Frank Li
ebaf6b26bc imx6: fix random hang when download by usb
ROM did not invalidate L1 cache when download by usb
Need invalidate L1 cache before enable cache

Signed-off-by: Huang yongcai <b20788@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
2013-12-17 18:48:45 +01:00
Fabio Estevam
89cfd0f575 mx6: clock: Fix the calculation of PLL_ENET frequency
According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:

"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"

Current logic does not handle the 25MHz case correctly, so fix it.

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-12-17 18:38:42 +01:00
Albert ARIBAUD
85b8c5c4bf Merge branch 'iu-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/Makefile
	board/compulab/cm_t35/Makefile
	board/corscience/tricorder/Makefile
	board/ppcag/bg0900/Makefile
	drivers/bootcount/Makefile
	include/configs/omap4_common.h
	include/configs/pdnb3.h

Makefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:

	board/compulab/common/Makefile
	board/udoo/Makefile

include/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.

include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.

Note: 'git show' will also list two files just because
they are new:

	include/configs/am335x_igep0033.h
	include/configs/omap3_igep00x0.h
2013-11-09 22:59:47 +01:00
Masahiro Yamada
4e1aa8437a armv7: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Pierre Aubert
762a88ccf8 mx6: compute PLL PFD frequencies rather than using defines
Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
2013-10-17 09:44:20 +02:00
trem
fac9640895 i2c: mxc: move to new subsystem
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-10-17 07:20:24 +02:00
Pierre Aubert
a0a0dacfe8 mx6: Fix use of improper value in enable_ipu_clock
The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize
the CCGR3 register caused an undefined value for CG0.

Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-09-27 13:53:35 +02:00
Fabio Estevam
31f07964c8 mx6slevk: Add Ethernet support
mx6slevk has a SMSC8720 connected in RMII mode.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20 17:55:37 +02:00
Andrew Gabbasov
d55e0dabd7 mx6: Fix calculation of emi_slow clock rate
This is porting of Freescale's patch from version imx_v2009.08_3.0.35_4.0.0,
that fixes the obvious mistype of bits offset macro name (ACLK_EMI_PODF_OFFSET
was used instead of ACLK_EMI_SLOW_PODF_OFFSET).

Using the occasion, change the variable name 'emi_slow_pof' to more consistent
'emi_slow_podf'.

Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2013-09-10 18:22:27 +02:00
Eric Nelson
8467faef7f i.MX6: Set and clear the gating bits for Phase Fractional Dividers
This addresses silicon errata ERR006282 as described in this
document:
	https://community.freescale.com/docs/DOC-94581

Also implemented in Freescale's 2009.08-based release:

	http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/
	Commit id: b7c5badf94ffbe6cd0845efbb75e16e05e3af404

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-08-31 18:09:37 +02:00
Stefano Babic
b83c709e8d imx: add status reporting for HAB status
Add functions to report the HAB (High Assurance Boot) status
of e.g. i.MX6 CPUs.

This is taken from

git://git.freescale.com/imx/uboot-imx.git branch imx_v2009.08_3.0.35_4.0.0
cpu/arm_cortexa8/mx6/generic.c
include/asm-arm/arch-mx6/mx6_secure.h

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-08-31 15:06:29 +02:00
Stefano Babic
326ea986ac Merge git://git.denx.de/u-boot-arm
Conflicts:
	board/freescale/mx6qsabrelite/Makefile
	board/freescale/mx6qsabrelite/mx6qsabrelite.c
	include/configs/mx6qsabrelite.h

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-07-31 11:30:38 +02:00
Pardeep Kumar Singla
5ea7f0e328 mx6: Factor out common HDMI setup code
Instead of duplicating HDMI setup code for every mx6 board, factor out the common code

Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
2013-07-27 10:49:36 +02:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Benoît Thébaudeau
112fd2ec6c Add mxc_ocotp driver
Add an mxc_ocotp driver for i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:43 +02:00
Benoît Thébaudeau
8f3ff11c1f imx: Homogenize and fix fuse register definitions
IIM:
 - Homogenize prg_p naming (the reference manuals are not always self-consistent
   for that).
 - Add missing SCSx and bank registers.
 - Fix the number of banks on i.MX53.

OCOTP:
 - Rename iim to ocotp in order to avoid confusion.
 - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the
   reference manual.
 - Merge the existing spinoff gp1 fuse definition on i.MX6.
 - Fix the number of banks on i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-28 11:07:40 +02:00
Stefan Roese
ae695b18df mtd: mxs_nand: Add support for i.MX6
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:26:36 +02:00
Fabio Estevam
25b4aa146a mx6: Add solo-lite variant support
mx6 solo-lite is another member of the mx6 series.

For more information about mx6 solo-lite, please visit:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 09:57:44 +02:00
Fabio Estevam
38e7007725 mx6: Fix get_board_rev() for the mx6 solo case
When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev()
returns 0x62xxx, which is not a value understood by the VPU
(Video Processing Unit) library in the kernel and causes the video playback to
fail.

The expected values for get_board_rev are:
0x63xxx: For mx6quad/dual
0x61xxx: For mx6dual-lite/solo

So adjust get_board_rev() accordingly and make it as weak function, so that we
do not need to define it in every mx6 board file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-04-03 11:36:34 +02:00
Stephen Warren
8f3937761b ARM: mx6: use common CPU errata config options
Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.S, since it's just duplicated code now.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2013-03-07 18:20:37 +01:00
Fabio Estevam
76c91e668a mx6: Disable Power Down Bit of watchdog
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.

Comparing the watchdog behaviour on a revB versus revC board:

- On a mx6qsabresd revB:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...

- On a mx6qsabresd revC:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR

So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.

Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-02-12 13:54:34 +01:00
Fabio Estevam
2b16e51c2f mx6: Add workaround for ARM errata
Add workaround for the following ARM errata: 743622 and 751472.

The motivation for this change is the following kernel commit 62e4d357a
(ARM: 7609/1: disable errata work-arounds which access
secure registers), which removes the errata from multiplatform kernel.

Since imx has been converted to multiplatform in the kernel, we need to apply
such workarounds into the bootloader.

Workaround code has been taken from arch/arm/mm/proc-v7.S from 3.7.1 kernel.

Explanation of each erratum is provided at "Chip Errata for the i.MX 6Dual/6Quad"
document available at: cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-09 19:22:06 +01:00
Fabio Estevam
cc446726de mx6: clock: Only show CSPI clock if CSPI is enabled
If a board does not enable CSPI, there is no need to show the CSPI clock
frequency as part of the 'clock' command.

Reported-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
2012-11-19 08:49:00 +01:00
Troy Kisky
20332a066a mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
Previously, the same value was returned for both mx6dl and mx6solo.
Check number of processors to differeniate.
Also, a freescale patch says that sololite has its cpu/rev
stored at 0x280 instead of 0x260.
I don't have a sololite to verify.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-11-10 08:15:40 +01:00
Benoît Thébaudeau
833b6435de mx5/6: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:10 -07:00
Matthias Weisser
e7bed5c2b3 imx: Use MXC_I2C_CLK in imx i2c driver
i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using
MXC_I2C_CLK on all imx systems using i2c.

Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Eric Nelson
2af7e81015 i.MX6: get rid of redundant struct src_regs (dupe of struct src)
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:09 -07:00
Eric Nelson
0bb7e316f0 i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.

Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:

     http://patchwork.ozlabs.org/patch/185129/

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:08 -07:00
Troy Kisky
124a06d7fb imx-common/cmd_bmode.c: add imx bmode (bootmode) command
This is useful for forcing the ROM's
usb downloader to activate upon a watchdog reset.
Or, you can boot from either SD Card.

Currently, support added for MX53 and MX6Q
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Note: MX53 support untested.
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Troy Kisky
cc54a0f7cc imx-common: add i2c.c for bus recovery support
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:57 +02:00
Troy Kisky
18c0ad27c1 i.mx: iomux-v3.c: move to imx-common directory
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:32 +02:00
Troy Kisky
af2a35fb1f i.mx: iomux-v3.h: move to imx-common include directory
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:19 +02:00
Troy Kisky
d3394ec198 iomux-v3: remove include of mx6x_pins.h
This include is not needed.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-07-31 07:59:56 +02:00
Fabio Estevam
5427d29c26 No need to define CONFIG_ARCH_CPU_INIT.
All mx6 based boards should use arch_cpu_init().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:44 +02:00
Eric Nelson
64e7cdb5e8 i.MX6: add enable_sata_clock()
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:33 +02:00
Dirk Behme
cac833a98c i.MX6: Add ANATOP regulator init
Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.

Note: This should be but can't be done in the DCD. The bootloader
      prevents access to the ANATOP registers.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
2012-05-15 08:31:33 +02:00
Fabio Estevam
6a376046ef imx-common: Factor out get_ahb_clk()
get_ahb_clk() is a common function between mx5 and mx6.

Place it into imx-common directory.

Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:32 +02:00
Aneesh V
74236acacc armv7: add appropriate headers for assembly functions
Use ENTRY and ENDPROC with assembly functions to ensure
necessary assembler directives for all functions.

Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-05-15 08:31:26 +02:00
Eric Nelson
4d422fe2dc i.MX6: implement enable_caches()
disabled by default until drivers are fixed

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-04-16 14:53:58 +02:00
Fabio Estevam
a768386746 mx6: Read silicon revision from register
Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU:   Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
2012-03-27 09:41:16 +02:00
Wolfgang Grandegger
3f467529ca usb/ehci: Add USB support for the MX6Q
Currently, only USB Host 1 is supported.

Cc: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
2012-03-26 23:09:23 +02:00
Jason Liu
f2f7745825 imx: mx6q: add aipstz init for off platform periph
Init peripheral access control register of AIPSTZ OPACRx:

Buffer Writes(BW):      0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses.
Write Protect(WP):      0 -> allows write accesses.
Trusted Protect(TP):    0 -> allows unstrusted master

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:10 +01:00
Jason Liu
bd2e27c043 i.mx6:imx6q: allign MAC address with burned-in ordering
For the i.mx6q, the burned-in MAC address will be the following odering,

fuse: 0x620[7:0]   MAC_ADDR[7:0]     ---> mac[5]
fuse: 0x620[15:8]  MAC_ADDR[15:8]    ---> mac[4]
fuse: 0x620[23:16] MAC_ADDR[23:16]   ---> mac[3]
fuse: 0x620[31:24] MAC_ADDR[31:24]   ---> mac[2]
fuse: 0x630[7:0]   MAC_ADDR[39:32]   ---> mac[1]
fuse: 0x630[15:8]  MAC_ADDR[47:40]   ---> mac[0]

This patch also fix the error caculation for the fuse bank[0] address

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:09 +01:00
Fabio Estevam
be252b654a net: imx: Add multi-FEC support for imx_get_mac_from_fuse
Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.

This feature is important on mx28 SoC for example that has two FEC ports.

Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:09 +01:00
Jason Liu
ff167df51c i.mx: i.mx6q: Add the enet clock function
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:08 +01:00