Fabio Estevam 76c91e668a mx6: Disable Power Down Bit of watchdog ... On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able to reach the Linux prompt. Comparing the watchdog behaviour on a revB versus revC board: - On a mx6qsabresd revB: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: WDOG ... - On a mx6qsabresd revC: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR. Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and is also safe for all mx6 boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>		2013-02-12 13:54:34 +01:00
..
clock.c	mx6: clock: Only show CSPI clock if CSPI is enabled	2012-11-19 08:49:00 +01:00
lowlevel_init.S	mx6: Add workaround for ARM errata	2013-01-09 19:22:06 +01:00
Makefile	i.mx: iomux-v3.c: move to imx-common directory	2012-07-31 08:00:32 +02:00
soc.c	mx6: Disable Power Down Bit of watchdog	2013-02-12 13:54:34 +01:00