u-boot/arch/arm/cpu/armv7/mx6
Peng Fan a2c74aaf51 imx: mx6ul select SYS_L2CACHE_OFF
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:08 +02:00
..
clock.c imx:mx6ul add clock support 2015-08-02 11:05:07 +02:00
ddr.c arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specified 2015-05-19 15:22:53 +02:00
hab.c imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QP 2015-08-02 10:45:41 +02:00
Kconfig imx: mx6ul select SYS_L2CACHE_OFF 2015-08-02 11:05:08 +02:00
Makefile mx6: add support of multi-processor command 2014-08-20 11:52:54 +02:00
mp.c mx6: add support of multi-processor command 2014-08-20 11:52:54 +02:00
soc.c imx: mx6: ccm: Change the clock settings for i.MX6QP 2015-08-02 10:43:45 +02:00