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https://github.com/AsahiLinux/u-boot
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mx6: compute PLL PFD frequencies rather than using defines
Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de>
This commit is contained in:
parent
262f08d6ea
commit
762a88ccf8
2 changed files with 42 additions and 25 deletions
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@ -100,6 +100,32 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
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}
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/* NOTREACHED */
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}
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static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
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{
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u32 div;
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u64 freq;
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switch (pll) {
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case PLL_BUS:
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if (pfd_num == 3) {
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/* No PFD3 on PPL2 */
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return 0;
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}
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div = __raw_readl(&imx_ccm->analog_pfd_528);
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freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
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break;
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case PLL_USBOTG:
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div = __raw_readl(&imx_ccm->analog_pfd_480);
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freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
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break;
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default:
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/* No PFD on other PLL */
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return 0;
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}
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return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
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ANATOP_PFD_FRAC_SHIFT(pfd_num));
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}
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static u32 get_mcu_main_clk(void)
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{
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@ -144,13 +170,14 @@ u32 get_periph_clk(void)
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freq = decode_pll(PLL_BUS, MXC_HCLK);
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break;
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case 1:
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freq = PLL2_PFD2_FREQ;
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freq = mxc_get_pll_pfd(PLL_BUS, 2);
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break;
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case 2:
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freq = PLL2_PFD0_FREQ;
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freq = mxc_get_pll_pfd(PLL_BUS, 0);
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break;
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case 3:
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freq = PLL2_PFD2_DIV_FREQ;
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/* static / 2 divider */
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freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
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break;
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default:
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break;
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@ -184,7 +211,7 @@ static u32 get_ipg_per_clk(void)
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static u32 get_uart_clk(void)
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{
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u32 reg, uart_podf;
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u32 freq = PLL3_80M;
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u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
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reg = __raw_readl(&imx_ccm->cscdr1);
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#ifdef CONFIG_MX6SL
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if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
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@ -204,7 +231,7 @@ static u32 get_cspi_clk(void)
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reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
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cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
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return PLL3_60M / (cspi_podf + 1);
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return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
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}
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static u32 get_axi_clk(void)
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@ -217,9 +244,9 @@ static u32 get_axi_clk(void)
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if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
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if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
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root_freq = PLL2_PFD2_FREQ;
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root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
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else
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root_freq = PLL3_PFD1_FREQ;
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root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
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} else
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root_freq = get_periph_clk();
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@ -244,10 +271,10 @@ static u32 get_emi_slow_clk(void)
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root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
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break;
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case 2:
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root_freq = PLL2_PFD2_FREQ;
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root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
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break;
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case 3:
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root_freq = PLL2_PFD0_FREQ;
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root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
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break;
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}
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@ -270,13 +297,14 @@ static u32 get_mmdc_ch0_clk(void)
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freq = decode_pll(PLL_BUS, MXC_HCLK);
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break;
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case 1:
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freq = PLL2_PFD2_FREQ;
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freq = mxc_get_pll_pfd(PLL_BUS, 2);
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break;
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case 2:
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freq = PLL2_PFD0_FREQ;
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freq = mxc_get_pll_pfd(PLL_BUS, 0);
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break;
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case 3:
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freq = PLL2_PFD2_DIV_FREQ;
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/* static / 2 divider */
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freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
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}
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return freq / (podf + 1);
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@ -359,9 +387,9 @@ static u32 get_usdhc_clk(u32 port)
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}
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if (clk_sel)
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root_freq = PLL2_PFD0_FREQ;
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root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
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else
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root_freq = PLL2_PFD2_FREQ;
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root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
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return root_freq / (usdhc_podf + 1);
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}
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@ -890,15 +890,4 @@ struct mxc_ccm_reg {
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#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
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(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
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#define PLL2_PFD0_FREQ 352000000
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#define PLL2_PFD1_FREQ 594000000
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#define PLL2_PFD2_FREQ 396000000
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#define PLL2_PFD2_DIV_FREQ 200000000
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#define PLL3_PFD0_FREQ 720000000
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#define PLL3_PFD1_FREQ 540000000
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#define PLL3_PFD2_FREQ 508200000
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#define PLL3_PFD3_FREQ 454700000
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#define PLL3_80M 80000000
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#define PLL3_60M 60000000
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#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
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