Commit graph

8342 commits

Author SHA1 Message Date
Michal Simek
da872d7c13 net: gem: Fix return value from recv
recv function should return 0 instead of frame_len not to
proceed the same packet again in core.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Michal Simek
bcdfef7a26 net: gem: Setup default phy address to -1
Undefined phy address is -1 not 0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Nathan Rossi
04a44d3671 spi: zynq_qspi: Add configuration to disable LQSPI feature
When the Zynq Boot ROM code loads the payload from QSPI it uses the
LQSPI feature of the QSPI device, however it does not clean up its
configuration before handing over to the payload which leaves the device
confgured to by-pass the standard non-linear operating mode.

This ensures the Linear QSPI mode is disabled before re-enabling the
device.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:57 +01:00
Tom Rini
123b701779 Merge branch 'master' of git://git.denx.de/u-boot-usb 2015-12-17 21:46:04 -05:00
Alexey Brodkin
fee331f66c usb: add support of generic OHCI devices
This driver is meant to be used with any OHCI-compatible host
controller in case if there's no need for platform-specific
glue such as setup of controller or PHY's power mode via
GPIOs etc.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
2015-12-17 21:54:41 +01:00
Lukasz Majewski
70cc443d58 usb: host: ehci: samsung: Move hcor initialization after usb phy setup
With the old order of initialization the hcor pointer has been setup to
the same address as Exynos EHCI base address (0x12110000 instead of
0x12110010).
Such behaviour was caused by reading value of 0 instead of 0x10 from EHCI
HCCPBASE register without doing proper clock initialization before.

To fix this problem hcor initialization has been moved after USB PHY setup.
Now ehci_readl(&ctx->hcd->cr_capbase) returns correct value.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2015-12-17 21:54:41 +01:00
Marek Vasut
5d5716eebc usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.h
The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.

The rename is done automatically:
	$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
		`git grep "s3c_udc\.h" | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:41 +01:00
Marek Vasut
a4bb9b3636 usb: s3c-otg: Rename s3c_udc_probe() function
The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.

The rename is done automatically:
	$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
		`git grep s3c_udc_probe | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
c0982871df usb: s3c-otg: Rename struct s3c_plat_otg_data
The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.

The rename is done automatically:
	$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
		`git grep s3c_plat_otg_data | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
e30824f439 usb: s3c-otg: Rename USB_GADGET_S3C_UDC_OTG* to USB_GADGET_DWC2_OTG*
The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the
config option to make it less misleading. No functional change, just
a mechanical change done using the following script:

  git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \
  while read line ; do
    sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ;
  done

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
e179cedd09 usb: s3c-otg: Tweak the comments
The driver is actually for the Designware DWC2 controller.
Tweak the comments in the driver to reflect this fact.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
507e677bc4 usb: s3c-otg: Rename remaining macros
The driver is actually for the Designware DWC2 controller.
This patch renames the remaining S3C_* macros to match the
DWC2 naming.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
be5e4bdced usb: s3c-otg: Rename sources to dwc2_*c
The driver is actually for the Designware DWC2 controller.
This patch renames the local source files to dwc2_*c and
adjusts the Makefile to use the new names.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
f4d9bd06f7 usb: s3c-otg: Rename local headers to dwc2_*h
The driver is actually for the Designware DWC2 controller.
This patch renames the local header files to dwc2_*h and
adjusts the sources to use the new names.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
06cb6ccd8e usb: s3c-otg: Change the driver name to dwc2-udc
Just change the driver name.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
193979e2fe usb: s3c-otg: Zap useless externs
The extern statements are useless, remove them. Also remove the
extern ... controller, which is completely useless.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
155e740f73 usb: s3c-otg: Rename remaining local s3c_*() functions
The driver is actually for the Designware DWC2 controller.
This patch renames the remaining local s3c_*() functions
to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:39 +01:00
Marek Vasut
f52dd802cc usb: s3c-otg: Rename s3c_udc_*() functions
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
The function s3c_udc_probe() is a special case and is not
renamed by this patch yet.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:39 +01:00
Marek Vasut
ae1f2f0c4a usb: s3c-otg: Rename s3c_ep_*() functions
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:39 +01:00
Marek Vasut
28b9774808 usb: s3c-otg: Rename s3c_ep0_*() functions
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep0_*() functions to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:39 +01:00
Marek Vasut
de578e22d4 usb: s3c-otg: Staticize functions in s3c_udc_otg_xfer_dma.c
Just staticize the functions, they are not used outside of the file.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:39 +01:00
Marek Vasut
2f6560a146 usb: s3c-otg: Staticize s3c_udc_ep_set_stall
This function is local to s3c_udc_otg_xfer_dma.c , staticize it.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:39 +01:00
Marek Vasut
c056c52bbd usb: s3c-otg: Rename struct s3c_request
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_request to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:39 +01:00
Marek Vasut
627d929826 usb: s3c-otg: Rename struct s3c_ep
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_ep to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:39 +01:00
Marek Vasut
5f3a562a3b usb: s3c-otg: Rename struct s3c_dev_*_ep
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_dev_*_ep to reflect this.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:38 +01:00
Marek Vasut
1f99ab5c92 usb: s3c-otg: Rename struct s3c_usbotg_phy to dwc2_usbotg_phy
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy
to make things more obvious and clear.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:38 +01:00
Marek Vasut
2c12ff039c usb: s3c-otg: Split private bits from s3c_udc.h
Most of the functions are local to the s3c_udc driver, remove them
from the s3c_udc.h header to stop those bits from propagating all
over the place. Instead, move all the private stuff into new private
s3c_udc_otg_priv.h header.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:38 +01:00
Marek Vasut
014728133a usb: s3c-otg: Rename struct s3c_usbotg_reg to dwc2_usbotg_reg
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_reg to struct dwc2_usbotg_reg
to make things more obvious and clear.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:38 +01:00
Marek Vasut
b4d5cf0bc8 usb: s3c-otg: Rename struct s3c_udc to dwc2_udc
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_udc to struct dwc2_udc to make
things more obvious and clear.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:38 +01:00
Marek Vasut
1c84cc6e3b usb: s3c-otg: Rename regs-otg.h to s3c_udc_otg_regs.h
Rename the header file, so it's obvious which driver it's part of.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:38 +01:00
Tom Rini
9cddb4fe02 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-12-17 07:52:56 -05:00
Shaohui Xie
ea1332ceb4 net: fm: disables unused FM1-DTSEC1 MAC node in DTS
We don't disable unused FM1-DTSEC1 MAC node in FMAN v2 since it is
used by MDIO. For FMAN v3, MDIO uses dedicated controller, so we
can disable unused FM1-DTSEC1 MAC node to avoid being probed in
Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: revised commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:19 +08:00
Mingkai Hu
862d9296dd armv8/ls1043a: remove print info
Remove verbose message for FMan port.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
[York Sun: Added commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:18 +08:00
Stuart Yoder
509356224b driver: net: fsl-mc: remove MC firmware version check
The MC version numbers provide no meaningful information
about binary interface compatibility, so remove the
check which refuses to start the MC unless a specific
version is found.

Version checking is supposed to be done at the individual
object level, and individual drivers are responsible
for their own version checking.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:18 +08:00
Robert P. J. Day
535cce0f90 video: Typo cleanup in drivers/video/da8xx-fb.c
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2015-12-16 21:02:03 +01:00
Robert P. J. Day
a418f7e850 video: Clean up formatting, spelling mistakes in exynos_dp*
Aesthetic cleanup in drivers/video/exynos_dp*.[ch] files.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2015-12-16 20:59:22 +01:00
Tom Rini
35065cdd94 Merge git://git.denx.de/u-boot-rockchip 2015-12-16 14:50:03 -05:00
Tom Rini
e6e3faa5c2 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-12-14 20:27:23 -05:00
Aneesh Bansal
3a4800a596 drivers/crypto/fsl: fix endianness issue in RNG
For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
CC: Alex Porosanu <alexandru.porosanu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:35 +08:00
Alexander Stein
beedbc2ea0 fsl_qspi: Pet the watchdog while reading/writing
When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.

Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:33 +08:00
Yao Yuan
000f4e7686 move erratum a008336 and a008514 to soc specific file
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:32 +08:00
Tom Rini
b1f6be5ac8 qbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submit
With gcc-5.x we get a warning about the ambiguity of BUG_ON(!a != b) and
becomes BUG_ON((!a) != b).  In this case reading of the function leads to
us wanting to rewrite this as BUG_ON(a != b).

Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Cc: Haiying Wang <Haiying.Wang@freescale.com>
Cc: Roy Pledge <Roy.Pledge@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Shengzhou Liu
a46b1852de fsl/ddr: updated ddr errata-A008378 for arm and power SoCs
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
York Sun
6c6e006a20 driver/ddr/fsl: Update timing config for heavy load
In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
York Sun
7cc079989d driver/ddr/fsl: Update workaround for A008511 for vref range
The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
York Sun
8a51429e00 driver/ddr/fsl: Update MR5 RTT park
For four chip-selects enabled case, RTT is parked on all of them.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
York Sun
0fb7197436 driver/ddr/fsl: Update DDR4 MR6 for Vref range
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
York Sun
19601dd99c driver/ddr/fsl: Update DDR4 RTT values
DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
Sjoerd Simons
fc011f6402 mmc: mmc: Don't use sprintf when using tiny-printf
There is no sprintf implementation in tiny-printf, so don't try to use
it when tiny-printf if used.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2015-12-13 17:07:31 -07:00
Kamil Lulko
665624149a stm32: Convert serial driver to DM
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-12 15:56:08 -05:00
Tom Rini
5076c64a08 Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-12-11 15:07:44 -05:00
Michal Simek
76de51a6da spi: xilinx: Add new compatible strings
Add xlnx,xps-spi-2.00.a/b which is compatible string
listed in the Linux kernel.
Remove origin one which has no real background.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:24 +05:30
Jagan Teki
cba65a77c4 sf: Rename sf_ops.c to spi-flash.c
Since all spi-flash core operations are moved into
sf_ops.c then it's better to renamed as spi-flash.c

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:24 +05:30
Jagan Teki
339fd6dca5 sf: Use static for file-scope functions
Used static for file-scope functions in sf_probe.c

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:24 +05:30
Jagan Teki
bfdb07eb4b sf: sf_probe: Remove spi_slave pointer argument
Since spi_slave is a spi pointer in spi_flash{} then assign
spi_slave{} pointer to flash->spi and remove spi_slave
pointer argument to
- spi_flash_probe_slave
- spi_flash_scan

Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:24 +05:30
Jagan Teki
b6a2c436e0 sf: ops: Fix missing break on spansion read_bar
For assigning read_bar commands in spansion case, break
is missing this patch add that break.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:24 +05:30
Jagan Teki
aae00f8bab sf: Remove unneeded SST_BP and SST_WP
SST parts added on sf_params.c supports both SST_WR which consits
of both BP and WP and there is a spi controller ich which supports
only BP so the relevent _write hook set based on "slave->op_mode_tx"
hence there is no respective change required from flash side hance
removed these.

Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:24 +05:30
Jagan Teki
615879ac1a sf: Remove unneeded header includes
Removed unneeded header includes in sf_ops and sf_probe

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:24 +05:30
Jagan Teki
6f9d670d8e sf: Flash power up read-only based on idcode0
Using macro's for flash power up read-only access code
leads wrong behaviour hence use idcode0 for runtime
detection, hence the flash which require this functionality
gets detected at runtime.

Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:24 +05:30
Jagan Teki
cb37518516 sf: Use simple name for register access functions
Most of the register access function are static,
so used simple name to represent each.

Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
fc335d63b0 sf: Fix Makefile
This patch removes unneeded ifdef and fixed accordingly.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
6fa40e796c sf: Use static for file-scope functions
Use static for file-scope functions and removed
them from header files.

Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
0edae52f08 sf: probe: Code cleanup
- Move bar read code below the bar write hance both
  at once place, hence it easy for #ifdef macro only
  once and readable.
- Move read_cmd_array at top

Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
1e90d9fd31 sf: Move read_id code to sf_ops
read_id code is related to spi_flash stuff
hence moved to sf_ops.

Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
3847c0c180 sf: Move spi_flash_scan code to sf_ops
Intension is that sf_ops should deals all spi_flash
related stuff and sf_probe (which should renamed future)
should be an interface layer for spi_flash versus spi drivers.

sf_ops => spi_flash interface
sf_probe => interface layer vs spi_flash(sf_probe) to spi drivers

Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
3a1adb621b sf: spi_flash_validate_params => spi_flash_scan
Rename spi_flash_validate_params to spi_flash_scan
as this code not only deals with params setup but
also configure all spi_flash attributes.

And also moved all flash related code into
spi_flash_scan for future functionality addition.

Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Michal Simek
8e4920e53e spi: Kconfig: Fix correct target name for ZynqMP
ZynqMP is using different symbol.
Use correct one.

Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-11 22:12:23 +05:30
Michal Simek
23ef5aea84 spi: zynq_spi: Add cadence compatible string
Extend compatible list table for cdns,spi-r1p6 compatible string.

Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
cd337da21e spi: ti_qspi: Fix SPI_3WIRE checking using mode
SPI_3WIRE is spi mode not spi flags, so this patch fixed
the spi-3wire checking throgh mode instead of flags.

Cc: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
379b49d82e spi: Get spi-3wire from dts
spi-3wire is used when SI/SO signals shared so get
the same from dts node and assign to mode on slave
plat->mode.

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Tom Rini
f7a5f025ba Merge git://git.denx.de/u-boot-dm 2015-12-11 10:29:28 -05:00
Tom Rini
a5d4785ccb Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-12-11 09:06:51 -05:00
Michal Simek
0305be1087 Kconfig: i2c: Fix indentation
Use tabs instead of space for indentation.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-11 06:30:01 +01:00
Michal Simek
61d815a2cb Kconfig: i2c: Fix typo Suport -> Support
Fix typo in command description.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-11 06:29:54 +01:00
Stefan Roese
eb623b98c9 dm: serial: Minor coding style cleanup of some comments
Fix incorrect comment alignments.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-10 20:42:03 -07:00
Stefan Roese
7b98a3b676 dm: core: Fix Kconfig text to mention SPL in SPL_OF_TRANSLATE
Add a remark about SPL to this Kconfig option. Otherwise its identitcal
to the non-SPL version, which is confusing.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-12-10 20:41:56 -07:00
vishnupatekar
813c7372bb sunxi: power: axp818: add support for axp818 driver
AXP818 is rsb based PMIC and used on Allwinner A83T H8 Homlet dev board.
It's registers are different and calculating reg config is different than
that of earlier axp power ICs.

DCDC1, DCDC2, DCDC3 and DCDC5 is implemented at the moment.
all other voltages can be added subsequently.
AXP datasheet is uploaded to wiki:
http://linux-sunxi.org/File:AXP818_datasheet_Revision1.0.pdf

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10 11:14:22 +01:00
Bin Meng
789fa275b3 x86: Remove HAVE_ACPI_RESUME
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:56 +08:00
Bin Meng
4932443d26 x86: Move i8254_init() to x86_cpu_init_f()
Right now i8254_init() is called from timer_init() in the tsc timer
driver. But actually i8254 and tsc are completely different things.
Since tsc timer has been converted to driver model, we should find
a new place that is appropriate for U-Boot to call i8254_init(),
which is now x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:44 +08:00
Tom Rini
dcf4cb068e Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2015-12-07 08:13:02 -05:00
Michal Simek
8bebf03c73 dm: core: Enable SPL_SIMPLE_BUS by default
This option is needed for all SoCs which have nodes on bus. Without
enabling this drivers are not found and probed.
Issue was found on Zynq MMC probe.
Enable this option by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:30 +01:00
Michal Simek
c643f3ef9b serial: zynq: Remove duplicated header
debug_uart.h is included twice.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:30 +01:00
Michal Simek
6bf87dacd9 serial: zynq: Fix incorrect reference to s5p driver
Remove this c&p error from s5p driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:29 +01:00
Michal Simek
d9ae52c8f0 zynq: sdhci: Move driver to DM
Move driver to DM

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:29 +01:00
Michal Simek
400434537b zynq: sdhci: Remove zynq_sdhci_of_init()
Prepare for using DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Siva Durga Prasad Paladugu
b8a9bebeec zynq: sdhci: Calculate minimum frequency based on max frequency
Calculate the minimum sd clock based on max clock. This will
be done by add_sdhci() if we pass minimum clock as zero.
It also does based on SD host contoller version.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Michal Simek
b8de29feae net: gem: Enable CTRL+C in wait_for_bit
Enable to break waiting loop at any time.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-07 10:14:29 +01:00
Michal Simek
596e5782e7 net: gem: Move gem to Kconfig
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 10:14:28 +01:00
Michal Simek
3cdb1450de net: gem: Read information about interface from DT
Do not set interface via configs. Read information from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 10:14:28 +01:00
Michal Simek
6889ca7198 net: gem: Move driver to DM
- Enable DM_ETH by default for Zynq and ZynqMP
- Remove board_eth_init code
- Change miiphy_read function to return value instead of error code
  based on DM requirement
- Do not enable EMIO DT support by default

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-07 10:14:22 +01:00
Michal Simek
5a9284f7f5 net: gem: Fix miiphy_read name
Sync it with write function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:05 +01:00
Michal Simek
687d731263 net: gem: Remove zynq_gem_of_init()
This function was used for OF init before DM.
Remove this function as the part of move to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:05 +01:00
Michal Simek
c8e29271b1 net: gem: Enable MDIO bus earlier
Enable access to MDIO before zynq_gem_init is called.
It enables read information about phy earlier.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:05 +01:00
Michal Simek
90c6f2e21b net: gem: Check if priv->phydev is valid
Check return value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:05 +01:00
Michal Simek
68cc3bd8b2 net: gem: Extract phy init code
Move phy init code out of zynq_gem_init. DM drivers are normally calling
this code from probe function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
64a7ead64b net: gem: Remove phydev variable
Resort code to use priv->phydev variable directly.
It will simplify move to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
f2fc27684f net: gem: Change mii function not to use eth_device structure
Next step to move driver to driver model. Do not use eth_device
structure. Use private structure instead.
Add iobase to private structure to store gem iobase.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
3fac27243c net: gem: Change mdio_wait prototype to pass regs
Pass regs instead of dev because this will be chagned by
driver model.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
b904725a11 net: gem: Do not continue if phy is not found
Add return value for phy detection algorithm to stop init function when
phy is not found.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:04 +01:00
Tom Rini
25ef4bea59 Merge git://git.denx.de/u-boot-nios 2015-12-06 21:53:18 -05:00
Tom Rini
2311335d4c Merge git://git.denx.de/u-boot-usb 2015-12-06 21:52:40 -05:00
Marek Vasut
c35ed77a78 mmc: dwmmc: socfpga: Convert to DM
Convert the SoCFPGA shim for registering the DWMMC driver to DM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2015-12-07 00:15:59 +01:00
Marek Vasut
6af4e2782d usb: xhci: zynqmp: Removing unused function usb_phy_reset
This patch removes unsued function usb_phy_reset, rather common function
dwc3_phy_reset is used.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-07 00:15:00 +01:00
Rajesh Bhagat
565b7f0fe1 usb: xhci: fsl: Removing unused function usb_phy_reset
This patch removes unsued function usb_phy_reset, rather common function
dwc3_phy_reset is used.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
2015-12-07 00:15:00 +01:00
Rajesh Bhagat
5955bb9345 usb: xhci: dwc3: Adding reset delay requirement as per dwc3 databook
As per dwc3 databook, delay is required before taking the core out of reset.
This delay is required so that the PHY are stable, and then we can take core
out of reset.

Reference is taken from linux dwc3 code, file: drivers/usb/dwc3/core.c.

Signed-off-by: Sriram Dash <sriram.dash@freescale.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
2015-12-07 00:15:00 +01:00
Alexey Brodkin
90fbb2823a usb: add support for generic EHCI devices
This driver is meant to be used with any EHCI-compatible host
controller in case if there's no need for platform-specific
glue such as setup of controller or PHY's power mode via
GPIOs etc.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
2015-12-07 00:14:59 +01:00
Marek Vasut
40c920821d sunxi: usb: Rename the sunxi usb driver DM entry
The DM entry should be unique, otherwise it will collide with other
drivers. Fix this by assigning the driver a more unique name than
usb_ehci.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Simon Glass <sjg@chromium.org>
2015-12-07 00:14:59 +01:00
Marek Vasut
04f378798d usb: zynqmp: Fix build warnings
The driver does "return 0" in function with void type.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2015-12-07 00:14:59 +01:00
Felipe Balbi
c2ad4e1b9f usb: dwc3: fix build warnings
fix the following build warnings:

drivers/usb/dwc3/core.c: In function ‘dwc3_uboot_init’:
drivers/usb/dwc3/core.c:625:6: warning: ‘dev’ is used uninitialized in this function [-Wuninitialized]
mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
        ^
drivers/usb/dwc3/dwc3-omap.c: In function ‘dwc3_omap_uboot_init’:
drivers/usb/dwc3/dwc3-omap.c:380:7: warning: ‘dev’ is used uninitialized in this function [-Wuninitialized]
omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);

Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-12-07 00:14:59 +01:00
Felipe Balbi
9dc522249a usb: host: xhci-omap: fix build break
Fix the following build break:

drivers/usb/host/xhci-omap.c:35:5: error: ‘board_usb_init’ aliased to external symbol ‘__board_usb_init’
 int board_usb_init(int index, enum usb_init_type init)
      ^

Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-12-07 00:14:59 +01:00
Siva Durga Prasad Paladugu
f4dd69ca82 usb: zynqmp: Add XHCI driver support
Added USB XHCI driver support for zynqmp.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2015-12-07 00:14:59 +01:00
Thomas Chou
f118fe5cf9 altera_qspi: fix erase and write error code
Fix erase and write error code, which should be "protected".

From the "Embedded Peripherals IP User Guide" of Altera,

The "Illegal write" flag indicates that a write instruction is
targeting a protected sector on the flash memory. This bit is
set to indicate that the IP has cancelled a write instruction.

The "Illegal erase" flag indicates that an erase instruction has
been set to a protected sector on the flash memory. This bit is
set to indicate that the IP has cancelled the erase instruction.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-12-06 11:31:29 +08:00
Thomas Chou
421f306f2c altera_qspi: add lock unlock ops
Add lock() and unlock() mtd ops to altera_qspi.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-12-06 11:31:25 +08:00
Simon Glass
b7e5a6439f dm: serial: ns16550: Add pre-reloc flag to the driver
For platforms that don't use device tree in SPL the only way to mark this
driver as 'required by relocation' is with the DM_FLAG_PRE_RELOC flag. Add
this to ensure that the driver is bound.

Fixes: fde7e18938 ("dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
2015-12-05 18:22:38 -05:00
Nishanth Menon
9cb05a8f9f drivers: remoteproc: rproc-uclass: Fix check for NULL pointers
Neither uc_pdata->name nor check_name are supposed to be NULL in
_rproc_name_is_unique(). if uc_pdata->name is NULL, we are not
intialized yet, however if check_data is NULL, we do not have
proper data. Further, if either were NULL, strlen will crap out
while attempting to derefence NULL.

Instead, just check if either of these are NULL and bail out.

This should also fix the following coverity scan warnings:
*** CID 132281:  Null pointer dereferences  (FORWARD_NULL)
/drivers/remoteproc/rproc-uclass.c: 73 in _rproc_name_is_unique()

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-12-05 18:22:32 -05:00
Kamil Lulko
5be9356926 Change e-mail address of Kamil Lulko
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
2015-12-05 18:22:32 -05:00
Thomas Chou
80e0614670 ns16550: change reg-shift property default to zero
Change reg-shift property default to zero. When the integer property
is missing, it should be taken as zero. This is consistent to Linux
drivers/tty/serial/of_serial.c.

The x86 and most powerpc use reg-shift of 0. Most others use reg-shift
of 2. While reg-shift of 1 is rarely used.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-05 18:22:29 -05:00
Vagrant Cascadian
1b25e586cb Fix typo: firstly -> first.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Marek Vasut <marex@denx.de>
2015-12-05 18:22:23 -05:00
Vagrant Cascadian
3f42dc87b4 Fix typo: commmand -> command.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-05 18:22:21 -05:00
Tom Rini
9eed48c8be Merge branch 'master' of http://git.denx.de/u-boot-sparc 2015-12-04 17:50:34 -05:00
Tom Rini
a85670e40d Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-12-04 08:21:28 -05:00
Francois Retief
78536bc4d3 sparc: Use microseconds instead of ticks for timeout
We now use the generic delay method which specifies the timeout as
microseconds instead of ticks.

Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03 13:15:49 +02:00
huang lin
2863724831 rockchip: mmc: get the fifo mode and fifo depth property from dts
rk3036 mmc do not have internal dma, so we use fifo mode when read
and write data, we get the fifo mode and fifo depth property from
dts, pass to dw_mmc driver.

Signed-off-by: Lin Huang <hl@rock-chips.com>
2015-12-01 08:07:22 -07:00
huang lin
ace2198b7c rockchip: mmc: use non-removable property to distinguish emmc and sdcard register
emmc and sdcard have different register address, use non-removeable property
to distinguish them.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
a65f51b978 mmc: dw_mmc: support fifo mode in dwc mmc driver
some soc(rk3036 etc) use dw_mmc but do not have internal dma,
so we implement fifo mode to read and write data.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
f382eb833a mmc: dw_mmc: move data transfer as a separate function
the data transfer seem to long in the dwmci_send_cmd function,
so move this block as a separate funciton.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
49ecaa928f rockchip: rk3036: Add pinctrl driver
Add a driver which support pin multiplexing setup for rk3036

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
3f2ef13924 rockchip: rk3036: Add clock driver
Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
a51dbebf30 rockchip: serial driver support rk3036
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
41c7f664b9 dm: core: Add SPL Kconfig for REGMAP and SYSCON
Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can
remove from SPL stage.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Simon Glass
3ba5f74a54 dm: pci: Disable PCI compatibility functions by default
We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01 06:26:38 -07:00
Simon Glass
011e948295 dm: pci: Move common auto-config functions to a common file
Some functions will be used by driver model and legacy PCI code. To avoid
duplication, put these in a separate, shared file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01 06:26:37 -07:00
Simon Glass
76a8b6a58a dm: pci: Rename pci_auto.c to pci_auto_old.c
This file should not be used with driver model as it has lots of legacy/
compatibility functions. Rename it to make this clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01 06:26:37 -07:00
Simon Glass
e81ca88451 dm: tegra: pci: Convert tegra boards to driver model for PCI
Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01 06:26:36 -07:00
Simon Glass
f9260336d0 dm: pci: Add a function to find the regions for a PCI bus
This function looks up the controller and returns a pointer to each region
type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01 06:26:36 -07:00
Simon Glass
9f60fb0db4 dm: pci: Add a function to get the controller for a bus
A PCI bus may be a bridge device where the controller is the bridge's
parent. Add a function to return the controller device, given a PCI device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01 06:26:36 -07:00
Simon Glass
9289db6c60 dm: pci: Add functions to emulate 8- and 16-bit access
Provide a few functions to support using 32-bit access to emulate 8- and
16-bit access.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01 06:26:36 -07:00
Simon Glass
9526d83ac5 dm: pci: Support decoding ranges with duplicate entries
At present we add a new resource entry for every range entry. But some range
entries refer to configuration regions. To make this work, avoid adding two
regions of the same type. The later ranges will overwrite the earlier
(configuration) ones.

There does not seem to be a way to distinguish the configuration ranges
other than by ordering (as per the device tree binding).

We could perhaps instead just store one region of each type in a simple
array. Once we are sure that we don't need to support multiple regions, we
could change this. It would be easier to do it when all drivers are
converted to use driver model for PCI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01 06:26:36 -07:00
Simon Glass
2084c5af6d dm: pci: Set up the SDRAM mapping correctly
SDRAM doesn't always start at 0. Adjust the region mapping so that it works
on platforms where SDRAM is somewhere else.

This needs testing on other platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01 06:26:36 -07:00
Simon Glass
fde7e18938 dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
Move this option to Kconfig and fix up all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01 06:26:36 -07:00
Bin Meng
7030f27ef3 x86: tsc: Move tsc_timer.c to drivers/timer
To group all dm timer drivers together, move tsc timer to
drivers/timer directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
9ca07ebbac dm: timer: Support 64-bit counter
There are timers with a 64-bit counter value but current timer
uclass driver assumes a 32-bit one. Modify timer_get_count()
to ask timer driver to always return a 64-bit counter value,
and provide an inline helper function timer_conv_64() to handle
the 32-bit/64-bit conversion automatically.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
f838f12452 timer: sandbox: Use device tree to pass the clock frequency
We should use device tree to pass the clock frequency of the timer
instead of hardcoded in the driver codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
9e360a5c9c timer: altera: Remove the codes to get clock frequency
Since we have timer uclass to get clock frequency for us, remove
the custom version in the altera timer driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
579eb5a0cc dm: timer: Implement pre_probe()
Every timer device needs to have a valid clock frequency and it
can be specified in the device tree. Use pre_probe() to get this
in the timer uclass driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
435ae76edd dm: timer: Fix several nits
This changes 'Timer' to 'timer' at several places.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Tom Rini
4a421a67b6 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-11-30 18:13:10 -05:00
Wenyou Yang
2c62c56a86 gpio: atmel: Add the PIO4 driver support
The PIO4 is introduced from SAMA5D2, as a new version
for Atmel PIO controller.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2015-11-30 22:27:52 +01:00
Tom Rini
1670c8c219 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-11-30 15:18:30 -05:00
Shaohui Xie
f8642ba6dd net: phy: added aquantia PHY AQR405 support
The phy can share driver with other aquantia PHYs, so we only
add PHY ID.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:13 -08:00
York Sun
da305b9f57 drivers/ddr/fsl: Fix typo in BIST test for DDR4
BIST test code has a typo, resulting the binding registers not
maintained as expected. This typo results BIST runs twice on
the covered memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-11-30 09:11:12 -08:00
York Sun
61bd2f75f5 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Mingkai Hu
af523a0d56 pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Prabhakar Kushwaha
06b5301043 armv8: ls2085a: Add support of LS2085A SoC
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:10:47 -08:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Prabhakar Kushwaha
14480454c7 driver: net: ldpaa: Fix Rx buffer alignment
MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted
in several combinations of buffer size and frame offsets.
Workaround: Use buffers that are of size that is a multiple of 256, and
frame offset that is a multiple of 256"

Updating the DPNI Eth driver to comply with the restriction.

Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
5038d3e5f2 driver: net: ldpaa: Add debug information
Add following debug information in the driver
 - Get various DPNI counter values
 - Get link status of DPNI objects
 - Get information of both ends of connection (DPMAC - DPNI)

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
c919ab9ee5 driver: net: ldpaa: Use DPMAC as net device
As per current implementation of DPAA2 ethernet driver DPNI is used as
net device. DPNI is tangible objects can be multiple connected to same physical lane.

Use DPMAC as net device where it represents physical lane.
Below modification done in driver
 - Use global DPNI object
 - Connect DPMAC to DPNI
 - Create and destroy DPMAC

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
1730a17db9 driver: net: fsl-mc: Create DPAA2 object at run-time
Freescale's DPAA2 ethernet driver depends upon the static DPL for the
DPRC, DPNI, DPBP, DPIO objects.

Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
fb4a87a737 driver: net: fsl-mc: Add DPAA2 commands to manage MC
Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.

Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
553d2751c1 driver: net: fsl-mc: Increase MC command timeout
dpni_create API take takes more time as comapred to existing supported
APIs of MC Flib.
So increase MC command timeout.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
f9127a046d driver: ldpaa: Add api to return linked PHY ID of DPMAC
DPMAC represents physical line on the board. This physical
line eventually asscociate with on-board PHY.

So Add an api to return linked PHY ID of DPMAC object.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
872d48a777 driver: net: fsl-mc: Add APIs for DPMAC objects in FLIB
DPMAC object of Management complex controls Physical MAC and MDIO controller.
It provides APIs for MDIO and link state updates. It also provides APIs for
PHY/link configuration.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
1ebbe4fcf7 driver: net: fsl-mc: Add create, destroy APIs in flibs
Current Management Complex Flibs does not support APIs for adding and
destroying the objects.

Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
99e904c1f0 armv8: lsch3: Fix lane protocol parsing logic
Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.

Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Tom Rini
2a8696dfc2 Merge git://git.denx.de/u-boot-socfpga 2015-11-30 08:30:14 -05:00
Chin Liang See
9a41404dc6 mmc: socfpga_dw_mmc: Move drvsel and smplsel to dts
socfpga_dw_mmc driver will obtain the drvsel and
smplsel value from device tree instead of definition
in config header file.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-11-30 13:30:19 +01:00
Tom Rini
c1924d85af Merge branch 'master' of git://git.denx.de/u-boot-video 2015-11-30 07:10:18 -05:00
Peng Fan
3dbdb4dd4f video: ipu: fix out of bounds access
We need to access reg stp_rep9, but not stp_rep[(9 - 1) / 2].
If using "__raw_writel(0, DI_STP_REP(disp, 9))", this will exceeds
the size of stp_rep array.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Liu Ying <Ying.Liu@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
2015-11-30 09:18:36 +01:00
Peng Fan
cd8f09d9d7 video: ipu: simplify if else code
Simplify if/else code, since if channel equals to MEM_BG_SYNC or
MEM_FG_SYNC, we have value 5 for 'dc_chan'.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-11-25 09:52:18 +01:00
Marcel Ziswiler
b4bd655493 pci: fix address range check in __pci_hose_phys_to_bus()
The address range check may overflow if the memory region is located at
the top of the 32-bit address space. This can e.g. be seen on TK1 if
using the E1000 gigabit Ethernet driver where start and size are both
0x80000000 leading to the following messages:

Apalis TK1 # tftpboot $loadaddr test_file
Using e1000#0 device
TFTP from server 192.168.10.1; our IP address is 192.168.10.2
Filename 'test_file'.
Load address: 0x80408000
Loading: pci_hose_phys_to_bus: invalid physical address

This patch fixes this by changing the order of the addition vs.
subtraction in the range check just like already done in
__pci_hose_bus_to_phys().

Reported-by: Ivan Mercier <ivan.mercier@nexvision.fr>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-23 11:01:52 -05:00
Heiko Schocher
f300dccde4 i2c, avr32: fix compiler warning "input is not relaxable"
compiling U-Boot for avr32 boards shows since
commit 3d1957f0ea "dm: i2c: Add support for multiplexed I2C buses"
this warning:

Building current source for 4 boards (4 threads, 8 jobs per thread)
     avr32:  +   atstk1002
+(atstk1002) drivers/i2c/built-in.o: warning: input is not relaxable
     avr32:  +   grasshopper
+(grasshopper) drivers/i2c/built-in.o: warning: input is not relaxable
     avr32:  +   atngw100
+(atngw100) drivers/i2c/built-in.o: warning: input is not relaxable
     avr32:  +   atngw100mkii
+(atngw100mkii) drivers/i2c/built-in.o: warning: input is not relaxable
    0    4    0 /4      0:00:16  : atngw100mkii

Fix it.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Roger Meier <r.meier@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-23 14:47:48 +01:00
Tom Rini
80d307d115 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-11-22 08:20:03 -05:00
Jens Kuske
1c27b7dcd0 sunxi: Add basic H3 support
Add initial sun8i H3 support, only uart + mmc are supported for now.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-11-22 11:30:59 +01:00
Siarhei Siamashka
6047a3a9c9 sunxi: musb: Implement dfu_usb_get_reset()
This is necessary to distinguish between the "dfu-util --detach" and
the "dfu-util --reset" requests.

The default weak implementation of dfu_usb_get_reset() unconditionally
reboots the device, but we want to be able to continue the boot.scr
execution after writing the kernel, fdt and ramdisk to RAM via DFU.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-11-22 11:30:59 +01:00
Thomas Chou
9e39003e7f ns16550: move CONFIG_SYS_NS16550 to Kconfig
Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-21 21:50:18 -05:00
Thomas Chou
4fb6055211 ns16550: zap CONFIG_NS16550_SERIAL
Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers
is completed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:17 -05:00
Thomas Chou
c7b9686d5d ns16550: unify serial_omap
Unify serial_omap, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:17 -05:00
Thomas Chou
1874626b2b ns16550: unify serial_tegra
Unify serial_tegra, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:16 -05:00
Thomas Chou
ace59da137 ns16550: unify serial_dw
Unify serial_dw, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:16 -05:00
Thomas Chou
fcd3367ce9 ns16550: unify serial_keystone
Unify serial_keystone, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:15 -05:00
Thomas Chou
98a51fc3d7 ns16550: unify serial_rockchip
Unify serial_rockchip, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21 21:50:15 -05:00
Thomas Chou
f27445cbdc ns16550: unify serial_ppc
Unify serial_ppc, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add TODO comment]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-21 21:50:04 -05:00
Thomas Chou
81cd63a991 ns16550: unify serial_x86
Unify serial_x86, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-20 20:41:30 -05:00
Thomas Chou
8e62d32e5b ns16550: add generic binding to unify the drivers
Add generic binding to unify ns16550 drivers. There are
several drivers using almost the same code, such as serial_dw,
serial_keystone, serial_omap, serial_ppc, serial_rockchip,
serial_tegra.c, and serial_x86. But each is platform specific.

The key difference between these drivers is the way to get
input clock frequency. With this unified approach, fixed clock
frequency should be extracted from "clock-frequency" property of
device tree blob. If this property is not available, the macro
CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a
function to get clock, eg, get_serial_clock().

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-20 20:41:29 -05:00
Thomas Chou
77d7b5cd40 ns16550: change map_sysmem to map_physmem
Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem()
can be used to map system memory, it might be wrong to use it for I/O
ports.  The map_physmem() serves the same purpose to translate physical
address to virtual address with the additional flag to take care of cache
property. Most drivers use map_physmem() since I/O ports access should be
uncached. As ns16550 is a driver, it should use map_physmem() rather
than map_sysmem().

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-20 20:41:29 -05:00
Thomas Chou
b1e361b605 debug_uart: restore ns16550 as default
Since commit 220e8021af ("nios2: convert altera_jtag_uart to
driver model"), the default debug uart was changed. Most people
use ns16550 UART, so restore it as default.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reported-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reported-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-20 20:41:28 -05:00
Simon Glass
d8a26f0300 usb: sandbox: Add a USB emulation driver
Add a simple USB keyboard driver for sandbox. It provides a function to
'load' it with input data, which it will then stream through to the normal
U-Boot input subsystem. When the input data is exhausted, the keyboard stops
providing data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:52 -07:00
Simon Glass
b70a3fea94 usb: sandbox: Add support for interrupt operations
Allow USB device emulation to support interrupt URBs so that we can use USB
keyboards with sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:52 -07:00
Simon Glass
eae11bece6 dm: usb: Remove inactive children after a bus scan
Each scan of the USB bus may return different results. Existing driver-model
devices are reused when found, but if a device no longer exists it will stay
around, de-activated, but bound.

Detect these devices and remove them after the scan completes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:52 -07:00
Simon Glass
e8ea5e8c85 dm: usb: Deprecate usb_get_dev_index()
This function should not be used with driver model. While there are users
of USB Ethernet that use driver model for USB but not Ethernet, we have
to keep it around. Add a comment to that effect.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:52 -07:00
Simon Glass
79725ca4f6 Revert "dm: Export device_remove_children / device_unbind_children"
This reverts commit bb52b367f6.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:51 -07:00
Simon Glass
ba94e83911 Revert "dm: usb: Use device_unbind_children to clean up usb devs on stop"
This reverts commit 6cda369509.

We want to avoid having the USB stack rely on unbind.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:51 -07:00
Simon Glass
1b6a1dff71 Revert "dm: usb: Rename usb_find_child to usb_find_emul_child"
This reverts commit 9b510df703.

We want to avoid having the USB stack rely on unbind.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:51 -07:00
Simon Glass
af9c7c11e9 sandbox: usb: Allow finding a USB emulator for a device
Each USB device has an emulator. Currently this can only be found by
supplying the 'pipe' value, which contains the device number. Add a way
to find it directly from the emulated device.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:51 -07:00
Simon Glass
80438a6c71 sandbox: usb: Allow up to 4 emulated devices on a hub
To support more advanced testing, support 4 devices instead of 2.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:51 -07:00
Simon Glass
c4876320db sandbox: usb: Allow dynamic emulated USB device descriptors
We would like the serial number to come from the device tree node name of
the emulated device. This avoids them all having the same name. Adjust the
code to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:51 -07:00
Simon Glass
24b852a7a2 Move console definitions into a new console.h file
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:50 -07:00
Daniel Schwierzeck
3f51a772d4 sandbox: cros_ec: fix uninitialized use of len
Building with gcc-5.2 raises this warning:

drivers/misc/cros_ec_sandbox.c: In function cros_ec_sandbox_packet:
drivers/misc/cros_ec_sandbox.c:483:5: warning: len may be used uninitialized in this function [-Wmaybe-uninitialized]
  if (len < 0)
     ^

If the function process_cmd() is called with
req_hdr->command == EC_CMD_ENTERING_MODE, the value of len will be
returned uninitialized.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:13:42 -07:00
Bin Meng
e5f330c482 input: Ban digit numbers if 'Num Lock' is not on
When 'Num Lock' is not on, we should not send these digit numbers
(0-9 and dot) to the output buffer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:13:42 -07:00