Commit graph

8342 commits

Author SHA1 Message Date
Bin Meng
ed3021af5c serial: lpuart: Call local version of setbrg and putc directly
There is no need to go through serial driver subsystem, instead
call the driver's setbrg and putc routines directly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:10:14 -07:00
Bin Meng
47f1bfca40 serial: lpuart: Fix several cosmetic issues
Clean up the driver codes a little bit, by:
- Use tab instead of space in the macro defines
- Use single line comment whenever possible
- Fix insertion of blank lines

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:10:14 -07:00
Bin Meng
5ed07cf53c serial: lpuart: Move CONFIG_FSL_LPUART to Kconfig
LPUART is seen on Freescale VF610 and QorIQ Layerscape devices.
Create a Kconfig option and move it to defconfig for all boards
that have this serial driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:10:14 -07:00
Masahiro Yamada
f0e075162f clk: add API to enable clock
The most basic thing for clock is to enable it, but it is missing
in this uclass.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:23 -07:00
Masahiro Yamada
9e52126f34 clk: add static qualifier to local functions
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:23 -07:00
Masahiro Yamada
8138581866 clk: move Kconfig options into sub-menu
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:23 -07:00
Stephen Warren
bb883f824c timer: sandbox: work without device tree
A default invocation of sandbox U-Boot apparently uses no device tree,
which means that no timer is registers, which in turn means that the
sleep shell command hangs.

Fix the sandbox timer code to register a device when there's no DT, just
like e.g. the sandbox reset driver does. When there's no DT, the DM uclass
can't initialize clock_rate from DT, so set a default value in the
timer code instead.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:23 -07:00
Stephen Warren
0a7edce0ef dm: timer: refuse timers with zero clock_rate
If a timer has a zero clock_rate, get_tbclk() will return zero for it,
which will cause tick_to_time() to perform a division-by-zero, which will
crash U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:23 -07:00
Simon Glass
20af3c0a00 dm: core: Call uclass post_bind() after the driver's bind() method
At present the uclass's post_bind() method is called before the driver's
bind() method. This means that the uclass cannot use any of the information
set up by the driver. Move it later in the sequence to permit this.

This is an ordering change which is always fairly major in nature. The main
impact is that devices which have children will not see them appear in their
bind() method. From what I can see, existing drivers do not look at their
children in the bind() method, so this should be safe.

Conceptually this change seems to result in a 'more correct' ordering, since
the uclass (which is broader than the device) gets the last word.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-20 19:06:22 -07:00
Simon Glass
5589a81829 pinctrl: Avoid binding all pinconfig nodes before relocation
This can create a large number of pinctrl devices. It chews up early
malloc() memory and takes time. Only bind those which are marked as needed
before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:22 -07:00
Simon Glass
4a1db6d8ab dm: mmc: Try to honour the sequence order
At present we add driver-model MMC devices in the order we find them. The
'alias' order is not honoured.

It is difficult to fix this for the case where we have holes in the
sequence. But for the common case where the devices are numbered from 0
without any gaps, we can add the devices to the internal data structures
in this order.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:22 -07:00
Simon Glass
4dc5259ac7 dm: gpio: Allow the uclass to work without printf()
For SPL we don't really need sprintf() and with tiny-printf this is not
available. Allow this to be dropped in SPL when using tiny-printf.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:22 -07:00
Mugunthan V N
dadf31375a drivers: timer: omap_timer: add timer driver for omap devices based on dm
Adding a timer driver for omap devices based on driver model
and device tree.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-01-20 19:06:21 -07:00
Mugunthan V N
a5d801130c dm: timer: uclass: Add flag to control sequence numbering
Like SPI and I2C, timer devices also have multiple chip
instances. This patch adds the flag 'DM_UC_FLAG_SEQ_ALIAS' in
timer_uclass driver to control device sequence numbering.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:21 -07:00
Mugunthan V N
c833697538 dm: timer: uclass: add timer init in uclass driver to add timer device
Adding timer init function in timer-uclass driver to create and
initialize the timer device on platforms where u-boot,dm-pre-reloc
is not used. Since there will be multiple timer devices in the
system, adding a tick-timer node in chosen node to know which
timer device to be used as tick timer in u-boot.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-01-20 19:06:21 -07:00
Simon Glass
c275dfefeb dm: core: Provide uclass_find_device_by_phandle() only when needed
This function cannot be used unless support is enabled for device tree
control. Adjust the code to reflect that.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:06:21 -07:00
Vignesh R
74d49bfde3 spi: ti_qspi: Use 4-byte opcode for mmap read
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for
memory-mapped read. This restricts maximum addressable flash size to
16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped
read to allow access to addresses above 16MB.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
[vigneshr@ti.com: Re-word commit description]
Signed-off-by: Vignesh R <vigneshr@ti.com>
2016-01-20 10:19:33 -05:00
Sergey Temerkhanov
19de81502b arm: serial: Add Kconfig entries to facilitate usage of the pl01x driver for early debug output
This patch adds Kconfig entries to facilitate usage of pl01x as
a debug UART.

Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>

Acked-by: Simon Glass <sjg@chromium.org>
2016-01-19 22:25:35 +00:00
Sergey Temerkhanov
b81406db51 arm: serial: Add debug UART capability to the pl01x driver
This patch adds an ability to use pl01x as a debug UART. It must
be configured like other types of debug UARTs

Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
[trini: Update for _debug_uart_init change]
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19 22:25:22 +00:00
Tom Rini
e6ac28b60b Merge branch 'master' of git://git.denx.de/u-boot-video 2016-01-19 08:32:38 -05:00
Tom Rini
6d6aececfe power: regulator: max77686: Don't use switch() on bools
With gcc-5.3 we get a warning for using switch() on a bool type.
Rewrite these sections as if/else and update the one section that was
using 1/0 instead of true/false.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
2016-01-19 08:32:00 -05:00
Tom Rini
22bd03a6a2 spi: rk_spi: Fix debug format warning
We need to use %lx not %x to describe a fdt_addr_t

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19 08:31:46 -05:00
Tom Rini
55616b86c7 pci_rom.c: Fix may be used uninitialized warning
With gcc-5.x we get:
drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios':
drivers/pci/pci_rom.c:352:3: warning: 'ram' may be used uninitialized in
this function [-Wmaybe-uninitialized]

While unconvinced that this can happen in practice (if we malloc we set
alloced to true, it will be false otherwise), silence the compiler.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-19 08:31:21 -05:00
Tom Rini
5b8031ccb4 Add more SPDX-License-Identifier tags
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19 08:31:21 -05:00
Tom Rini
b57843e688 Merge branch 'master' of git://git.denx.de/u-boot-mips 2016-01-16 21:45:31 -05:00
Daniel Schwierzeck
df50b3b414 net: pcnet: refactor mapping of virtual addresses to physical ones
pci_virt_to_mem() uses virt_to_phys() to get the physical address.
But pci_virt_to_mem() is also called with uncached addresses which
is wrong according to the documentation of virt_to_phys().

Refactor the PCI_TO_MEM() macro to optionally map an uncached address
back to a cached one before calling pci_virt_to_mem().

Currently pcnet works because virt_to_phys() is incorrectly implemented
on MIPS. With the upcoming asm header file update for MIPS, the
virt_to_phys() implementation will be fixed. Thus this patch is needed
to keep pcnet working on MIPS Malta board.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Tom Rini
b8c5b47296 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2016-01-16 08:30:49 -05:00
Dinh Nguyen
b00a21f088 arm: socfpga: set the fpga global bit to disable HPS to FPGA signals
We should be setting the FPGA Interface Group global bit that will correctly
disable all interfaces between the FPGA and HPS.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-01-16 07:07:22 +01:00
Marek Vasut
1720fad0f1 ddr: altera: Init the rule ID in debug code
Init the rule ID, otherwise the debug code will always dump the
protection settings entry 0.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
2016-01-16 07:07:22 +01:00
Sanchayan Maity
08c11cb5df usb: host: ehci-vf: Implement board_usb_phy_mode weak function
Add board_usb_phy_mode weak function on similar lines to ehci-mx6.
However since Vybrid USB does not have a true OTG, make this weak
functon just return 0. The function is supposed to be implemented
by the individual boards using a GPIO for providing the OTG pin
functionality.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2016-01-16 07:06:55 +01:00
Sanchayan Maity
6089f75141 usb: host: ehci-vf: Remove hardcoded USB host client configuration
The current ehci-vf USB driver for Vybrid hardcodes the USB host
and client functionality. Remove this.

Reported-by: Santhosh Kumar Janardhanam <santhosh.kj@hcl.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2016-01-16 07:06:55 +01:00
Ye.Li
8991fdef6d usb:ci_udc: Remove ULPI setting for i.MX OTG controller
All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI
interface. Set to ULPI is not correct, even the controller will
reject this setting in PORTSC register.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-01-16 07:06:55 +01:00
Tom Rini
782acf7b52 Merge git://git.denx.de/u-boot-rockchip 2016-01-15 08:11:15 -05:00
Simon Glass
d830b1520a dm: pci: Avoid a memory leak when allocating the ROM
Adjust pci_rom_load() to return an indication of whether it allocated
memory or not. Adjust the caller to free it. This fixes a memory leak
when PCI_VGA_RAM_IMAGE_START is not used.

Reported-by: Coverity (CID: 134194)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-15 08:09:44 -05:00
Simon Glass
f19345b51c dm: pci: Add a 'fall through' comment
For this class it is intended to set up the PCI device, so add a comment to
indicate this. This avoids a coverity warning.

Reported-by: Coverity (CID: 134194)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-15 08:09:42 -05:00
Simon Glass
3c8fb12b77 dm: spi_flash: Allow the uclass to work without printf()
For SPL we don't really need sprintf() and with tiny-printf this is not
available. Allow this to be dropped in SPL when using tiny-printf.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-15 05:39:27 -07:00
huang lin
6579385b46 mmc: rockchip: the non-removable property must point to emmc
the non-removable property point to sdcard before, it is wrong,
it must point to emmc, correct it.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-15 05:39:27 -07:00
Ben Whitten
192bc6948b Fix GCC format-security errors and convert sprintfs.
With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.

Simple uses of sprintf are also converted to use strcpy.

Signed-off-by: Ben Whitten <ben.whitten@gmail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 22:11:34 -05:00
Tom Rini
f46c25583a Merge git://www.denx.de/git/u-boot-marvell
Conflicts:
	arch/arm/Kconfig

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-14 11:23:05 -05:00
Phil Sutter
4444d230ac mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT
This should make it clear that this symbol is meant to be defined by
board headers.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Phil Sutter
9a04527840 drivers/pci/pci_mvebu: Fix for boards with X4 lanes
Armada XP has support for X4 lanes, boards specify this in their
serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration
is stored in GEN_PURP_RES_2_REG.

When enumerating PEX, subsequent interfaces of an X4 lane must be
skipped. Otherwise the enumeration hangs up the board.

The way this is implemented here is not exactly beautiful, but it mimics
how Marvell's BSP does it. Alternatively we could get the information
using board_serdes_cfg_get(), but that won't lead to clean code, either.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Phil Sutter
7e1e59a7b7 axp: Fix debugging support in DDR3 write leveling
If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing.
In addition to that, get rid of debug output printing non-existent
counter variable.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Phil Sutter
1113146793 drivers/pci: Fix for debug builds without CONFIG_PCI_ENUM_ONLY
The debug printing references bar_res, which exists only if
CONFIG_PCI_ENUM_ONLY is not defined. Therefore move it into the ifdef'd
area.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Stefan Roese
81e33f4b65 arm: mvebu: Move SoC selection (A38X vs AXP) into Kconfig
Until now, the SoC selection for the ARCH_MVEBU platforms has been done
in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As
it needed to get selected for AXP and A38x based boards. This patch
now changes this to move the SoC selection to Kconfig. And also
uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x.
This makes things a bit clearer - especially for new board additions.

Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and
CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available
CONFIG_ARMADA_38X and CONFIG_ARMADA_XP.

And CONFIG_DDR3 is removed, as its not referenced anywhere.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
698ffab239 arm: mvebu: Make ECC support configurable on Armada XP
Currently, ECC support is enabled for all Armada XP boards. So the
DDR3 driver tries to configure the controller with ECC support, even
on boards without ECC. This patch makes this ECC optional which now
can be configured on a board-per-board basis.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Phil Sutter <phil@nwl.cc>
2016-01-14 14:08:59 +01:00
Tor Krill
169789dcb9 sata: Add SATA driver with DMA support for Marvell Kirkwood and Armada XP
This patch adds a new SATA driver for the Marvell Kirkwood and Armada
370 / XP SoC's.

This driver supports the SATA controller of some Mavell SoC's.
Here a (most likely incomplete) list of the supported SoC's:
- Kirkwood
- Armada 370
- Armada XP

This driver implementation is an alternative to the already available
driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
But this driver only supports PIO mode and as this new driver also
supports transfer via DMA, its much faster.

Please note, that the newer SoC's (e.g. Armada 38x) are not supported
by this driver. As they have an AHCI compatible SATA controller
integrated.

The original version of this driver was sent by Tor Krill to the U-Boot
list a few years ago. Here the link:

http://lists.denx.de/pipermail/u-boot/2010-June/073147.html

Changes by Stefan:
- Coding-style cleanup
- Support for Armada XP added
- MBUS window setup added
- D-cache flush and invalidation added - works with dcache enabled on
  Armada XP
- Removed mdelay() from ata_wait_register() and add timer based timeout
  detection to speed up the transfer

Signed-off-by: Tor Krill <tor@excito.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Stefan Roese
e3b9c98a23 net: mvneta: Convert to driver model
Update this driver to support driver model. As all MVEBU boards using
this driver are converted with this patch, the non-driver-model code
can be removed completely. This is also the reason why this patch
is quite big and includes a) the driver change and b) the
platform change. As its not git-bisect save otherwise.

With this conversion, some parameters are now extracted from the
DT instread of using the config header defines. The supported
properties right now are:

PHY-mode ("phy-mode") and PHY-address ("reg").

The base addresses for the ethernet controllers can be removed from
the header files as well.

Please note that this patch also removes the E1000 network driver
from some MVEBU config headers. This is necessary, as with DM_ETH
configured and the e1000 driver enabled, the PCI driver also needs
to support DM. But the MVEBU PCI(e) driver still needs to get
ported to DM. When this is done, the E1000 driver can be enabled
again.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Simon Glass <sjg@chromium.org>
2016-01-14 14:08:59 +01:00
Stefan Roese
9985bdb1ce spi: kirkwood_spi.c: Add driver model support
This patch adds driver model support to the kirkwood SPI driver. Which
is also used on the MVEBU SoC's, now being converted to DM. Non-DM
support is still available for the "older" platforms using this
driver, like kirkwood.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
2016-01-14 14:08:59 +01:00
Stefan Roese
18dd3b2221 spi: kirkwood_spi.c: Prepare for driver model support
This patch prepares the Kirkwood SPI driver, also used on the MVEBU board
(Armada XP / 38x), for the conversion to driver model.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
2016-01-14 14:08:59 +01:00
Stefan Roese
cdf1d240ba arm: mvebu: ddr: Fix compilation warning
gcc 5.1 generates this new warning (for Armada 38x platforms):

drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result':
drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array
  function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument]
  memcpy(result, training_result, sizeof(result));
                                        ^
drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here
  u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
                               ^

Since this functions is not referenced anywhere, lets just remove it.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00