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drivers/crypto/fsl: fix endianness issue in RNG

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For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
CC: Alex Porosanu <alexandru.porosanu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Aneesh Bansal 2015-12-08 13:54:30 +05:30 committed by York Sun
parent 9711f52806
commit 3a4800a596
1 changed files with 2 additions and 6 deletions
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8
drivers/crypto/fsl/jr.c
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@ -470,17 +470,13 @@ static void kick_trng(int ent_delay)
sec_out32(&rng->rtfreqmin, ent_delay >> 2);
/* disable maximum frequency count */
sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
/* read the control register */
val = sec_in32(&rng->rtmctl);
/*
* select raw sampling in both entropy shifter
* and statistical checker
*/
sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
/* put RNG4 into run mode */
sec_clrbits32(&val, RTMCTL_PRGM);
/* write back the control register */
sec_out32(&rng->rtmctl, val);
sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
}
static int rng_init(void)