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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
nios2: convert altera_jtag_uart to driver model
Convert altera_jtag_uart to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
37e24499b9
commit
220e8021af
6 changed files with 146 additions and 64 deletions
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@ -149,5 +149,6 @@
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chosen {
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bootargs = "debug console=ttyJ0,115200";
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stdout-path = &jtag_uart;
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};
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};
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@ -1,4 +1,5 @@
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CONFIG_NIOS2=y
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CONFIG_DM_SERIAL=y
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CONFIG_TARGET_NIOS2_GENERIC=y
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CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
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CONFIG_HUSH_PARSER=y
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@ -14,3 +15,5 @@ CONFIG_CMD_PING=y
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CONFIG_OF_CONTROL=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_ALTERA_JTAG_UART=y
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CONFIG_ALTERA_JTAG_UART_BYPASS=y
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4
doc/device-tree-bindings/serial/altera_jtaguart.txt
Normal file
4
doc/device-tree-bindings/serial/altera_jtaguart.txt
Normal file
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@ -0,0 +1,4 @@
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Altera JTAG UART
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Required properties:
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- compatible : should be "altr,juart-1.0"
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@ -54,6 +54,13 @@ choice
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prompt "Select which UART will provide the debug UART"
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depends on DEBUG_UART
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config DEBUG_UART_ALTERA_JTAGUART
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bool "Altera JTAG UART"
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help
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Select this to enable a debug UART using the altera_jtag_uart driver.
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You will need to provide parameters to make this work. The driver will
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be available until the real driver model serial is running.
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config DEBUG_UART_NS16550
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bool "ns16550"
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help
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@ -130,6 +137,25 @@ config DEBUG_UART_ANNOUNCE
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debug_uart_init()). This can be useful just as a check that
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everything is working.
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config ALTERA_JTAG_UART
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bool "Altera JTAG UART support"
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depends on DM_SERIAL
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help
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Select this to enable an JTAG UART for Altera devices.The JTAG UART
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core implements a method to communicate serial character streams
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between a host PC and a Qsys system on an Altera FPGA. Please find
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details on the "Embedded Peripherals IP User Guide" of Altera.
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config ALTERA_JTAG_UART_BYPASS
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bool "Bypass output when no connection"
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depends on ALTERA_JTAG_UART
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help
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Bypass console output and keep going even if there is no JTAG
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terminal connection with the host. The console output will resume
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once the JTAG terminal is connected. Without the bypass, the console
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output will wait forever until a JTAG terminal is connected. If you
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not are sure, say Y.
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config ROCKCHIP_SERIAL
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bool "Rockchip on-chip UART support"
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depends on ARCH_ROCKCHIP && DM_SERIAL
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@ -6,98 +6,149 @@
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <serial.h>
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typedef volatile struct {
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unsigned data; /* Data register */
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unsigned control; /* Control register */
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} nios_jtag_t;
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struct altera_jtaguart_regs {
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u32 data; /* Data register */
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u32 control; /* Control register */
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};
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struct altera_jtaguart_platdata {
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struct altera_jtaguart_regs *regs;
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};
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/* data register */
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#define NIOS_JTAG_RVALID (1<<15) /* Read valid */
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#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */
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#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */
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#define ALTERA_JTAG_RVALID (1<<15) /* Read valid */
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/* control register */
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#define NIOS_JTAG_RE (1 << 0) /* read intr enable */
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#define NIOS_JTAG_WE (1 << 1) /* write intr enable */
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#define NIOS_JTAG_RI (1 << 8) /* read intr pending */
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#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/
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#define NIOS_JTAG_AC (1 << 10) /* activity indicator */
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#define NIOS_JTAG_RRDY (1 << 12) /* read available */
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#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */
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#define ALTERA_JTAG_AC (1 << 10) /* activity indicator */
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#define ALTERA_JTAG_RRDY (1 << 12) /* read available */
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#define ALTERA_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */
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/* Write fifo size. FIXME: this should be extracted with sopc2dts */
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#define ALTERA_JTAG_WRITE_DEPTH 64
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DECLARE_GLOBAL_DATA_PTR;
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/*------------------------------------------------------------------
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* JTAG acts as the serial port
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*-----------------------------------------------------------------*/
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static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
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static void altera_jtag_serial_setbrg(void)
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{
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}
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static int altera_jtag_serial_init(void)
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static int altera_jtaguart_setbrg(struct udevice *dev, int baudrate)
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{
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return 0;
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}
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static void altera_jtag_serial_putc(char c)
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static int altera_jtaguart_putc(struct udevice *dev, const char ch)
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{
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while (1) {
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unsigned st = readl(&jtag->control);
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if (NIOS_JTAG_WSPACE(st))
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break;
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struct altera_jtaguart_platdata *plat = dev->platdata;
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struct altera_jtaguart_regs *const regs = plat->regs;
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u32 st = readl(®s->control);
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#ifdef CONFIG_ALTERA_JTAG_UART_BYPASS
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if (!(st & NIOS_JTAG_AC)) /* no connection */
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return;
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if (!(st & ALTERA_JTAG_AC)) /* no connection yet */
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return -ENETUNREACH;
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#endif
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WATCHDOG_RESET();
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}
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writel ((unsigned char)c, &jtag->data);
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if (ALTERA_JTAG_WSPACE(st) == 0)
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return -EAGAIN;
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writel(ch, ®s->data);
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return 0;
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}
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static int altera_jtag_serial_tstc(void)
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static int altera_jtaguart_pending(struct udevice *dev, bool input)
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{
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return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
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struct altera_jtaguart_platdata *plat = dev->platdata;
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struct altera_jtaguart_regs *const regs = plat->regs;
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u32 st = readl(®s->control);
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if (input)
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return st & ALTERA_JTAG_RRDY ? 1 : 0;
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else
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return !(ALTERA_JTAG_WSPACE(st) == ALTERA_JTAG_WRITE_DEPTH);
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}
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static int altera_jtag_serial_getc(void)
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static int altera_jtaguart_getc(struct udevice *dev)
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{
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int c;
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unsigned val;
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struct altera_jtaguart_platdata *plat = dev->platdata;
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struct altera_jtaguart_regs *const regs = plat->regs;
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u32 val;
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while (1) {
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WATCHDOG_RESET ();
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val = readl (&jtag->data);
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if (val & NIOS_JTAG_RVALID)
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break;
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}
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c = val & 0x0ff;
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return (c);
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val = readl(®s->data);
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if (!(val & ALTERA_JTAG_RVALID))
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return -EAGAIN;
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return val & 0xff;
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}
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static struct serial_device altera_jtag_serial_drv = {
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.name = "altera_jtag_uart",
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.start = altera_jtag_serial_init,
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.stop = NULL,
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.setbrg = altera_jtag_serial_setbrg,
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.putc = altera_jtag_serial_putc,
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.puts = default_serial_puts,
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.getc = altera_jtag_serial_getc,
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.tstc = altera_jtag_serial_tstc,
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static int altera_jtaguart_probe(struct udevice *dev)
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{
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#ifdef CONFIG_ALTERA_JTAG_UART_BYPASS
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struct altera_jtaguart_platdata *plat = dev->platdata;
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struct altera_jtaguart_regs *const regs = plat->regs;
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writel(ALTERA_JTAG_AC, ®s->control); /* clear AC flag */
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#endif
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return 0;
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}
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static int altera_jtaguart_ofdata_to_platdata(struct udevice *dev)
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{
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struct altera_jtaguart_platdata *plat = dev_get_platdata(dev);
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plat->regs = ioremap(dev_get_addr(dev),
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sizeof(struct altera_jtaguart_regs));
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return 0;
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}
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static const struct dm_serial_ops altera_jtaguart_ops = {
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.putc = altera_jtaguart_putc,
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.pending = altera_jtaguart_pending,
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.getc = altera_jtaguart_getc,
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.setbrg = altera_jtaguart_setbrg,
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};
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void altera_jtag_serial_initialize(void)
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static const struct udevice_id altera_jtaguart_ids[] = {
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{ .compatible = "altr,juart-1.0", },
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{ }
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};
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U_BOOT_DRIVER(altera_jtaguart) = {
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.name = "altera_jtaguart",
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.id = UCLASS_SERIAL,
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.of_match = altera_jtaguart_ids,
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.ofdata_to_platdata = altera_jtaguart_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct altera_jtaguart_platdata),
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.probe = altera_jtaguart_probe,
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.ops = &altera_jtaguart_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#ifdef CONFIG_DEBUG_UART_ALTERA_JTAGUART
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#include <debug_uart.h>
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void debug_uart_init(void)
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{
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serial_register(&altera_jtag_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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static inline void _debug_uart_putc(int ch)
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{
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return &altera_jtag_serial_drv;
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struct altera_jtaguart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
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while (1) {
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u32 st = readl(®s->control);
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if (ALTERA_JTAG_WSPACE(st))
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break;
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}
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writel(ch, ®s->data);
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}
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DEBUG_UART_FUNCS
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#endif
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@ -23,14 +23,11 @@
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/*
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* SERIAL
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*/
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#define CONFIG_ALTERA_JTAG_UART
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#if defined(CONFIG_ALTERA_JTAG_UART)
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# define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_JTAG_UART_BASE
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#else
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# define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_UART_BASE
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#endif
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#define CONFIG_ALTERA_JTAG_UART_BYPASS
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#define CONFIG_SYS_NIOS_FIXEDBAUD
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#define CONFIG_BAUDRATE CONFIG_SYS_UART_BAUD
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#define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE}
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