Commit graph

13979 commits

Author SHA1 Message Date
Reinhard Meyer
e0cd44c3c1 AT91: reset.c: fix comments, add option
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2010-09-03 11:21:51 +02:00
Reinhard Meyer
93dfcbe3c8 AT91: fix at91sam9260.h for AT91SAM9XE
Define the different location of the GPBRs for the 9XE
Define the proper CPU Name

Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2010-09-03 11:21:02 +02:00
Reinhard Meyer
d88bebe16d AT91SAM9XE: add embedded flash support
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2010-09-03 11:20:31 +02:00
Reinhard Meyer
c7260d1539 AT91: add RTT and GPBR based RTC
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2010-09-03 11:20:02 +02:00
Reinhard Meyer
1592ef8596 AT91: MCI: add SD/MMC driver using mmc framework
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2010-09-03 11:19:01 +02:00
Stefan Roese
f3cac53840 ppc4xx: Invalidate d-cache when used as init-ram
We need to invalidate the data cache after it has been used as init-ram.

This problem was detected on the lwmon5 update.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-03 11:14:26 +02:00
Stefan Roese
c1ab75c7d4 ppc4xx: Fix 440EPx bug in reconfigure_pll()
This patch fixes a bug in reconfigure_pll(), where the detection of
the current bootstrap option is wrong. The ICS bits where incorrectly
shifted. This bug was found on the lwmon5 board, which uses bootstrap
option H (I2C bootstrap EEPROM).

Additionally a bit of code was moved into the if statement, since its
only used after later on. No need to run this code all the time.

Also, a few empty lines are added to make the code better readable.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Rupjyoti Sarmah <rsarmah@amcc.com>
Cc: Victor Gallardo <vgallardo@appliedmicro.com>
2010-09-03 11:14:21 +02:00
York Sun
8d9207c792 Fix parameters to support RDIMM for P2020DS
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-31 11:23:04 -05:00
Jens Scharsig
c982d866ea AT91 Fix: return value of get_tbclk
* Fix: return value of get_tbclk
 * this fixes issue with prematurely restart/retry, if BOOT_RETRY_TIMEOUT is used

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-08-31 10:38:35 +02:00
Minkyu Kang
a87bc64cb4 ARMV7: S5P: rename the member of gpio structure
Typically we declare the name of gpio structure to "gpio",
so it was duplicated around the name. (e.g: gpio->gpio_a)
This patch modified the naming that is removing "gpio_".

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2010-08-30 14:44:33 +09:00
Minkyu Kang
f70409aff3 ARMV7: S5P: separate the peripheral clocks
Because of peripheral devices can select clock sources,
separate the peripheral clocks. (pwm, uart and so on)
It just return the pclk at s5pc1xx SoC,
but s5pc210 SoC must be calculated by own clock register setting.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2010-08-30 14:44:16 +09:00
Albert Aribaud
438c37e1b3 orion5x: fix comment-in-comment typo in cpu.h
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
2010-08-27 21:41:48 +05:30
Prafulla Wadaskar
f106056095 Kirkwood: bugfix: window size (mis)calculation
Fixed kw_winctrl_calcsize() off-by-1 bug which caused mapping
windows size to be cut by half.
This corrected all windows address configuration

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-08-26 14:43:55 +05:30
Albert Aribaud
4e4479a892 Orion5x: bugfix: window size (mis)calculation
Fix orion5x_winctrl_calcsize() off-by-1 bug which caused mapping
windows to be cut by half. This afected all windows including NOR
flash (causing half the flash to be unaccessible) but DRAM was and
still is fine as its size is determined otherwise.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
2010-08-26 14:05:19 +05:30
Minkyu Kang
545dabbeef ARMV7: S5P: fix the macro at samsung_get_base function
New line is unnecessary at last line of macro.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-08-26 17:34:38 +09:00
Minkyu Kang
da70a2bb4a S5P: mmc: fix the mmc offset
This patch fixed the size of mmc structure.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-08-23 15:34:37 +09:00
Minkyu Kang
37168dab52 ARMV7: S5P: rename from s5pc1xx to s5p
Because of these are common files around s5p Socs, rename from s5pc1xx to s5p.
And getting cpu_id is SoC specific, so move to SoC's header file.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2010-08-23 15:34:25 +09:00
Minkyu Kang
852bd07c80 ARMV7: S5P: make s5p-common for sharing the code between s5pc1xx and s5pc2xx
This patch adds basic support for s5pc210.
s5p-common will be used by all of s5p SoCs.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2010-08-23 15:34:20 +09:00
Nishanth Menon
a947f4b68b omap2: i2c: remove redundant header definitions
Remove the register offset and common defines which are
already present in drivers/i2c/omap24xx.h. All of these
defines carry the same value even.

Cc: Steve Sakoman <steve@sakoman.com>
Cc: Heiko <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Wolfang Denk <wd@denx.de>

Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Steve Sakoman <steve@sakoman.com>
2010-08-23 08:09:04 +02:00
Nishanth Menon
46d8ece4e8 omap2: i2c: add syss offset
OMAP2420 ES2.3 trm defines syss register offset as 0x10. Add it.

Cc: Steve Sakoman <steve@sakoman.com>
Cc: Heiko <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Wolfang Denk <wd@denx.de>

Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Steve Sakoman <steve@sakoman.com>
2010-08-23 08:08:49 +02:00
Matthew McClintock
b80d30546e mpx85xx/fdt: Add cpu-release-addr for all cores
We currently do not add a cpu-release-addr for core 0, this is needed
when we want to reset core 0 and later restart it from Linux

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-19 21:20:10 -05:00
Thomas Chou
7a6a7d10e6 nios2: fix out of reach case for do_reset
There is a limitation (or bug?) of nios2 toolchain. The nios2 gcc
didn't generate correct code when the reset vector is passed as a
constant. It just generated a direct "call", which was wrong when
the reset vector was not located in the same 256MB span as u-boot.

The "Nios II Processor Reference Handbook" said,
"call can transfer execution anywhere within the 256 MByte range
determined by PC31..28. The Nios II GNU linker does not automatically
handle cases in which the address is out of this range."

So we have to use registered "callr" instruction to do the job.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-08-19 22:15:49 -04:00
Thomas Chou
62a0557382 nios2: fix bootm error on fdt args
We should check argv[3] only if there are enough args. Otherwise,
it might cause invalid memory access fault.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-08-19 22:15:49 -04:00
Kumar Gala
ed062e0f6c powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs
Official docs call it the Job Ring not Job Queue for the p4080 security
block.  Match the docs to reduce confusion.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-19 02:06:13 -05:00
Kim Phillips
680c613a5c powerpc/8xxx: share PIC defines among 85xx and 86xx
fixes breakeage introduced by commit
a37c36f4e7 "powerpc/8xxx: query
feature reporting register for num cores on unknown cpus"

Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-19 02:06:13 -05:00
Wolfgang Denk
5549d22b65 Merge branch 'master' of /home/wd/git/u-boot/master 2010-08-18 21:19:00 +02:00
Sandeep Paulraj
9ce2c4b7f7 ARM: Update ARM mach-types
This patch updates the mach-types.h based on the latest linux kernel

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-08-18 21:15:57 +02:00
Minkyu Kang
d93d0f0cfe S5P: Use accessor functions instead of SoC specific defines to access the base address
This patch is intended to prepare the other S5P SoC. (s5pc210)
If use SoC specific defines then can't share with other SoC.
So, make the accessor functions for access the base address by common way.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2010-08-17 11:38:19 +09:00
Wolfgang Denk
ae37a0704a Merge branch 'master' of git://git.denx.de/u-boot-ti 2010-08-12 23:08:05 +02:00
Wolfgang Denk
668a6b4591 Merge branch 'master' of git://git.denx.de/u-boot-usb 2010-08-12 23:05:22 +02:00
Ajay Kumar Gupta
a7e9c513b6 AM35x: Adding SCM general register definitions
Adding general register structure of system control module (SCM)
of AM35x. This would be required to access devconf2 and ip_sw_reset
register in musb module.

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
2010-08-12 16:39:59 +02:00
Mike Frysinger
5d89115c53 Blackfin: re-use board data in cpu banner
The bi_cpu field of the board data is already set to the relevant cpu
string, so there is no need for us to use the define directly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-08-11 11:29:19 -04:00
Michael Hennerich
5fc564eda7 Blackfin: shutdown video DMA when booting Linux
In case there is no frame buffer driver present in Linux to hand over the
PPI LCD DMA upon boot, the DMA initiated by u-boot to display the splash
screen runs unattended.  Therefore always stop the video driver in u-boot
before starting Linux.  If people don't want this behavior, then they can
simply stub out the video_stop() function in their board video driver.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-08-11 11:29:08 -04:00
Matthias Weisser
6052ac8386 ARM: Add support for MB86R0x SoCs
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
2010-08-10 23:13:28 +02:00
Wolfgang Denk
b9d51fbb18 Merge branch 'master' of git://git.denx.de/u-boot-arm 2010-08-10 23:03:15 +02:00
Wolfgang Denk
b77f380115 Merge branch 'master' of git://git.denx.de/u-boot-imx 2010-08-10 22:49:09 +02:00
Albert Aribaud
4cfa0ab2c9 orion5x: allow overriding default mappings windows
Turn all ORION5X_DEF{ADR,SZ}_xxx macros into ORION5X_{ADR,SZ}_xxx
and allow defining them from board code to override defaults. This
is particularly useful for defining board-specific FLASH address
and size in board header file rather than having to tweak orion5x
code.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
2010-08-10 22:44:12 +02:00
Wolfgang Denk
fe8d63c8c7 Merge branch 'master' of git://git.denx.de/u-boot-marvell 2010-08-10 22:37:27 +02:00
Wolfgang Denk
9844d027b5 Merge branch 'master' of git://git.denx.de/u-boot-ti 2010-08-10 22:20:51 +02:00
Wolfgang Denk
201532a69c Merge branch 'master' of ../master 2010-08-10 22:20:27 +02:00
Li Haibo
51b5870bdc MX51EVK: fix return value of get_timer_masked
get_timer_masked() should return current timestamp,
not current ticks from hardware register.

Tested on one custom board with NAND flash.
Without this patch, NAND write always TIMEOUT
because get_timer(0) return a big value.

This patch applies for u-boot-2010.06

Signed-off-by: Li Haibo <hbli@sinocastel.com>
2010-08-10 09:46:44 +02:00
Mike Frysinger
5700bb6352 miiphy: constify device name
The driver name does not need to be writable, so constify it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-08-09 11:52:29 -07:00
Heiko Schocher
48690d8024 net ppc: fix ethernet device names with spaces
since commit 1384f3bb8a ethernet names
with spaces drop a

Warning: eth device name has a space!

message. This patch fix it for:

- "FEC ETHERNET" devices found on
  mpc512x, mpc5xxx, mpc8xx and mpc8220 boards.
  renamed to "FEC".
- "SCC ETHERNET" devices found on
  mpc8xx, mpc82xx based boards. Renamed to "SCC".
- "HDLC ETHERNET" devices found on mpc8xx boards
  Renamed to "HDLC"
- "FCC ETHERNET" devices found on mpc8260 and mpc85xx based
  boards. Renamed to "FCC"

Tested on the kup4k board.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-08-09 11:52:28 -07:00
Stephan Linz
958e120643 fdt relocate: have more attention to use a bootmap or not
Platforms with flat device tree support can use a bootmap to relocate
the fdt_blob. This is not a must. That's why the relocation function
boot_relocate_fdt() should be use only if CONFIG_OF_LIBFDT was defined
together with CONFIG_SYS_BOOTMAPSZ (see common/cmd_bootm.c).

On MicroBlaze platforms there is no need to use a bootmap to relocate
a fdt blob. So we need a more precise focus on the compilation and usage
of boot_relocate_fdt().

In general it is valid to exclude the function boot_relocate_fdt() if
the bootmap size CONFIG_SYS_BOOTMAPSZ is not defined.

Signed-off-by: Stephan Linz <linz@li-pro.net>
2010-08-08 22:16:05 +02:00
Prafulla Wadaskar
5f30500316 cmd_ide: add support for Kirkwood
Added MVSATAC definitions to Kirkwood.
Added support for Kirkwood in cmd_ide.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-08-08 05:17:55 +05:30
Albert Aribaud
113bfe48bc cmd_ide: add support for orion5x
Add MVSATAHC definitions to orion5x.
Add support for orion5x in cmd_ide.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
2010-08-08 05:17:06 +05:30
Albert Aribaud
f2a37fcd9b ide: add configuration
CONFIG_IDE_SWAP_IO

This configuration option replaces a complex conditional
in cmd_ide.c with an explicit define to be added to SoC or
board configs.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
2010-08-08 05:17:05 +05:30
Marek Vasut
560639806d ARM: Define __raw_readX and __raw_writeX
These functions are undefined on ARM when using __io. These are the commonly
used versions and can be redefined.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-08-07 22:34:25 +02:00
Wolfgang Denk
3df4f46f32 Merge branch 'master' of /home/wd/git/u-boot/master 2010-08-07 22:33:06 +02:00
Steve Sakoman
9b16757758 ARMV7: Restructure omap3 musb driver to allow code sharing between OMAP3 and OMAP4
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-08-05 10:11:34 -04:00
Steve Sakoman
d708395d2f ARMV7: Modify i2c driver for more reliable operation on OMAP4
This patch modifies the init routine to follow the TRM
recommendations. It also modifies the i2c_read_byte function
to reflect subtle differences between the i2c controller in
OMAP3 and OMAP4.

Signed-off-by:  Steve Sakoman <steve@sakoman.com>
Acked-by: Nishanth Menon <menon.nishanth@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-08-05 10:11:24 -04:00
Steve Sakoman
674e0b217f ARMV7: Fix udelay for OMAP4
The OMAP4 x-load code sets gptimer1 clock source to 32Khz.  This isn't
acceptable for udelay.  This patch changes from gptimer1 to gptimer2,
which uses sys_clk at 38.4 Mhz.

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-08-05 10:11:20 -04:00
Steve Sakoman
2ad853c348 ARMV7: Add pad mux support for OMAP4
Add functional multiplexing support for OMAP4 pads.
Configure all the pads for the OMAP4430 SDP
and OMAP4 Panda boards

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-08-05 10:11:14 -04:00
Wolfgang Denk
cdb749778a Rename getenv_r() into getenv_f()
While running from flash, i. e. before relocation, we have only a
limited C runtime environment without writable data segment. In this
phase, some configurations (for example with environment in EEPROM)
must not use the normal getenv(), but a special function.  This
function had been called getenv_r(), with the idea that the "_r"
suffix would mean the same as in the _r_eentrant versions of some of
the C library functions (for example getdate vs. getdate_r, getgrent
vs. getgrent_r, etc.).

Unfortunately this was a misleading name, as in U-Boot the "_r"
generally means "running from RAM", i. e. _after_ relocation.

To avoid confusion, rename into getenv_f() [as "running from flash"]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
2010-08-04 00:45:36 +02:00
Wolfgang Denk
9efac4a1eb Merge branch 'master' of git://git.denx.de/u-boot-samsung 2010-08-04 00:35:10 +02:00
Wolfgang Denk
36448c6038 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-08-04 00:30:50 +02:00
Wolfgang Denk
ac956293be Merge branch 'master' of /home/wd/git/u-boot/master 2010-08-03 22:45:13 +02:00
Minkyu Kang
5000284872 S5P: support mmc driver
This patch adds support mmc driver for s5p SoC

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2010-08-03 10:18:15 +09:00
Kim Phillips
a37c36f4e7 powerpc/8xxx: query feature reporting register for num cores on unknown cpus
doing so helps avant garde users, such as those using simulators that
allow users to configure the number of cores, so as to not have to
manually adjust u-boot sources.  h/w should also be reliably setting
FRR NCPU in the future.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-01 11:18:45 -05:00
Mike Frysinger
c8cf4fc407 Blackfin: gpio: use common usage func
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-29 13:29:52 -04:00
york
5fb8a8a731 powerpc/8xxx: Improvement to DDR parameters
Changes for P2020DS DDR applies to other 8xxx platform

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:10 -05:00
york
9490ff4864 powerpc/8xxx: Enable DDR3 RDIMM support
Enabled registered DIMMs using data from SPD. RDIMMs have registers
which need to be configured before using. The register configuration
words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software
should read those RCWs and put into DDR controller before initialization.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:10 -05:00
york
7fd101c97b powerpc/8xxx: Enabled address hashing for 85xx
For 85xx silicon which supports address hashing, it can be activated by
hwconfig.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:09 -05:00
york
5800e7ab32 powerpc/8xxx: Enable quad-rank DIMMs.
Previous code presumes each DIMM has up to two rank (chip select). Newer
DDR controller supports up to four chip select on one DIMM.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:09 -05:00
york
076bff8f47 powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.

Also check dimm size and rank size for memory controller interleaving

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:09 -05:00
Kumar Gala
79e4e6480b powerpc/8xxx: Enabled hwconfig for memory interleaving
Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with
hwconfig parameters. The syntax is

    setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>"

The mode values for memory controller interleaving are
    cacheline
    page
    bank
    superbank

The mode values for bank interleaving are
    cs0_cs1
    cs2_cs3
    cs0_cs1_and_cs2_cs3
    cs0_cs1_cs2_cs3

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:08 -05:00
Kumar Gala
fd3c9befa8 powerpc/p4080: Add workaround for erratum CPU22
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:57 -05:00
Kumar Gala
61054ffa16 powerpc/p4080: Add workaround for errata SERDES8
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:57 -05:00
Kumar Gala
34a8258fea powerpc/p4080: Add support for initializing SERDES
Add support for initializing the SERDES blocks on CoreNet style QoriQ
devices and the p4080 specific SERDES tables to know which actual
componetns are enabled.

Additionally, split out the Frame Manger (FMAN) into its specific ethernet
ports instead of gross level of the full FMAN.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:57 -05:00
Kumar Gala
db977abfc8 powerpc/85xx: Add support to initialize LIODN registers and portals
On the new QorIQ/CoreNet based platforms we need to initialize the
"portals" as access into the Data Path subystem as well as Logical IO
Device Numbers (LIODN) that are used for the IOMMU (PAMU).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:56 -05:00
Kumar Gala
6aba33e939 powerpc/p4080: Add support for CPC(Corenet platform cache) on CoreNet platforms
The CoreNet style platforms can have a L3 cache that fronts the memory
controllers.  Enable that cache as well as add information into the
device tree about it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:56 -05:00
york
a3f18529ec powerpc/85xx: Move INIT_RAM_ADDR physical address to 36-bit space
If 36-bit physical address is used, move the INIT_RAM_ADDR to higher
address. This frees the low 4GB address space for better use.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:07:49 -05:00
Kumar Gala
ebd7cb0ba9 powerpc/fsl_fman: Add initial fman immap structures
Add basic structures for Frame Manager on P4080/P3041/P5020 devices

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 08:07:47 -05:00
Kumar Gala
9ab87d04a8 powerpc/85xx: Add additional p4080 platform related defines/structs
* Added PCIE4 address, offset, DEVDISR & LAW target ID
* Added new p4080 DDR registers and defines to immap
* Add missing corenet platform DEVDISR related defines
* Updated ccsr_gur to include LIODN registers
* Add RCWSR defines
* Added Basic qman, pme, bman immap structs
* Added SATA related offsets & addresses
* Added Frame Manager 1/2 offsets & addresses
* Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
* Added various offsets and addresses that where missing

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 08:07:47 -05:00
Mike Frysinger
b990c7bda4 Blackfin: jtag-console: handle newline stuffing
Serial devices currently have to manually stuff \r after every \n found,
but this is a bit more difficult with the jtag console since we process
everything in chunks of 4 bit.  So we have to scan & stuff the whole
string rather than what most serial drivers do which is output on a byte
per byte basis.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-25 15:17:34 -04:00
Mike Frysinger
4fff5ac2f8 Blackfin: jtag-console: add debug markers
While we're in here, add some useful debug points.  We need custom debug
statements because we need the output to only go to the serial port.  If
we used the standard debug helpers, the output would also go to the stdout
(which would be the jtag console) and make it hard to figure out what is
going where exactly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-25 15:17:31 -04:00
Mike Frysinger
5079d8bbad Blackfin: jtag-console: robustify against missing peer
If the other side isn't listening, we should reset the state to ignore
the whole message and not just the part we missed.  This makes it easier
to connect at any time to the jtag console without worrying about the two
sides getting out of sync and thus sending garbage back and forth.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-25 15:17:27 -04:00
Wolfgang Denk
47e26b1bf9 cmd_usage(): simplify return code handling
Lots of code use this construct:

	cmd_usage(cmdtp);
	return 1;

Change cmd_usage() let it return 1 - then we can replace all these
ocurrances by

	return cmd_usage(cmdtp);

This fixes a few places with incorrect return code handling, too.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-07-24 20:43:57 +02:00
Wolfgang Denk
9662317142 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-07-24 20:34:13 +02:00
Stefan Roese
be24ef6e8e ppc4xx: Add ECC status info to machine-check exception for IBM DDR2 core
Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:55:03 +02:00
Stefan Roese
58eb869ffc ppc4xx: Add "ecctest" command to test/simulate ECC errors
This patch adds the "ecctest" command to test and simulate ECC errors
(single bit and/or double bit) while running from SDRAM. Currently only
the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT).

This is done by copying and calling functions, modifying the SDRAM
controller operation mode, in internal SRAM/OCM.

For correctable ECC errors (single bit) only the status will be printed
since the DDR2 controller doesn't provide the faulting address:

=> ecctest 1000000 1
Using address 01000000 for 1 bit ECC error injection
ECC: Correctable error

Uncorrectable ECC errors (double bit) will also display the faulting
address:

=> ecctest 1000000 2
Using address 01000000 for 2 bit ECC error injection
ECC: Uncorrectable error at 0x0001000000

To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST
in the board config header.

Tested on katmai and t3corp.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:54:54 +02:00
Stefan Roese
b995d7cb2c ppc4xx: DDR/ECC: Use correct macros to clear error status
Use the correct macro instead of the hardcoded 0x4c to clear the ECC
status in the 440/460 DDR(2) error status register after ECC
initialization.

Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
(440GX) use a different registers to clear this error status. Use the
correct ones.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:54:28 +02:00
Stefan Roese
897d6abc50 ppc4xx: Only define DDR2 registers for the correct PowerPC variants
Make sure that some SDRAM/DDR2 registers are only defined for the PPC
variants really implementing those registers.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:54:22 +02:00
Stefan Roese
eab9800182 ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC values
Using this define, a board can define an opimized RFDC value and use
the auto calibration code to "tune" the remaining DDR2 controller
calibration register.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:54:09 +02:00
Kumar Gala
47ec10c597 powerpc/85xx: Rework P1022 SERDES is_serdes_configured support
Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-21 00:40:20 -05:00
Kumar Gala
af0250652a powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured support
Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-21 00:40:16 -05:00
Kumar Gala
c26de2d8b1 powerpc/p3041: Add various p3041 related defines
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p3041 to cpu_type_list and SVR list
* Added number of LAWs for p3041
* Set CONFIG_MAX_CPUS to 4 for p3041

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:19 -05:00
Kumar Gala
19dbcc96c0 powerpc/p5020: Add various p5020 related defines (and p5010)
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p5020 & p5010 to cpu_type_list and SVR list
* Added number of LAWs for p5020
* Set CONFIG_MAX_CPUS to 2 for p5020

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:19 -05:00
Emil Medve
7eda1f8eed powerpc/mpc85xx: Report FMAN # to match user manual
The user manual refers to FMAN1 and FMAN2 not 0 and 1.

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:18 -05:00
Kumar Gala
85f8cda3c2 powerpc/p4080: Add setting of clock-frequency for clockgen node
On QorIQ CoreNet based devices we have a global clocking block.  We want
to keep track of SYSCLK frequency as it is what is used to derive all
other frequencies in the SoC

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:18 -05:00
Kumar Gala
1b942f7483 powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates
Move to using fdt_node_offset_by_compat_reg to find the node offsets we
want to update instead of using aliases.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:40:06 -05:00
Kumar Gala
6525d51fa5 powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases
Previously we used an alias the pci node to determine which node to
fixup or delete.  Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.

Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:40:06 -05:00
Kumar Gala
dd2cda3dbd powerpc/86xx: Move PCI/PCIe address defines into common immap_86xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.  Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on
MPC8641 boards since its really PCIE controllers and not PCI.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:37:11 -05:00
Kumar Gala
99d9c07edc powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:37:11 -05:00
Wolfgang Denk
0fe247b973 Drop support for GTH board
The board maintainer states:

    The GTH board is obsolete and has not been manufactured for
    several years.
    To my knowledge, no recent U-Boot build has been tested on that
    card.

So drop support for this board.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Thomas Lange <thomas@corelatus.se>
Acked-by: Thomas Lange<thomas@corelatus.se>
2010-07-17 20:47:08 +02:00
Wolfgang Denk
e9aecdec15 Merge branch 'master' of git://git.denx.de/u-boot-ti 2010-07-16 23:24:38 +02:00
Wolfgang Denk
b6c208ab1e Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-07-16 23:15:01 +02:00
Kumar Gala
9f43d7997e powerpc/85xx: Move p1022ds slot code into board file
The code to map SERDES configs to slot names is board specific and not
chip specific.  Thus it should live in board/freescale/p1022ds/ and not
in arch/powerpc/cpu/.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:10 -05:00
Kumar Gala
79ee344802 powerpc/85xx: Add command to report errata workarounds
Add 'errata' command to report what errata we workaround.  Report
workaround for erratum SATA-A001 on P1022/P1013.

Also sorted the CONFIG_CMD_* list.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:10 -05:00
Timur Tabi
c59e1b4d07 powerpc: add support for the Freescale P1022DS reference board
Specifics:

1) 36-bit only
2) Booting from NOR flash only
3) Environment stored in NOR flash only
4) No SPI support
5) No DIU support

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:10 -05:00
Timur Tabi
752bc33530 fsl: add LAW target to fsl_pci_info structure
Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that
we can capture the LAW target for a given PCI or PCIE controller.  Also update
the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the
LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure.

This will allow future PCI[E] code to configure the LAW target automatically,
rather than requiring each board to it for each PCI controller separately.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:10 -05:00
Kumar Gala
ae3913922a powerpc/85xx: Add support for link stack & STAC on e5500
The e5500 has a link register stack and segment target address cache.
Its safe to enable these bits on older e500 cores as the bits are
implemented in the register.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Kumar Gala
2a3a96ca5e powerpc/85xx: Add recognition of e5500 core
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
f2d9a5da29 powerpc 83xx/85xx: Merge lbc upmconfig code
Each platform had its own version of the upmconfig, despite the
init process being identical.  Now that we have a spot for common
lbc code, create a common upmconfig() there.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
199e262eb3 mpc85xx: Add reginfo command
The new command dumps the TLBCAM, the LAWs, and the BR/OR regs.
Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
e71755f887 drivers/misc/fsl_law.c: Rearrange code to avoid duplication
The current code redefines functions based on FSL_CORENET_ vs not -
create macros/inlines instead that hide the differences.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
70e02bca6b mpc85xx: Add print_tlbcam() function
This dumps out the contents of TLB1 on 85xx-based systems.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
4e63df300f mpc85xx: tlb.c cleanups
Extract the operation to read a tlb into a function - we will need
this later to print out the tlbs, and there's no point in duplicating
the code.  Create a TSIZE_TO_BYTES macro to deal with the conversion
from the MAS field to an actual size instead of duplicating this in code.
There are a few misc other minor cleanups.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
f51cdaf191 83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers.  Merge
this into a single spot.

To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from
each processor family.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Kumar Gala
8f3a7fa4a2 powerpc/8xxx: Add is_core_disabled to remove disabled cores from dtb
If we explicitly disabled a core remove it from the dtb we pass on to
the kernel.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:08 -05:00
Kumar Gala
11beefa382 mpc8xxx: Remove cpu-handles for cpus we delete
We may have cpu-handles pointing to the cpu nodes we delete.  If so we
should delete the handles as well.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:08 -05:00
Kim Phillips
22f292c7b2 powerpc/8xxx: Add base support for the SEC4
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:07 -05:00
Kim Phillips
929a213830 powerpc/8xxx: Distinguish between incompatible SEC h/w types
CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x.
Parts with newer SEC h/w versions will increment the number to
accomodate incompatible code changes.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:07 -05:00
Kim Phillips
5d0c3b57b2 fdt: move fsl specific code from common fdt area to mpc8xxx/fdt.c
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:07 -05:00
Wolfgang Denk
16909f34b7 Merge branch 'master' of git://git.denx.de/u-boot-pxa 2010-07-15 22:49:12 +02:00
Wolfgang Denk
93502a5e0a Merge branch 'master' of ../master 2010-07-15 22:48:46 +02:00
Steve Sakoman
27952014c4 ARMV7: Add basic gpmc initialization for OMAP4
This patch adds a gpmc_init function for OMAP4 and adds calls to
gpmc_init for existing OMAP4 boards: panda and sdp4430

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-07-15 16:19:16 -04:00
Marek Vasut
546cd608dd PXA: Add support for LMS285GF05 into pxafb
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-07-14 23:25:22 +02:00
Marek Vasut
9b92cf045a Voipac PXA270 LCD Support
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-07-14 23:25:22 +02:00
Marek Vasut
5ab877b688 PXA: Add OneNAND booting support to start.S
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-07-14 22:41:39 +02:00
Marek Vasut
8c77f232f0 PXA: Add PWM2 and PWM3 regs to pxa-regs.h
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-07-14 22:41:39 +02:00
Marek Vasut
fea0ffe418 PXA: Add hardware init helper macros
This patch adds macros for the following purposes:
- GPIO configuration
- SDRAM configuration
- Wakeup
- Clock configuration
- Interrupt controller configuration
These macros are intended to replace numerous copies of the same code.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-07-14 22:41:39 +02:00
Marek Vasut
8c35d0c570 Enable PXAFB for PXA27X and PXA3XX 2010-07-14 22:41:39 +02:00
Wolfgang Denk
d6f324d03d Merge branch 'next' of git://git.denx.de/u-boot-nios 2010-07-14 22:07:41 +02:00
Wolfgang Denk
e1e3cf7c79 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-07-14 22:05:31 +02:00
Wolfgang Denk
50298d37e6 Merge branch 'master' of git://git.denx.de/u-boot-net 2010-07-14 22:04:30 +02:00
Mike Frysinger
bbf4fbb6cc Blackfin: bf561: use DMA for Core B L1 regions
The L1 regions of Core B are not directly accessible from Core A, so we
need to use DMA to get at them.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-13 17:50:52 -04:00
Mike Frysinger
a409fdd8fe Blackfin: serial: convert to portmux framework
Use the new portmux framework to handle the details when possible.
Unfortunately, we cannot yet use this in the standalone initialization
logic, so we need to keep around the old portmux writes for now.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-13 17:50:50 -04:00
Albert Aribaud
d3c9ffd07d mvgbe: add support for orion5x GbE controller
Add definitions and initialization in orion5x for mvgbe.
Add orion5x in mvgbe SoC includes.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-07-12 23:40:31 -07:00
Albert Aribaud
d44265ad78 mvgbe: support SoCs other than kirkwood
Rename all references to kirkwood in mvgbe symbols
throughout the whole codebase.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-07-12 23:40:31 -07:00
Thomas Chou
6db6c18b50 nios2: add gpio_request
This will be used by nand_plat.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-07-12 11:30:51 -04:00
Thomas Chou
06c5d30dc3 nios2: add fdt support
This patch adds fdt support to boot linux, followed Michal's
work on microblaze.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-07-12 11:30:51 -04:00
Thomas Chou
cb2da50f0f nios2: use gc sections to reduce image size
Follow the discussion of Charles Manning and Mike Frysinger.
Using gc_sections helps reduce image size.

Configuring for nios2-generic board...
Before,
   text    data     bss     dec     hex filename
 123979    3724   22892  150595   24c43 /tmp/u-boot/u-boot
After,
   text    data     bss     dec     hex filename
 115983    3800   22732  142515   22cb3 /tmp/u-boot/u-boot

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-07-12 11:30:51 -04:00
Ilya Yanok
7c619ddcee mpc8308: support for Freescale MPC8308 cpu
This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also supported. eSDHC, NAND and USB may work but aren't
tested (using ULPI PHY requires additional patch).

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-07-09 15:00:54 -05:00
Steve Sakoman
938717cee1 ARMV7: Restructure OMAP i2c driver to allow code sharing between OMAP3 and OMAP4
This patch modifies the omap24xx driver so that it will also work with OMAP4.

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-07-05 20:00:10 -04:00
Steve Sakoman
bec3dc7599 ARMV7: Restructure OMAP mmc driver to allow code sharing between OMAP3 and OMAP4
The architecture independent header is moved to drivers/mmc, and the architecture
dependent headers reside in asm/arch-omap3 and asm/arch-omap4

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-07-05 20:00:05 -04:00
Steve Sakoman
d34efc767d ARMV7: Add basic support for TI OMAP4
This patch adds minimum support for OMAP4. Code which can be shared
between OMAP3 and OMAP4 is placed in arch/arm/cpu/armv7/omap-common

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-07-05 20:00:00 -04:00
Steve Sakoman
f56348af5d ARM: Rename arch/arm/cpu/arm_cortexa8 to armv7
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9

Cortex A8 and A9 both belong to the armv7 architecture, hence the name change.

The two architectures are similar enough that substantial code can be shared.

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-07-05 19:59:55 -04:00
Steve Sakoman
8f22327a66 OMAP: mmc: add support for second and third mmc channels
This patch adds support for the second and third mmc channels on OMAP3
processors

Boards wishing to use this feature should define CONFIG_SYS_MMC_SET_DEV
in the board config

Tested on Overo

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Tested-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-07-05 19:59:49 -04:00
Mike Frysinger
c5530555f8 Blackfin: unify custom gpio commands
Now that we have a unified gpio layer, the misc partial gpio commands
can be unified and made complete (support all possible gpios).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-05 05:30:07 -04:00
Mike Frysinger
4638b21f2e Blackfin: import gpio/portmux layer from Linux
The current pinmux handling has spread throughout Blackfin drivers and
board code and is getting hideous to maintain.  So import the gpio and
portmux layer from the Blackfin Linux code.  This should spur a serious
of cleanups across the Blackfin tree.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-05 05:30:07 -04:00
Mike Frysinger
ce53fc6601 Blackfin: set up simple NMI handlers for anomaly 05000219
Older on-chip Blackfin bootroms do not create a dummy NMI handler, so set
up one ourselves when anomaly 05000219 applies.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-05 04:18:18 -04:00
Mike Frysinger
53ea1505bb Blackfin: update anomaly lists to latest sheets
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-05 04:18:18 -04:00
Mike Frysinger
b30453ace4 Blackfin: expand EVT1 usage documentation a bit more
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-05 04:18:18 -04:00
Mike Frysinger
a5384ae49a Blackfin: implement bootcount support
The default storage location for bootcount is EVT0.  This version uses
one 32bit value and combines the magic/count value in the upper/lower
16bits.  If there is demand for more, should be easy to do.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-05 04:18:18 -04:00
Mike Frysinger
66a4909a3d Blackfin: clean up trace buffer handling when crashing
Avoid banging on the trace MMRs when debugging is disabled, avoid calling
the funcs multiple times in a row, disable the trace buffer earlier in the
exception handler to avoid eating more user entries, and dump the buffer
before calling the kgdb hook.  This way we maximize useful debugging info
up front rather than needing external tools (like gdb/serial/etc...).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-05 04:18:18 -04:00
Wolfgang Denk
54841ab50c Make sure that argv[] argument pointers are not modified.
The hush shell dynamically allocates (and re-allocates) memory for the
argument strings in the "char *argv[]" argument vector passed to
commands.  Any code that modifies these pointers will cause serious
corruption of the malloc data structures and crash U-Boot, so make
sure the compiler can check that no such modifications are being done
by changing the code into "char * const argv[]".

This modification is the result of debugging a strange crash caused
after adding a new command, which used the following argument
processing code which has been working perfectly fine in all Unix
systems since version 6 - but not so in U-Boot:

int main (int argc, char **argv)
{
	while (--argc > 0 && **++argv == '-') {
/* ====> */	while (*++*argv) {
			switch (**argv) {
			case 'd':
				debug++;
				break;
			...
			default:
				usage ();
			}
		}
	}
	...
}

The line marked "====>" will corrupt the malloc data structures and
usually cause U-Boot to crash when the next command gets executed by
the shell.  With the modification, the compiler will prevent this with
an
	error: increment of read-only location '*argv'

N.B.: The code above can be trivially rewritten like this:

	while (--argc > 0 && **++argv == '-') {
		char *arg = *argv;
		while (*++arg) {
			switch (*arg) {
			...

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2010-07-04 23:55:42 +02:00
Wolfgang Denk
291e9044d4 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-07-04 23:37:00 +02:00
Stefan Roese
4978e60584 ppc4xx: Cleanup Boot/FLASH TLB reassignment for PPC440/460
Background Info:
Some PPC440/460 boards have caches enabled in the Boot/FLASH TLB (via
init.S) to speed up the boot process. In relocate_code (start.S) the
cache inhibit attribute for this TLB is set to disable cache. This is
needed for the CFI FLASH driver.

This patch now cleans this code up:
- CONFIG_SYS_TLB_FOR_BOOT_FLASH is defined to 0 (default TLB) if not
  defined in the top of this file. This way, we can remove an ugly
  #ifdef in this code.
- Replace complex "#if defined(CONFIG_440EP) || defined(CONFIG_GR)..."
  statement with "#if defined(CONFIG_440)".
- Remove unnecessary cache invalidate calls resulting in faster bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:25 +02:00
Stefan Roese
2909ac03f4 ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as well
This patch adds some DDR(2) macros to all PPC4xx's equipped with
this IBM DDR1/2 controller.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:20 +02:00
Stefan Roese
e9c020df96 ppc4xx: DDR2: Complete RDSS configuration on non-SPD based boards
As described in item #10 of the SDRAM initialization (chapter 22.2.9
of the PPC460EX/EXr/GT users manual), RDSS may need to be adjusted. The
code for this is now factored out and executed for non-SPD based boards
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:15 +02:00
Stefan Roese
066003b2c5 ppc4xx: Enable overwriting of default scan window for IBM DDR2 controller
This patch makes it possible to overwrite the default auto-calibration
scan window (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR] values) with
board specific values. The parameters of the weak default function are
corrected as well. This way we don't need the casts any more.

This feature will be used by an upcoming PPC460GT board port.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:10 +02:00
Stefan Roese
db643773fc ppc4xx: Enable PCIe support without PCI support on PPC440/460
By not defining CONFIG_SYS_PCI_MASTER_INIT and CONFIG_SYS_PCI_TARGET_INIT,
PCI support (host and adapter) will not be enabled. But it's still
possible to use the U-Boot PCI infrastructure for the PCIe ports.

This configuration option is needed for a new 460GT board, which uses
PCIe but has PCI disabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:01 +02:00
Stefan Roese
fe7cca715c ppc4xx: Enable booting with Option E on 460EX/EXr/GT
This patch enables booting with option E on the PPC460EX/EXr/GT.
When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0.
The Software Boot Configuration Procedure is needed to engage the
PLL and perform a chip reset.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:25:56 +02:00
Sergey Matyukevich
64203c7b0f USB OHCI support for at91sam9g45 SoC
Add USB OHCI support for at91sam9g45ekes/at91sam9m10g45ek boards.

Note that according to errata from Atmel, OHCI is not operational
on the first revision of at91sam9g45 chip. So this patch enables
OHCI support for later revisions.

Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
2010-06-30 21:37:36 +02:00
Wolfgang Denk
0a9463e935 Merge branch 'master' into next 2010-06-30 01:02:11 +02:00
Michael Weiss
955ea6fc27 powerpc/bootcount: Add bootcount support for MPC512x
This also uses the breadcrumb register as on MPC5200.

Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-06-29 23:13:35 +02:00
Andreas Bießmann
3746a5e65c avr32: add unaligned.h
This patch fixes following error:

zlib.c:31:27: error: asm/unaligned.h: No such file or directory

Suggested-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Andreas Biemann <biessmann@corscience.de>
2010-06-29 22:37:23 +02:00
Andreas Bießmann
eb70d05d74 avr32: disable branch folding
Due to a hardware bug mentioned in latest AP7000 datasheet errata
(revision M from 09.09) branch folding is unreliable.
This patch disables CPUCR.FE bitfield as stated in datasheet.

Signed-off-by: Andreas Biemann <biessmann@corscience.de>
2010-06-29 22:34:11 +02:00
Reinhard Meyer (-VC)
d04250cbe1 Fix (null) problem for AVR32 boards
Currently the U-Boot address ranges for AVR32 boards are
printed like this:
"U-Boot code: (null) -> 0001183c  data: 000188e8 -> 0004e9b0"
This patch fixes this to print:
"U-Boot code: 00000000 -> 0001183c  data: 000188f8 -> 0004e9c0"

Signed-off-by: Reinhard Meyer <info@emk-elektronik.de>
2010-06-29 22:30:57 +02:00
Wolfgang Denk
e365c43d6a Merge branch 'next' of git://git.denx.de/u-boot-ti into next 2010-06-29 21:58:16 +02:00
Wolfgang Denk
8515f081e4 Merge branch 'master' of git://git.denx.de/u-boot-sh into next 2010-06-29 21:37:44 +02:00
Wolfgang Denk
4ccd5510e5 MPC512x: workaround data corruption for unaligned local bus accesses
Commit 460c2ce3 "MPC5200: workaround data corruption for unaligned
local bus accesses" fixed the problem for MPC5200 only, but MPC512x is
affected as well, so apply the same fix here, too.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
2010-06-29 14:41:37 +02:00
Nobuhiro Iwamatsu
754613f740 sh: Add trigger_address_error and support cpu reset
This add support cpu reset by trigger_address_error function.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2010-06-28 11:58:34 +09:00
Nobuhiro Iwamatsu
9a1e3e9fe3 sh: Fix path of irqflags.h
This changes path of irqflags.h from linux/ to asm/.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2010-06-28 11:58:34 +09:00
Nobuhiro Iwamatsu
61973afc59 sh: Fix overflow problem in get_ticks
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2010-06-28 11:58:33 +09:00
Wolfgang Denk
953b7e6291 Remove AmigaOneG3SE board
The AmigaOneG3SE board has been orphaned or a very long time, and
broken for more than 12 releases resp. more than 3 years.  As nobody
seems to be interested any more in this stuff we may as well ged rid
of it, especially as it clutters many areas of the code so it is a
continuous pain for all kinds of ongoing work.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-06-23 23:24:20 +02:00
Wolfgang Denk
ee80fa7b6e Get rid of bogus CONFIG_SYS_BUS_HZ and CONFIG_SYS_CONFIG_BUS_CLK definitions
CONFIG_SYS_BUS_HZ has not really been used anywhere except to be
redined as CONFIG_SYS_BUS_CLK; in addition, the mpc7448hpc2 had the
bogus CONFIG_SYS_CONFIG_BUS_CLK setting which duplicated the
funtionality.  Change all this to use CONFIG_SYS_BUS_CLK consistently.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Frank Gottschling <fgottschling@eltec.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Eran Man <eran@nbase.co.il>
Cc: Stefan Roese <sr@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
2010-06-23 23:24:11 +02:00
Wolfgang Denk
f35f3968c2 Merge branch 'master' into next 2010-06-23 21:17:29 +02:00
Wolfgang Denk
482126e27b Prepare v2010.06-rc3
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-06-23 20:50:54 +02:00
Wolfgang Denk
460c2ce362 MPC5200: workaround data corruption for unaligned local bus accesses
The MPC5200 has a nasty problem that will cause silent data corruption
when performing unaligned 16 or 32 byte accesses when reading from the
local bus - typically this affects reading from flash. The problem can
be easily shown:

=> md fc0c0000 10
fc0c0000: 323e4337 01626f6f 74636d64 3d72756e    2>C7.bootcmd=run
fc0c0010: 206e6574 5f6e6673 00626f6f 7464656c     net_nfs.bootdel
fc0c0020: 61793d35 00626175 64726174 653d3131    ay=5.baudrate=11
fc0c0030: 35323030 00707265 626f6f74 3d656368    5200.preboot=ech
=> md fc0c0001 10
fc0c0001: 65636801 00000074 0000003d 00000020    ech....t...=...
fc0c0011: 0000005f 00000000 00000074 00000061    ..._.......t...a
fc0c0021: 00000000 00000064 00000065 00000035    .......d...e...5
fc0c0031: 00000000 00000062 0000003d 0000006f    .......b...=...o
=> md.w fc0c0001 10
fc0c0001: 0000 3701 0000 6f74 0000 643d 0000 6e20    ..7...ot..d=..n
fc0c0011: 0000 745f 0000 7300 0000 6f74 0000 6c61    ..t_..s...ot..la

This commit implements a workaround at least for the most blatant
problem: using memcpy() from NOR flash. We rename the assembler
routine into __memcpy() and provide a wrapper, which will use a
byte-wise copy loop for unaligned source or target addresses when
reading from NOR flash, and branch to the optimized __memcpy()
in all other cases, thus minimizing the performance impact.

Tested on lite5200b and TQM5200S.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2010-06-23 02:09:20 +02:00
Minkyu Kang
47ea6edfb3 ARM: remove unused VIDEOLFB ATAG
ATAG_VIDEOLFB is not used anywhere.
The belowing warning is occurred due to this ATAG.

[    0.000000] Ignoring unrecognised tag 0x54410008

This patch fixed it.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Martin Krause <Martin.Krause@tqs.de>
2010-06-23 00:11:10 +02:00
Wolfgang Denk
39e9b7c3c3 Merge branch 'master' of /home/wd/git/u-boot/custodians 2010-06-22 22:37:16 +02:00
Albert Aribaud
23fdf05806 Fix wrong orion5x MPP and GIPO writel arguments
Orion5x MPP and GPIO setting code had writel arguments
the wrong way around. Fixed and tested.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
2010-06-22 22:37:00 +02:00
Terry Lv
95bc39e848 ARM: fix bug in macro __arch_ioremap.
Signed-off-by: Terry Lv <r65388@freescale.com>

Fix commit message and code formatting.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-06-22 22:33:06 +02:00
Vitaly Kuzmichev
a71da1b6c9 ARM: Align stack to 8 bytes
The ARM ABI requires that the stack be aligned to 8 bytes as it is noted
in Procedure Call Standard for the ARM Architecture:
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/index.html

Unaligned SP also causes the problem with variable-length arrays
allocation when VLA address becomes less than stack pointer during
aligning of this address, so the next 'push' in the stack overwrites
first 4 bytes of VLA.

Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com>

Tested on tx25(mx25), imx27lite(mx27), qong(mx31) and trab(s3c2400)
Tested-by: Wolfgang Denk <wd@denx.de>
2010-06-22 22:15:07 +02:00
Prakash PM
e6441c4f40 DaVinci: EMAC: Get EMAC_MDIO_PHY_NUM from config files
Currently EMAC_MDIO_PHY_NUM is defined as 1 in emac_defs.h.
Because of this, EMAC does not work on EVMs which do not have phy
connected at 1. Moving the macro to board config file makes this
configurable depending on where the phy is connected on the MDIO bus.

This patch fixes the board reset issue observed during network access
on DM365EVM. EMAC driver was assuming EMAC_MDIO_PHY_NUM as 1
but it is 0 on DM365EVM.

This patch is verified on da830/omap-l137, dm365 and dm644x evms.

Signed-off-by: Prakash PM <prakash.pm@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-22 10:24:43 -04:00
Wolfgang Denk
cd040a4953 arch/arm/cpu/arm_cortexa8/omap3/cache.S: make build with older tools
The push / pop instructions used in this file are available only with
more recent tool chains:

cache.S: Assembler messages:
cache.S:133: Error: bad instruction `push {r0,r1,r2,lr}'
cache.S:160: Error: bad instruction `pop {r1,r2,r3,pc}'
cache.S:164: Error: bad instruction `push {r0,r1,r2,lr}'
cache.S:191: Error: bad instruction `pop {r1,r2,r3,pc}'

Change push/pop into stmfd/ldmfd instructions to support older
versions of binutils as well.

I verified that the modified source code generates exactly the same
binary code.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rix <tom@bumblecow.com>
2010-06-18 16:01:07 +02:00
Wolfgang Denk
54e19a7ded Merge branch 'master' into next
Conflicts:
	Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-06-18 01:20:49 +02:00
Wolfgang Denk
ec6baf53f7 Merge branch 'next' of git://git.denx.de/u-boot-video into next 2010-06-17 22:53:03 +02:00
Wolfgang Denk
1f241263e0 Merge branch 'fix' of git://git.denx.de/u-boot-pxa 2010-06-17 22:31:04 +02:00
Wolfgang Denk
cecda170e7 Merge branch 'master' of git://git.denx.de/u-boot-marvell 2010-06-17 22:22:06 +02:00
Wolfgang Denk
530135dcac Merge branch 'master' of git://git.denx.de/u-boot-ti
Conflicts:
	CONFLICT (rename/add): Rename
	board/davinci/da830evm/Makefile->board/ti/tnetv107xevm/Makefile
	in 89b765c7f6.
	board/ti/tnetv107xevm/Makefile added in HEAD
But files were identical, so no problem.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-06-17 21:59:57 +02:00
Wolfgang Denk
399b09331f Merge branch 'master' of git://git.denx.de/u-boot-arm 2010-06-17 21:06:16 +02:00
Albert Aribaud
0c61e6f925 Initial support for Marvell Orion5x SoC
This patch adds support for the Marvell Orion5x SoC.
It has no use alone, and must be followed by a patch
to add Orion5x support for serial, then support for
the ED Mini V2, an Orion5x-based product from LaCie.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
2010-06-17 19:36:07 +05:30
Anatolij Gustschin
1054382007 video: cfb_console: add weak default video_set_lut()
Do not enforce drivers to provide empty video_set_lut()
if they do not implement indexed color (8 bpp) frame
buffer support. Add default function to the cfb_console
driver and remove empty video_set_lut() functions.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-06-14 12:28:28 +02:00
Marek Vasut
bb596e84eb PXA: Add missing MDREFR bits
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-06-13 13:39:11 +02:00
Marek Vasut
52dc45e5a3 PXA: Add UP2OCR register bit definitions
This register is used on PXA to control the USB Port2 operation (USB Port2 is
the host port).

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-06-13 13:39:11 +02:00
Marek Vasut
3a96ad851f PXA: Align stack to 8 bytes
Part of this patch is by: Mikhail Kshevetskiy.

Stack must be aligned to 8 bytes on PXA (possibly all armv5te) for LDRD/STRD
instructions. In case LDRD/STRD is issued on an unaligned address, the behaviour
is undefined.

The issue was observed when working with the NAND code, which was rendered
disfunctional. Also, the vsprintf() function had serious problems with printing
64bit wide long longs. After aligning the stack, this wrong behaviour is no
longer present.

Tested on:
	Marvell Littleton PXA310 board
	Toradex Colibri PXA320 board
	Aeronix Zipit Z2 PXA270 handheld
	Voipac PXA270 board

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2010-06-13 13:39:02 +02:00
Sudhakar Rajashekhara
89b765c7f6 TI: DaVinci: Add board specific code for da850 EVM
Provides initial support for TI OMAP-L138/DA850 SoC devices on
a Logic PD EVM board.

Provides:
Initial boot and configuration.
Support for i2c.
UART support (console).

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Acked-by: Ben Gardiner <bengardiner@nanometrics.ca>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-10 12:04:42 -04:00
Vaibhav Hiremath
1a5038ca68 AM35x: Add support for EMIF4
This patch adds support for the EMIF4 interface
available in the AM35x processors.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:19 -05:00
Vaibhav Hiremath
cae377b59a omap3: Consolidate SDRC related operations
Consolidated SDRC related functions into one file - sdrc.c

And also replaced sdrc_init with generic memory init
function (mem_init), this generalization of omap memory setup
is necessary to support the new emif4 interface introduced in AM3517.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:18 -05:00
Vaibhav Hiremath
d11212e377 omap3: Calculate CS1 size only when SDRC is
initialized for CS1

From: Vaibhav Hiremath <hvaibhav@ti.com>

The patch makes sure that size for SDRC CS1 gets calculated
only when the CS1 SDRC is initialized.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:18 -05:00
Cyril Chemparathy
3712367c48 ARM1176: TI: TNETV107X soc initial support
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
bunch on on-chip integrated peripherals.  This is an initial commit with
basic functionality, more commits with drivers, etc. to follow.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:17 -05:00
Cyril Chemparathy
678e008c3a ARM1176: Coexist with other ARM1176 platforms
The current ARM1176 CPU specific code is too specific to the SMDK6400
architecture.  The following changes were necessary prerequisites for the
addition of other SoCs based on ARM1176.

Existing board's (SMDK6400) configuration has been modified to keep behavior
unchanged despite these changes.

1. Peripheral port remap configurability
The earlier code had hardcoded remap values specific to s3c64xx in start.S.
This change makes the peripheral port remap addresses and sizes configurable.

2. U-Boot code relocation support
Most architectures allow u-boot code to run initially at a different
address (possibly in NOR) and then get relocated to its final resting place
in RAM.  Added support for this capability in ARM1176 architecture.

3. Disable TCM if necessary
If a ROM based bootloader happened to have initialized TCM, we disable it here
to keep things sane.

4. Remove unnecessary SoC specific includes
ARM1176 code does not really need this SoC specific include.  The presence
of this include prevents builds on other ARM1176 archs.

5. Modified virt-to-phys conversion during MMU disable
The original MMU disable code masks out too many bits from the load address
when it tries to figure out the physical address of the jump target label.
Consequently, it ends up branching to the wrong address after disabling the
MMU.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:17 -05:00
Vaibhav Hiremath
05ee415e31 AM35x: Add support for EMIF4
This patch adds support for the EMIF4 interface
available in the AM35x processors.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 15:20:53 -04:00
Vaibhav Hiremath
8aa5c7cdc4 omap3: Consolidate SDRC related operations
Consolidated SDRC related functions into one file - sdrc.c

And also replaced sdrc_init with generic memory init
function (mem_init), this generalization of omap memory setup
is necessary to support the new emif4 interface introduced in AM3517.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 15:20:34 -04:00
Vaibhav Hiremath
16807ee411 omap3: Calculate CS1 size only when SDRC is
initialized for CS1

From: Vaibhav Hiremath <hvaibhav@ti.com>

The patch makes sure that size for SDRC CS1 gets calculated
only when the CS1 SDRC is initialized.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 15:20:29 -04:00
Cyril Chemparathy
da1ec42aaf ARM1176: TI: TNETV107X soc initial support
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
bunch on on-chip integrated peripherals.  This is an initial commit with
basic functionality, more commits with drivers, etc. to follow.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 14:13:32 -04:00
Cyril Chemparathy
b87996d24a ARM1176: Coexist with other ARM1176 platforms
The current ARM1176 CPU specific code is too specific to the SMDK6400
architecture.  The following changes were necessary prerequisites for the
addition of other SoCs based on ARM1176.

Existing board's (SMDK6400) configuration has been modified to keep behavior
unchanged despite these changes.

1. Peripheral port remap configurability
The earlier code had hardcoded remap values specific to s3c64xx in start.S.
This change makes the peripheral port remap addresses and sizes configurable.

2. U-Boot code relocation support
Most architectures allow u-boot code to run initially at a different
address (possibly in NOR) and then get relocated to its final resting place
in RAM.  Added support for this capability in ARM1176 architecture.

3. Disable TCM if necessary
If a ROM based bootloader happened to have initialized TCM, we disable it here
to keep things sane.

4. Remove unnecessary SoC specific includes
ARM1176 code does not really need this SoC specific include.  The presence
of this include prevents builds on other ARM1176 archs.

5. Modified virt-to-phys conversion during MMU disable
The original MMU disable code masks out too many bits from the load address
when it tries to figure out the physical address of the jump target label.
Consequently, it ends up branching to the wrong address after disabling the
MMU.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-07 14:13:27 -04:00
George G. Davis
409a07c9d7 ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments
The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
instruction which means "Invalidate Both Caches" when in fact the intent
is to clean and invalidate all caches.  So add an "mcr p15, 0, %0, c7,
c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate
Both Caches" instruction to insure that memory is consistent with any
dirty cache lines.

Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
used.

Signed-off-by: George G. Davis <gdavis@mvista.com>
2010-06-01 06:44:09 -05:00
Wolfgang Denk
9bb3b3d440 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-05-30 21:44:07 +02:00
Wolfgang Denk
a81cd434b9 Merge branch 'master' of git://git.denx.de/u-boot-arm 2010-05-30 21:43:05 +02:00
Timur Tabi
6e37a04407 fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition
Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of
struct ccsr_gur.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-30 11:10:32 -05:00
Wolfgang Denk
bd7bb6f8a3 Merge branch 'next' of git://git.denx.de/u-boot-nios 2010-05-28 20:34:39 +02:00
Tom
39c209546a ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 3defb2476166445982a90c12d33f8947e75476c4

Signed-off-by: Tom <Tom@bumblecow.com>
2010-05-28 13:23:16 -05:00
Tom
551bd947bd ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 257dab81413b31b8648becfe11586b3a41e5c29a

Signed-off-by: Tom <Tom@bumblecow.com>
2010-05-28 11:49:42 -05:00
Thomas Chou
1117cbf2ad nios: remove nios-32 arch
The nios-32 arch is obsolete and broken. So it is removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2010-05-28 10:56:04 -04:00
Thomas Chou
6803336c9f nios2: allow STANDALONE_LOAD_ADDR overriding
This patch allows users to override default STANDALONE_LOAD_ADDR.
The gcclibdir path was duplicated in the standalone Makefile and
can be removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-05-28 10:56:04 -04:00
Thomas Chou
8d52ea6db4 nios2: fix div64 issue for gcc4
This patch fixes the run-time error on div64 when built with
gcc4, which was reported by jhwu0625 on nios forum. It merges
math support from libgcc of gcc4. This patch is copied from
nios2-linux.

It works with both gcc3 and gcc4. The old mult.c, divmod.c and
math.h are removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-05-28 10:56:03 -04:00
Thomas Chou
0df01fd3d7 nios2: fix r15 issue for gcc4
The "-ffixed-r15" option doesn't work well for gcc4. Since we
don't use gp for small data with option "-G0", we can use gp
as global data pointer. This allows compiler to use r15. It
is necessary for gcc4 to work properly.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-05-28 10:56:03 -04:00
Thomas Chou
cedd341d55 nios2: add gpio support
This patch adds driver for a trivial gpio core, which is described
in http://nioswiki.com/GPIO. It is used for gpio led and nand flash
interface in u-boot.

When CONFIG_SYS_GPIO_BASE is not defined, board may provide
its own driver.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Tested-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-05-28 10:56:03 -04:00
Wolfgang Wegner
adf55679af add CONFIG_SYS_FEC_FULL_MII for MCF5445x
This patch adds support for full MII interface on MCF5445x (in contrast
to RMII as used on the evaluation boards).

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-05-28 02:15:57 -05:00
Wolfgang Wegner
ae49099755 add CONFIG_SYS_FEC_NO_SHARED_PHY for MCF5445x
This patch adds the possibility to handle seperate PHYs to MCF5445x.
Naming is chosen to resemble the contrary CONFIG_FEC_SHARED_PHY in the
linux kernel.

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-05-28 02:15:55 -05:00
Wolfgang Wegner
e9b43cae1a add missing PCS3 for MCF5445x
This patch adds the code for handling PCS3 (DSPI chip select 3) in
cpu_init.c and m5445x.h

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-05-28 02:15:51 -05:00
Wolfgang Denk
c4976807cb Coding style cleanup, update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-05-26 23:51:22 +02:00
Wolfgang Denk
45b728cdee Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-05-26 22:36:32 +02:00
Kumar Gala
6ece2550d1 Convert Makefiles from COBJS-${} to COBJS-$()
Match style we use almost everywhere else

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-26 22:27:38 +02:00
Michael Weiss
59dde44acb powerpc/bootcount: Fix endianness problem
For CONFIG_SYS_BOOTCOUNT_SINGLEWORD the code had an endianness problem.

Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-05-26 22:26:32 +02:00
Wolfgang Denk
40792d675a a320evb: fix udelay / __udelay confusion
Fix the following compiler problems:

arch/arm/cpu/arm920t/a320/liba320.a(timer.o): In function `udelay':
/home/wd/git/u-boot/work/arch/arm/cpu/arm920t/a320/timer.c:160: multiple definition of `udelay'
lib/libgeneric.a(time.o):/home/wd/git/u-boot/work/lib/time.c:34: first defined here
lib/libgeneric.a(time.o): In function `udelay':
time.c:(.text+0x1c): undefined reference to `__udelay'

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-05-21 23:14:53 +02:00
Wolfgang Denk
92381c41c7 ARM: */timer.c: fix spelling and vertical alignment
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-05-21 23:13:18 +02:00
Kim Phillips
71bd860cce mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c
commit c7190f028f "mpc83xx:
retain POR values of non-configured ACR, SPCR, SCCR, and LCRR
bitfields" incorrectly shifted <register>_<bitfield> (e.g.
ACR_PIPE_DEP) values that were preshifted by their
definition in mpc83xx.h.

this patch removes the unnecessary shifting for the newly
utilized mask values in cpu_init.c, and prevents seemingly
unrelated symptoms such as an mpc8379erdb board from
locking up whilst performing a networking operation,
e.g. a tftp.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-21 15:22:39 -05:00
Horst Kronstorfer
f6970d0c54 Fixed two typos in arch/powerpc/cpu/mpc83xx/start.S.
Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-21 15:22:36 -05:00
Wolfgang Denk
8a452c2c17 Merge branch 'master' of git://git.denx.de/u-boot-imx 2010-05-21 22:22:23 +02:00
Wolfgang Denk
568278e336 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-05-17 23:16:08 +02:00
Wolfgang Denk
1a1e6bf12b Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-05-17 23:11:21 +02:00
Kim Phillips
a4bfc4cc46 mpc83xx: fix NAND bootstrap too big error
commit 167cdad137 "SERIAL: Enable
port-mapped access" inadvertently broke 83xx nand boards by
converting NS16550_init to use io accessors, which expanded
the size of the generated code.

this patch fixes the problem by removing icache functions from
the nand builds, which somewhat follows commit
1a2e203b31 "mpc83xx: turn on icache
in core initialization to improve u-boot boot time"

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-17 14:44:25 -05:00
Wolfgang Denk
cd4b02be1b ARM: add __aeabi_unwind_cpp_pr0() function to avoid linker complaints
Signed-off-by: Wolfgang Denk <wd@denx.de>
Tested-by: Thomas Weber <weber@corscience.de>
2010-05-15 19:50:36 +02:00
York Sun
bcb6c2bb84 Enabled support for Rev 1.3 SPD for DDR2 DIMMs
SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3.
The difference has ben examined and the code is compatible.
Speed bins is not verified on hardware for CL7 at this moment.

This patch also enables SPD Rev 1.x where x is up to "F". According to SPD
spec, the lower nibble is optionally used to determine which additinal bytes
or attribute bits have been defined. Software can safely use defaults. However,
the upper nibble should always be checked.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:54:30 -05:00
Kumar Gala
f54fe87ace 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled
On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.

Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabled and error out if its not in the
driver.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:53:51 -05:00
Kumar Gala
54648985e2 85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled
The new is_serdes_configured covers a broader range of devices than the
PCI specific code.  Use it instead as we convert away from the
is_fsl_pci_cfg() code.

Additionally move to setting LAWs for PCI based on if its configured.
Also updated PCI FDT fixup code to remove PCI controllers from dtb if
they are configured.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:53:51 -05:00
Kumar Gala
6ab4011b79 85xx: Add is_serdes_configured() support to MPC8536 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:53:50 -05:00
Wolfgang Denk
ab92d0fd9a Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-05-09 01:16:51 +02:00
Ron Madrid
3b439792b0 mpc83xx: Add UPMA configuration to SIMPC8313
Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-07 12:19:52 -05:00
Mike Frysinger
f745817e74 update include/asm/ gitignore after move
With the cpu include paths moved, the gitignore paths need updating.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Tom Rix <tom@bumblecow.com>
2010-05-07 00:17:30 +02:00
Stefan Roese
e4a95d112e powerpc: Consolidate bootcount_{store|load} for PowerPC
This patch consolidates bootcount_{store|load} for PowerPC by
implementing a common version in arch/powerpc/lib/bootcount.c. This
code is now used by all PowerPC variants that currently have these
functions implemented.

The functions now use the proper IO-accessor functions to read/write the
values.

This code also supports two different bootcount versions:

a) Use 2 separate words (2 * 32bit) to store the bootcounter
b) Use only 1 word (2 * 16bit) to store the bootcounter

Version b) was already used by MPC5xxx.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
          for 83xx parts
Cc: Michael Zaidman <michael.zaidman@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-05-06 23:28:48 +02:00
Graeme Russ
1f9f3cf6cc sc520: Fix minor DRAM Controller Setup bug
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:20:56 +02:00
Graeme Russ
d20053efdf sc520: Update to new AMD Copyright
AMD recently changed the licensing of the RAM sizing code to the
GPLv2 (or at your option any later version)

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:20:44 +02:00
Graeme Russ
21e67e796b sc520: Board Specific PCI Init
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:18:52 +02:00
Graeme Russ
0278216b76 sc520: Move PCI defines to PCI include file
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:18:41 +02:00
Graeme Russ
5204566e53 sc520: Allow boards to override udelay
If the board has a high precision mico-second timer, it maked sense to use
it instead of the on-chip one

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:17:37 +02:00
Graeme Russ
95ffaba390 x86: Fix support for booting bzImage
Add support for newer (up to 2.6.33) kernels

Add zboot command which takes the address of a bzImage as its first
argument and (optionally) the size of the bzImage as the second argument
(the second argument is needed for older kernels which do not include
the bzImage size in the header)

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:17:01 +02:00
Graeme Russ
79ea6b8701 x86: Provide weak PC/AT compatibility setup function
It is possibly to setup x86 boards to use non-PC/AT configurations. For
example, the sc520 is an x86 CPU with PC/AT and non-PC/AT peripherals.
This function allows the board to set itself up for maximum PC/AT
compatibility just before booting the Linux kernel (the Linux kernel
'just works' if everything is PC/AT compliant)

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:16:54 +02:00
Graeme Russ
bf16500f79 x86: Use CONFIG_SERIAL_MULTI
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:16:46 +02:00
Graeme Russ
153c2d9f23 x86: Fix copying of Real-Mode code into RAM
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:15:58 +02:00
Graeme Russ
2fb1bc4f53 x86: Pass relocation offset into Global Data
In order to locate the 16-bit BIOS code, we need to know the reloaction
offset.

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:15:51 +02:00
Graeme Russ
c14a3669b2 x86: Move GDT to a safe location in RAM
Currently, the GDT is either located in FLASH or in the non-relocated
U-Boot image in RAM. Both of these locations are unsafe as those
locations can be erased during a U-Boot update. Move the GDT into the
highest available memory location and relocate U-Boot to just below it

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:15:43 +02:00
Graeme Russ
077e1958ca x86: Add RAM bootstrap functionality
Add a parameter to the 32-bit entry to indicate if entry is from Real
Mode or not. If entry is from Real Mode, execute the destructive 'sizer'
routine to determine memory size as we are booting cold and running in
Flash. If not entering from Real Mode, we are executing a U-Boot image
from RAM and therefore the memory size is already known (and running
'sizer' will destroy the running image)

There are now two 32-bit entry points. The first is the 'in RAM' entry
point which exists at the start of the U-Boot binary image. As such,
you can load u-boot.bin in RAM and jump directly to the load address
without needing to calculate any offsets. The second entry point is
used by the real-to-protected mode switch

This patch also changes TEXT_BASE to 0x6000000 (in RAM). You can load
the resulting image at 0x6000000 and simple go 0x6000000 from the u-boot
prompt

Hopefully a later patch will completely elliminate any dependency on
TEXT_BASE like a relocatable linux kernel (perfect world)

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:15:31 +02:00
Graeme Russ
759598f82f x86: Split sc520 memory sizing versus reporting
This patch allows the low-level assembler boot-strap to obtain the RAM
size without calling the destructive 'sizer' routine. This allows
boot-strapping from a U-Boot image loaded in RAM

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:14:44 +02:00
Graeme Russ
4dba333b3c x86: Fix sc520 memory size reporting
There is an error in how the assembler version of the sc520 memory size
reporting code works. As a result, it will only ever report at most the
size of one bank of RAM

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:14:32 +02:00
Graeme Russ
9e08efcfee x86: Fix do_go_exec()
This was broken a long time ago by a49864593e
which munged the NIOS and x86 do_go_exec()

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:14:08 +02:00
Graeme Russ
433ff2bdbc x86: Add register dump to crash handlers
Shamelessly steal the Linux x86 crash handling code and shove it into
U-Boot (cool - it fits). Be sure to include suitable attribution to
Linus

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:14:00 +02:00
Graeme Russ
64a0a4995e x86: Fix MMCR Access
Change sc520 MMCR Access to use memory accessor functions

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:13:48 +02:00
Graeme Russ
535ad2db06 x86: #ifdef out getenv_IPaddr()
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:13:34 +02:00
Graeme Russ
721c36705a x86: Add unaligned.h
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2010-05-06 00:13:08 +02:00
Norbert van Bolhuis
3882d7a5a5 ppc: unused memory region too close to current stack pointer
This avoids a possible overwrite of the (end of) ramdisk by u-boot.
The unused memory region for ppc boot currently starts 1k below the
do_bootm->bootm_start->arch_lmb_reserve stack ptr. This isn't enough since
do_bootm->do_bootm_linux->boot_relocate_fdt calls printf which may
very well use more than 1k stack space.

Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
2010-05-05 23:55:02 +02:00
Fabio Estevam
60381d6878 MX51: Fix MX51 CPU detect message
Fix MX51 CPU detect message.

Original string was:
CPU:   Freescale i.MX51 family 3.0V at 800 MHz

which can be misinterpreted as  3.0 Volts instead of the silicon revision.

,change it to:
CPU:   Freescale i.MX51 family rev3.0 at 800 MHz

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2010-05-05 09:48:41 +02:00
Wolfgang Denk
679ec15462 Merge branch 'master' of git://git.denx.de/u-boot-net 2010-05-04 22:57:37 +02:00
Detlev Zundel
6f5f89f011 Remove unused "local_crc32" function.
For code archeologists, this is a nice example of copy and paste history.

Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-05-03 14:52:48 -07:00
Asen Dimov
d6b91e30d3 at91: define matrix registers bit fields
Signed-off-by: Asen Dimov <dimov@ronetix.at>
2010-04-30 05:23:26 -05:00
Stefano Babic
eab40f819d MX31: Support 128MB RAM on QONG module
The QONG module can be downsized and delivered
with 128MB instead of 256MB. The patch adds
run time support for the two different memory
configurations.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:26 -05:00
Stefano Babic
efb9591069 MX31: add pin definitions for NAND controller
Add pin definitions ralted to the NAND controller to be used
to set up the pin multiplexer.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:25 -05:00
Stefano Babic
7d27cd08b4 MX31: add accessor function to get a gpio
The patch adds an accessor function to get the value of a gpio.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:25 -05:00
John Rigby
34196b0a8b MX25 print arm clock instead of mpllclk on boot
Replace call to imx_get_mpllclk with imx_get_armclk
to show frequency of ARM core instead of mpll internal
bus in print_cpuinfo.

Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:24 -05:00
Stefano Babic
5e1fe88fe3 Moved board specific values in config file
The lowlevel_init file contained some hard-coded values
to setup the RAM. These board related values are moved into
the board configuration file.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-04-30 05:23:24 -05:00
Heiko Schocher
1e65c2beb5 arm, mx27: add support for SDHC1 pin init
Signed-off-by: Heiko Schocher <hs@denx.de>
2010-04-30 05:23:23 -05:00
Minkyu Kang
3bb6b037e8 SAMSUNG: make s5p common gpio functions
Because of s5pc1xx gpio is same as s5p seires SoC,
move gpio functions to drvier/gpio/
and modify structure's name from s5pc1xx_ to s5p_.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-04-30 05:23:23 -05:00
Minkyu Kang
46a3b5c8df SAMSUNG: serial: modify name from s5pc1xx to s5p
Because of other s5p series SoC will use these serial functions,
modify function's name and structure's name.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-04-30 05:23:23 -05:00
Alexander Holler
47eb08a97e at91: add defines for RTT and GPBR
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
2010-04-30 05:23:22 -05:00
trix
7bc8768039 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 85b3cce880a19e78286570d5fd004cc3cac06f57

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2010-04-30 05:23:21 -05:00
Wolfgang Denk
d03f4230a6 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-04-28 00:09:53 +02:00
Wolfgang Denk
8e98f5f70b Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx 2010-04-27 23:02:12 +02:00
Wolfgang Denk
c303176aa0 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-04-27 22:57:41 +02:00
Wolfgang Denk
c88d6ab19f Merge branch 'next' of git://git.denx.de/u-boot-nios 2010-04-27 22:53:04 +02:00
Kumar Gala
7e1afb62a7 ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
determining of a device on SERDES is configured.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-26 22:37:57 -05:00
Lan Chunhe
3f0202ed13 mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:56 -05:00
Dave Liu
0c955dafab 85xx: clean up the io_sel for PCI express of P1022
clean up the wrong io_sel for PCI express according to latest manual.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:56 -05:00
Kumar Gala
9ce3c22827 85xx: Fix compile warning
cpu.c: In function 'checkcpu':
cpu.c:47: warning: unused variable 'gur'

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:55 -05:00
Kumar Gala
4db9708b94 85xx: Convert cpu_init_f code to use out_be32 for LBC registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:55 -05:00
Dave Liu
99bac479dd fsl-ddr: Add extra cycle to turnaround times
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:53 -05:00
Dave Liu
f8d05e5e58 fsl-ddr: add the macro for Rtt_Nom definition
add the macro definition for Rtt_Nom termination value for DDR3

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:53 -05:00
Kumar Gala
1231c498e0 ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines
Added some needed fines and some misc additional defines
used by p4080 initialization.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:52 -05:00
Dave Liu
17d90f31a8 ppc/p4080: Extend the GUTS memory map
Extend pin control and clock control to GUTS memory map

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:52 -05:00
Srikanth Srinivasan
ab48ca1a66 ppc/p4080: Fix synchronous frequency calculations
When DDR is in synchronous mode, the existing code assigns sysclk
frequency to DDR frequency.  It should be synchronous with the platform
frequency.  CPU frequency is based on platform frequency in synchronous
mode.

Also fix:

* Fixes the bit mask for DDR_SYNC (RCWSR5[184])
* Corrects the detection of synchronous mode.

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:51 -05:00
Thomas Chou
441cac10d8 nios2: fix no flash, add nand and mmc init in board.c
This patch fixes error when CONFIG_SYS_NO_FLASH. And adds
nand flash and mmc initialization, which should go before
env initialization.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:23 -04:00
Thomas Chou
fd2712d0b1 nios2: consolidate reset initialization
Global interrupt should be disabled from the beginning.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:23 -04:00
Thomas Chou
7e812f2e9c nios2: add dma_alloc_coherent
This function return cache-line aligned allocation which is mapped
to uncached io region.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:22 -04:00
Thomas Chou
0dc1c7f692 nios2: add 64 bits swab support
This patch adds 64 bits swab support. Most 32 bits processors use
this. We need 64 bits swab for UBI.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:22 -04:00
Thomas Chou
dd168ef5b8 nios2: allow link script overriding from boards
This patch allow boards to override the default link script.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-24 18:21:22 -04:00
Anatolij Gustschin
2ebdb9a9d7 mpc5121: add common post_word_load/store code
Add common post_word_load/post_word_store routines
for all mpc5121 boards. pdm360ng board POST support
added by subsequent patch needs them.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:39 +02:00
Anatolij Gustschin
a3921eefa1 mpc5121: add support for PDM360NG board
PDM360NG is a MPC5121E based board by ifm ecomatic gmbh.

Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:37 +02:00
Anatolij Gustschin
b9947bbb08 mpc5121: determine RAM size using get_ram_size()
Configure CONFIG_SYS_MAX_RAM_SIZE address range in
DDR Local Access Window and determine the RAM size.
Fix DDR LAW afterwards using detected RAM size.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:35 +02:00
Anatolij Gustschin
5d937e8b59 mpc512x: make MEM IO Control configuration a board config option
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:34 +02:00
Anatolij Gustschin
8e234e33bf mpc5121: add PSC serial communication routines
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:32 +02:00
Anatolij Gustschin
e3b28e6732 mpc512x: add multi serial PSC support
Extend mpc512x serial driver to support multiple PSC ports.

Subsequent patches for PDM360NG board support make use of this
functionality by defining CONFIG_SERIAL_MULTI in the board config
file. Additionally the used PSC devices are specified by defining
e.g. CONFIG_SYS_PSC1, CONFIG_SYS_PSC4 and CONFIG_SYS_PSC6.

Support for PSC devices other than 1, 3, 4 and 6 is not added
by this patch because these aren't used currently. In the future
it can be easily added using DECLARE_PSC_SERIAL_FUNCTIONS(N) and
INIT_PSC_SERIAL_STRUCTURE(N) macros in cpu/mpc512x/serial.c.
Additionally you have to add code for registering added
devices in serial_initialize() in common/serial.c.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:30 +02:00
Anatolij Gustschin
fbb0030e38 serial: struct serial_device: add uninit() entry for drivers
Subsequent patch extends mpc512x serial driver to support
multiple PSC ports. The driver will provide an uninit()
function to stop the serial controller and to disable the
controller's clock. Adding uninit() entry to struct serial_device
allows disabling the serial controller after usage of
a stdio serial device.

This patch adds uninit() entry to the struct serial_device
and fixes initialization of this structure in the code
accordingly.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 21:34:07 +02:00
Wolfgang Denk
a77034a8df Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-04-24 21:16:57 +02:00
Wolfgang Denk
500fbae204 Merge branch 'master' of git://git.denx.de/u-boot-microblaze 2010-04-24 21:13:31 +02:00
Kim Phillips
1a2e203b31 mpc83xx: turn on icache in core initialization to improve u-boot boot time
before, MPC8349ITX boots u-boot in 4.3sec:

        column1 is elapsed time since first message
        column2 is elapsed time since previous message
        column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA:  Configured for compact flash
0.032 0.000: I2C:   ready
0.061 0.028: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI:   Bus Dev VenId DevId Class Int
2.652 0.011:         00  10  1095  3114  0180  00
2.652 0.000: PCI:   Bus Dev VenId DevId Class Int
2.652 0.000: In:    serial
2.652 0.000: Out:   serial
2.652 0.000: Err:   serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE:   Bus 0: .** Timeout **

after, MPC8349ITX boots u-boot in 3.0sec:

0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA:  Configured for compact flash
0.038 0.000: I2C:   ready
0.038 0.000: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI:   Bus Dev VenId DevId Class Int
1.390 0.000:         00  10  1095  3114  0180  00
1.390 0.000: PCI:   Bus Dev VenId DevId Class Int
1.400 0.010: In:    serial
1.400 0.000: Out:   serial
1.400 0.000: Err:   serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE:   Bus 0: .** Timeout **

also tested on these boards (albeit with a less accurate
boottime measurement method):

seconds: before  after
8349MDS  ~2.6    ~2.2
8360MDS  ~2.8    ~2.6
8313RDB  ~2.5    ~2.3 #nand boot
837xRDB  ~3.1    ~2.3

also tested on an 8323ERDB.

v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:44:56 -05:00
Kim Phillips
dfe812c744 mpc83xx: use "A" nomenclature only on mpc834x and mpc836x families
marketing didn't extend their postpend-with-an-A naming strategy
on rev.2's and higher beyond the first two 83xx families.  This
patch stops us from misreporting we're running e.g., on an MPC8313EA,
when such a name doesn't exist.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:34:49 -05:00
Rini van Zetten
27ef578df7 mpc83xx: Use CONFIG_FSL_ESDHC to enable sdhc clk
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define
instead of a platform define. This will enable all the 83xx
platforms to use sdhc_clk based on CONFIG_FSL_ESDHC.  It's
the same patch as commit 6b9ea08c50
for the ppc/85xx.

Signed-off-by: Rini <rini@arvoo.nl>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:34:22 -05:00
Stefan Roese
a47a12becf Move arch/ppc to arch/powerpc
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.

Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-04-21 23:42:38 +02:00
Stefan Roese
cf6eb6da43 ppc4xx: TLB init file cleanup
This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.

Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-19 15:29:03 +02:00
Scott McNutt
254ab7bd46 nios2: Move individual board linker scripts to common script in cpu tree.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-04-16 16:12:39 -04:00
Michal Simek
8ff972c6e9 microblaze: Consolidate cache code
Merge cpu and lib cache code.
Flush cache before disabling.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:56:33 +02:00
Michal Simek
9b4d905690 microblaze: Flush cache before jumping to kernel
There is used max cache size on system which doesn't define
cache size.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:16:04 +02:00
Michal Simek
70524883b0 microblaze: Support system with WB cache
WB cache use different instruction that WT cache but the major code
is that same. That means that wdc.flush on system with WT cache
do the same thing as before.

You need newer toolchain with wdc.flush support.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:16:02 +02:00
Michal Simek
9769b73f60 microblaze: Change initialization sequence
env_relocation should be called first.
Added stdio_init too.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:56 +02:00
Michal Simek
e6177b36b8 microblaze: Change cache report messages
It is more accurate to show that caches are OFF instead of FAIL.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:36 +02:00
Michal Simek
8125c980cc microblaze: Fix interrupt handler code
It is better to read ivr and react on it than do long parsing from
two regs. Interrupt controller returs actual irq number.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:34 +02:00
Michal Simek
b26640971a microblaze: Move FSL initialization to board.c
Move FSL out of interrupt controller.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:33 +02:00
Michal Simek
5bbcb6cf22 microblaze: Move timer initialization to board.c
I would like to handle case where system doesn't contain
intc that's why I need timer initialization out of intc code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:31 +02:00
Michal Simek
cc53690e05 microblaze: Fix irq.S code
It is ancient code. There is possible to save several instructions
just if we use offset instead of addik

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:30 +02:00
Arun Bhanu
398b1d57a6 microblaze: Add FDT support
This patch adds FDT (flattened device tree) support to microblaze arch.

Tested with Linux arch/microblaze kernels with and without compiled in
FDT on Xilinx ML506 board.

Signed-off-by: Arun Bhanu <arun@bhanu.net>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-16 12:15:13 +02:00
Stefan Roese
2a72e9ed18 ppc4xx: Add option for PPC440SPe ports without old Rev. A support
The 440SPe Rev. A is quite old and newer 440SPe boards don't need support
for this CPU revision. Since removing support for this older version
simplifies the creation for newer U-Boot ports, this patch now enables
440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By
defining this in the board config header, Rev. A will still be supported.
Otherwise (default for newer board ports), Rev. A will not be supported.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 10:27:39 +02:00
Peter Tyser
37e4dafaae nios2: Move cpu/nios2/* to arch/nios2/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:27 +02:00
Peter Tyser
6a8a2b7058 nios: Move cpu/nios/* to arch/nios/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:27 +02:00
Peter Tyser
1e9c26578e sparc: Move cpu/leon[23] to arch/sparc/cpu/leon[23]
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:26 +02:00
Peter Tyser
e9a882803e i386: Move cpu/i386/* to arch/i386/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:26 +02:00
Peter Tyser
6260fb0458 microblaze: Move cpu/microblaze/* to arch/microblaze/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:26 +02:00
Peter Tyser
8a15c2d10b avr32: Move cpu/at32ap/* to arch/avr32/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:25 +02:00
Peter Tyser
1e3827d9cf mips: Move cpu/mips/* to arch/mips/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:25 +02:00
Peter Tyser
c6fb83d217 blackfin: Move cpu/blackfin/* to arch/blackfin/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:25 +02:00
Peter Tyser
a414553485 m68k: Move cpu/$CPU to arch/m68k/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:24 +02:00
Peter Tyser
84ad688473 arm: Move cpu/$CPU to arch/arm/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:24 +02:00
Peter Tyser
8f0fec74ac sh: Move cpu/$CPU to arch/sh/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:17 +02:00
Peter Tyser
8d1f268204 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:16 +02:00
Peter Tyser
819833af39 Move architecture-specific includes to arch/$ARCH/include/asm
This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:12 +02:00
Peter Tyser
ea0364f1bb Move lib_$ARCH directories to arch/$ARCH/lib
Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk

This change is intended to clean up the top-level directory structure
and more closely mimic Linux's directory organization.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:03 +02:00