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https://github.com/AsahiLinux/u-boot
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AM35x: Add support for EMIF4
This patch adds support for the EMIF4 interface available in the AM35x processors. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Vaibhav Hiremath
Sandeep Paulraj
parent
3d9f0ffdda
commit
05ee415e31
6 changed files with 274 additions and 1 deletions
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@ -37,6 +37,7 @@ COBJS += syslib.o
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COBJS += sys_info.o
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COBJS += timer.o
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COBJS-$(CONFIG_EMIF4) += emif4.o
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COBJS-$(CONFIG_SDRC) += sdrc.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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168
arch/arm/cpu/arm_cortexa8/omap3/emif4.c
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168
arch/arm/cpu/arm_cortexa8/omap3/emif4.c
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@ -0,0 +1,168 @@
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/*
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* Author :
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Based on mem.c and sdrc.c
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*
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* Copyright (C) 2010
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* Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/emif4.h>
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extern omap3_sysinfo sysinfo;
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static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
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/*
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* is_mem_sdr -
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* - Return 1 if mem type in use is SDR
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*/
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u32 is_mem_sdr(void)
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{
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return 0;
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}
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/*
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* get_sdr_cs_size -
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* - Get size of chip select 0/1
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*/
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u32 get_sdr_cs_size(u32 cs)
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{
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u32 size;
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/* TODO: Calculate the size based on EMIF4 configuration */
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size = CONFIG_SYS_CS0_SIZE;
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return size;
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}
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/*
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* get_sdr_cs_offset -
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* - Get offset of cs from cs0 start
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*/
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u32 get_sdr_cs_offset(u32 cs)
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{
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u32 offset = 0;
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return offset;
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}
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/*
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* do_emif4_init -
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* - Init the emif4 module for DDR access
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* - Early init routines, called from flash or SRAM.
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*/
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void do_emif4_init(void)
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{
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unsigned int regval;
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/* Set the DDR PHY parameters in PHY ctrl registers */
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regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
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EMIF4_DDR1_EXT_STRB_DIS);
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writel(regval, &emif4_base->ddr_phyctrl1);
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writel(regval, &emif4_base->ddr_phyctrl1_shdw);
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writel(0, &emif4_base->ddr_phyctrl2);
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/* Reset the DDR PHY and wait till completed */
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regval = readl(&emif4_base->sdram_iodft_tlgc);
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regval |= (1<<10);
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writel(regval, &emif4_base->sdram_iodft_tlgc);
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/*Wait till that bit clears*/
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while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
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/*Re-verify the DDR PHY status*/
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while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
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regval |= (1<<0);
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writel(regval, &emif4_base->sdram_iodft_tlgc);
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/* Set SDR timing registers */
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regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
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EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
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EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
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EMIF4_TIM1_T_RP);
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writel(regval, &emif4_base->sdram_time1);
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writel(regval, &emif4_base->sdram_time1_shdw);
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regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
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EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
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EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
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writel(regval, &emif4_base->sdram_time2);
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writel(regval, &emif4_base->sdram_time2_shdw);
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regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
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writel(regval, &emif4_base->sdram_time3);
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writel(regval, &emif4_base->sdram_time3_shdw);
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/* Set the PWR control register */
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regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
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EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
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writel(regval, &emif4_base->sdram_pwr_mgmt);
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writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
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/* Set the DDR refresh rate control register */
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regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
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writel(regval, &emif4_base->sdram_refresh_ctrl);
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writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
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/* set the SDRAM configuration register */
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regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
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EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
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EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
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EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
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EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
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EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
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writel(regval, &emif4_base->sdram_config);
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}
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/*
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* dram_init -
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* - Sets uboots idea of sdram size
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*/
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int size0 = 0, size1 = 0;
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size0 = get_sdr_cs_size(CS0);
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/*
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* If a second bank of DDR is attached to CS1 this is
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* where it can be started. Early init code will init
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* memory on CS0.
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*/
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if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
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size1 = get_sdr_cs_size(CS1);
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = size0;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
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gd->bd->bi_dram[1].size = size1;
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return 0;
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}
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/*
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* mem_init() -
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* - Initialize memory subsystem
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*/
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void mem_init(void)
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{
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do_emif4_init();
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}
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@ -216,6 +216,30 @@ struct sdrc {
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struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
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};
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/* EMIF4 */
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typedef struct emif4 {
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unsigned int sdram_sts;
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unsigned int sdram_config;
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unsigned int res1;
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unsigned int sdram_refresh_ctrl;
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unsigned int sdram_refresh_ctrl_shdw;
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unsigned int sdram_time1;
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unsigned int sdram_time1_shdw;
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unsigned int sdram_time2;
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unsigned int sdram_time2_shdw;
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unsigned int sdram_time3;
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unsigned int sdram_time3_shdw;
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unsigned char res2[8];
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unsigned int sdram_pwr_mgmt;
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unsigned int sdram_pwr_mgmt_shdw;
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unsigned char res3[32];
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unsigned int sdram_iodft_tlgc;
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unsigned char res4[128];
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unsigned int ddr_phyctrl1;
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unsigned int ddr_phyctrl1_shdw;
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unsigned int ddr_phyctrl2;
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} emif4_t;
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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79
arch/arm/include/asm/arch-omap3/emif4.h
Normal file
79
arch/arm/include/asm/arch-omap3/emif4.h
Normal file
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@ -0,0 +1,79 @@
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/*
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* Auther:
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Copyright (C) 2010
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* Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _EMIF_H_
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#define _EMIF_H_
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/*
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* Configuration values
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*/
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#define EMIF4_TIM1_T_RP (0x3 << 25)
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#define EMIF4_TIM1_T_RCD (0x3 << 21)
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#define EMIF4_TIM1_T_WR (0x3 << 17)
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#define EMIF4_TIM1_T_RAS (0x8 << 12)
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#define EMIF4_TIM1_T_RC (0xA << 6)
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#define EMIF4_TIM1_T_RRD (0x2 << 3)
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#define EMIF4_TIM1_T_WTR (0x2)
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#define EMIF4_TIM2_T_XP (0x2 << 28)
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#define EMIF4_TIM2_T_ODT (0x0 << 25)
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#define EMIF4_TIM2_T_XSNR (0x1C << 16)
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#define EMIF4_TIM2_T_XSRD (0xC8 << 6)
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#define EMIF4_TIM2_T_RTP (0x1 << 3)
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#define EMIF4_TIM2_T_CKE (0x2)
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#define EMIF4_TIM3_T_RFC (0x25 << 4)
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#define EMIF4_TIM3_T_RAS_MAX (0x7)
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#define EMIF4_PWR_IDLE_MODE (0x2 << 30)
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#define EMIF4_PWR_DPD_DIS (0x0 << 10)
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#define EMIF4_PWR_DPD_EN (0x1 << 10)
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#define EMIF4_PWR_LP_MODE (0x0 << 8)
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#define EMIF4_PWR_PM_TIM (0x0)
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#define EMIF4_INITREF_DIS (0x0 << 31)
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#define EMIF4_REFRESH_RATE (0x50F)
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#define EMIF4_CFG_SDRAM_TYP (0x2 << 29)
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#define EMIF4_CFG_IBANK_POS (0x0 << 27)
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#define EMIF4_CFG_DDR_TERM (0x0 << 24)
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#define EMIF4_CFG_DDR2_DDQS (0x1 << 23)
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#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20)
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#define EMIF4_CFG_SDR_DRV (0x0 << 18)
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#define EMIF4_CFG_NARROW_MD (0x0 << 14)
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#define EMIF4_CFG_CL (0x5 << 10)
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#define EMIF4_CFG_ROWSIZE (0x0 << 7)
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#define EMIF4_CFG_IBANK (0x3 << 4)
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#define EMIF4_CFG_EBANK (0x0 << 3)
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#define EMIF4_CFG_PGSIZE (0x2)
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/*
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* EMIF4 PHY Control 1 register configuration
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*/
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#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7)
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#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7)
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#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6)
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#define EMIF4_DDR1_PWRDN_EN (0x1 << 6)
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#define EMIF4_DDR1_READ_LAT (0x6 << 0)
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#endif /* endif _EMIF_H_ */
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@ -33,6 +33,7 @@ void per_clocks_enable(void);
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void memif_init(void);
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void sdrc_init(void);
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void do_sdrc_init(u32, u32);
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void emif4_init(void);
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void gpmc_init(void);
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
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u32 size);
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@ -33,7 +33,7 @@
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
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#define CONFIG_EMIF4 1 /* The chip has EMIF4 controller */
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#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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