mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
commit
9662317142
13 changed files with 440 additions and 33 deletions
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@ -767,6 +767,13 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
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debug("\n\n");
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#if defined(CONFIG_DDR_RFDC_FIXED)
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mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
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size = 512;
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rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK;
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mfsdram(SDRAM_RDCC, rdcc); /* record this value */
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cal->rdcc = rdcc;
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#else /* CONFIG_DDR_RFDC_FIXED */
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in_window = 0;
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rdcc = 0;
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@ -830,6 +837,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
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rffd_average = SDRAM_RFDC_RFFD_MAX;
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mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
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#endif /* CONFIG_DDR_RFDC_FIXED */
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rffd = rffd_average;
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in_window = 0;
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@ -1211,10 +1219,14 @@ u32 DQS_autocalibration(void)
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debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
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rqdc_reg);
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#if defined(CONFIG_DDR_RFDC_FIXED)
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mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
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#else /* CONFIG_DDR_RFDC_FIXED */
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mfsdram(SDRAM_RFDC, rfdc_reg);
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rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
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mtsdram(SDRAM_RFDC, rfdc_reg |
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SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
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#endif /* CONFIG_DDR_RFDC_FIXED */
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mfsdram(SDRAM_RFDC, rfdc_reg);
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debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",
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@ -51,6 +51,9 @@ COBJS += cpu_init.o
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COBJS += denali_data_eye.o
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COBJS += denali_spd_ddr2.o
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COBJS += ecc.o
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ifdef CONFIG_CMD_ECCTEST
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COBJS += cmd_ecctest.o
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endif
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COBJS += fdt.o
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COBJS += interrupts.o
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COBJS += iop480_uart.o
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284
arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
Normal file
284
arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
Normal file
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@ -0,0 +1,284 @@
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/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
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defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
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#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
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#if defined(CONFIG_405EX)
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/*
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* Currently only 405EX uses 16bit data bus width as an alternative
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* option to 32bit data width (SDRAM0_MCOPT1_WDTH)
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*/
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#define SDRAM_DATA_ALT_WIDTH 2
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#else
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#define SDRAM_DATA_ALT_WIDTH 8
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#endif
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#if defined(CONFIG_SYS_OCM_BASE)
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#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_OCM_BASE
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#endif
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#if defined(CONFIG_SYS_ISRAM_BASE)
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#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_ISRAM_BASE
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#endif
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#if !defined(CONFIG_FUNC_ISRAM_ADDR)
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#error "No internal SRAM/OCM provided!"
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#endif
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#define force_inline inline __attribute__ ((always_inline))
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static inline void machine_check_disable(void)
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{
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mtmsr(mfmsr() & ~MSR_ME);
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}
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static inline void machine_check_enable(void)
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{
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mtmsr(mfmsr() | MSR_ME);
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}
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/*
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* These helper functions need to be inlined, since they
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* are called from the functions running from internal SRAM.
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* SDRAM operation is forbidden at that time, so calling
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* functions in SDRAM has to be avoided.
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*/
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static force_inline void wait_ddr_idle(void)
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{
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u32 val;
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do {
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mfsdram(SDRAM_MCSTAT, val);
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} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
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}
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static force_inline void recalibrate_ddr(void)
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{
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u32 val;
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/*
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* Rewrite RQDC & RFDC to calibrate again. If this is not
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* done, the SDRAM controller is working correctly after
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* changing the MCOPT1_MCHK bits.
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*/
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mfsdram(SDRAM_RQDC, val);
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mtsdram(SDRAM_RQDC, val);
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mfsdram(SDRAM_RFDC, val);
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mtsdram(SDRAM_RFDC, val);
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}
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static force_inline void set_mcopt1_mchk(u32 bits)
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{
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u32 val;
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wait_ddr_idle();
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mfsdram(SDRAM_MCOPT1, val);
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mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | bits);
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recalibrate_ddr();
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}
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/*
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* The next 2 functions are copied to internal SRAM/OCM and run
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* there. No function calls allowed here. No SDRAM acitivity should
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* be done here.
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*/
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static void inject_ecc_error(void *ptr, int par)
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{
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u32 val;
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/*
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* Taken from PPC460EX/EXr/GT users manual (Rev 1.21)
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* 22.2.17.13 ECC Diagnostics
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*
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* Items 1 ... 5 are already done by now, running from RAM
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* with ECC enabled
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*/
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out_be32(ptr, 0x00000000);
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val = in_be32(ptr);
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/* 6. Set memory controller to no error checking */
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set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON);
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/* 7. Modify one or two bits for error simulation */
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if (par == 1)
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out_be32(ptr, in_be32(ptr) ^ 0x00000001);
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else
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out_be32(ptr, in_be32(ptr) ^ 0x00000003);
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/* 8. Wait for SDRAM idle */
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val = in_be32(ptr);
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set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
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/* Wait for SDRAM idle */
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wait_ddr_idle();
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/* Continue with 9. in calling function... */
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}
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static void rewrite_ecc_parity(void *ptr, int par)
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{
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u32 current_address = (u32)ptr;
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u32 end_address;
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u32 address_increment;
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u32 mcopt1;
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u32 val;
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/*
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* Fill ECC parity byte again. Otherwise further accesses to
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* the failure address will result in exceptions.
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*/
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/* Wait for SDRAM idle */
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val = in_be32(0x00000000);
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set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN);
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/* ECC bit set method for non-cached memory */
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mfsdram(SDRAM_MCOPT1, mcopt1);
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if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
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address_increment = 4;
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else
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address_increment = SDRAM_DATA_ALT_WIDTH;
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end_address = current_address + CONFIG_SYS_CACHELINE_SIZE;
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while (current_address < end_address) {
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*((unsigned long *)current_address) = 0;
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current_address += address_increment;
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}
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set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
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/* Wait for SDRAM idle */
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wait_ddr_idle();
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}
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static int do_ecctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 old_val;
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u32 val;
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u32 *ptr;
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void (*sram_func)(u32 *, int);
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int error;
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if (argc < 3) {
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cmd_usage(cmdtp);
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return 1;
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}
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ptr = (u32 *)simple_strtoul(argv[1], NULL, 16);
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error = simple_strtoul(argv[2], NULL, 16);
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if ((error < 1) || (error > 2)) {
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cmd_usage(cmdtp);
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return 1;
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}
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printf("Using address %p for %d bit ECC error injection\n",
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ptr, error);
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/*
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* Save value to restore it later on
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*/
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old_val = in_be32(ptr);
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/*
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* Copy ECC injection function into internal SRAM/OCM
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*/
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sram_func = (void *)CONFIG_FUNC_ISRAM_ADDR;
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memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, inject_ecc_error, 0x10000);
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/*
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* Disable interrupts and exceptions before calling this
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* function in internal SRAM/OCM
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*/
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disable_interrupts();
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machine_check_disable();
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eieio();
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/*
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* Jump to ECC simulation function in internal SRAM/OCM
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*/
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(*sram_func)(ptr, error);
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/* 10. Read the corresponding address */
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val = in_be32(ptr);
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/*
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* Read and print ECC status register/info:
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* The faulting address is only known upon uncorrectable ECC
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* errors.
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*/
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mfsdram(SDRAM_ECCES, val);
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if (val & SDRAM_ECCES_CE)
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printf("ECC: Correctable error\n");
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if (val & SDRAM_ECCES_UE) {
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printf("ECC: Uncorrectable error at 0x%02x%08x\n",
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mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
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}
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/*
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* Clear pending interrupts/exceptions
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*/
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mtsdram(SDRAM_ECCES, 0xffffffff);
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mtdcr(SDRAM_ERRSTATLL, 0xff000000);
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set_mcsr(get_mcsr());
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|
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/* Now enable interrupts and exceptions again */
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eieio();
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machine_check_enable();
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enable_interrupts();
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/*
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* The ECC parity byte need to be re-written for the
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* corresponding address. Otherwise future accesses to it
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* will result in exceptions.
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*
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* Jump to ECC parity generation function
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*/
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memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, rewrite_ecc_parity, 0x10000);
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(*sram_func)(ptr, 0);
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/*
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* Restore value in corresponding address
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*/
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out_be32(ptr, old_val);
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return 0;
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}
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U_BOOT_CMD(
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ecctest, 3, 0, do_ecctest,
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"Test ECC by single and double error bit injection",
|
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"address 1/2"
|
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);
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#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
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#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
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@ -130,7 +130,26 @@ static void program_ecc_addr(unsigned long start_address,
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/* clear ECC error repoting registers */
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mtsdram(SDRAM_ECCES, 0xffffffff);
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mtdcr(0x4c, 0xffffffff);
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
|
||||
/*
|
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* IBM DDR(1) core (440GX):
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* Clear Mx bits in SDRAM0_BESR0/1
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*/
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mtsdram(SDRAM0_BESR0, 0xffffffff);
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mtsdram(SDRAM0_BESR1, 0xffffffff);
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#elif defined(CONFIG_440)
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||||
/*
|
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* 440/460 DDR2 core:
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||||
* Clear EMID (Error PLB Master ID) in MQ0_ESL
|
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*/
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mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
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||||
#else
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||||
/*
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* 405EX(r) DDR2 core:
|
||||
* Clear M0ID (Error PLB Master ID) in SDRAM_BESR
|
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*/
|
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mtsdram(SDRAM_BESR, 0xf0000000);
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#endif
|
||||
|
||||
mtsdram(SDRAM_MCOPT1,
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(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
|
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|
|
|
|||
|
|
@ -209,6 +209,22 @@ MachineCheckException(struct pt_regs *regs)
|
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/* Clear MCSR */
|
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mtspr(SPRN_MCSR, val);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
|
||||
/*
|
||||
* Read and print ECC status register/info:
|
||||
* The faulting address is only known upon uncorrectable ECC
|
||||
* errors.
|
||||
*/
|
||||
mfsdram(SDRAM_ECCES, val);
|
||||
if (val & SDRAM_ECCES_CE)
|
||||
printf("ECC: Correctable error\n");
|
||||
if (val & SDRAM_ECCES_UE) {
|
||||
printf("ECC: Uncorrectable error at 0x%02x%08x\n",
|
||||
mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
|
||||
}
|
||||
#endif /* CONFIG_DDR_ECC ... */
|
||||
|
||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
mfsdram(DDR0_00, val) ;
|
||||
printf("DDR0: DDR0_00 %lx\n", val);
|
||||
|
|
|
|||
|
|
@ -63,6 +63,8 @@
|
|||
#define SDRAM_CFG0 0x20 /* memory controller options 0 */
|
||||
#define SDRAM_CFG1 0x21 /* memory controller options 1 */
|
||||
|
||||
#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */
|
||||
#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */
|
||||
#define SDRAM0_BEAR 0x0010 /* bus error address reg */
|
||||
#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
|
||||
#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
|
||||
|
|
@ -363,6 +365,7 @@
|
|||
/*
|
||||
* Memory controller registers
|
||||
*/
|
||||
#ifdef CONFIG_405EX
|
||||
#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
|
||||
#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
|
||||
#define SDRAM_BEARL 0x02 /* PLB bus error address low */
|
||||
|
|
@ -371,11 +374,10 @@
|
|||
#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
|
||||
#define SDRAM_PLBOPT 0x08 /* PLB slave options */
|
||||
#define SDRAM_PUABA 0x09 /* PLB upper address base */
|
||||
#ifndef CONFIG_405EX
|
||||
#define SDRAM_MCSTAT 0x14 /* memory controller status */
|
||||
#else
|
||||
#define SDRAM_MCSTAT 0x1F /* memory controller status */
|
||||
#endif
|
||||
#else /* CONFIG_405EX */
|
||||
#define SDRAM_MCSTAT 0x14 /* memory controller status */
|
||||
#endif /* CONFIG_405EX */
|
||||
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
|
||||
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
|
||||
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
|
||||
|
|
|
|||
|
|
@ -34,7 +34,17 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define CONFIG_SYS_BCSR3_PCIE 0x10
|
||||
struct board_bcsr {
|
||||
u8 board_id;
|
||||
u8 cpld_rev;
|
||||
u8 led_user;
|
||||
u8 board_status;
|
||||
u8 reset_ctrl;
|
||||
u8 flash_ctrl;
|
||||
u8 eth_ctrl;
|
||||
u8 usb_ctrl;
|
||||
u8 irq_ctrl;
|
||||
};
|
||||
|
||||
#define BOARD_CANYONLANDS_PCIE 1
|
||||
#define BOARD_CANYONLANDS_SATA 2
|
||||
|
|
@ -112,6 +122,9 @@ int board_early_init_f(void)
|
|||
{
|
||||
#if !defined(CONFIG_ARCHES)
|
||||
u32 sdr0_cust0;
|
||||
struct board_bcsr *bcsr_data =
|
||||
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -172,14 +185,10 @@ int board_early_init_f(void)
|
|||
|
||||
#if !defined(CONFIG_ARCHES)
|
||||
/* Enable ethernet and take out of reset */
|
||||
out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
|
||||
out_8(&bcsr_data->eth_ctrl, 0) ;
|
||||
|
||||
/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
|
||||
out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
|
||||
|
||||
/* Enable USB host & USB-OTG */
|
||||
out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
|
||||
|
||||
out_8(&bcsr_data->flash_ctrl, 0) ;
|
||||
mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
|
||||
|
||||
/* Setup PLB4-AHB bridge based on the system address map */
|
||||
|
|
@ -201,6 +210,41 @@ int board_early_init_f(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
|
||||
int usb_board_init(void)
|
||||
{
|
||||
struct board_bcsr *bcsr_data =
|
||||
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
|
||||
u8 val;
|
||||
|
||||
/* Enable USB host & USB-OTG */
|
||||
val = in_8(&bcsr_data->usb_ctrl);
|
||||
val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
|
||||
out_8(&bcsr_data->usb_ctrl, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_board_stop(void)
|
||||
{
|
||||
struct board_bcsr *bcsr_data =
|
||||
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
|
||||
u8 val;
|
||||
|
||||
/* Disable USB host & USB-OTG */
|
||||
val = in_8(&bcsr_data->usb_ctrl);
|
||||
val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
|
||||
out_8(&bcsr_data->usb_ctrl, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_board_init_fail(void)
|
||||
{
|
||||
return usb_board_stop();
|
||||
}
|
||||
#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
|
||||
|
||||
#if !defined(CONFIG_ARCHES)
|
||||
static void canyonlands_sata_init(int board_type)
|
||||
{
|
||||
|
|
@ -244,11 +288,13 @@ int get_cpu_num(void)
|
|||
#if !defined(CONFIG_ARCHES)
|
||||
int checkboard(void)
|
||||
{
|
||||
struct board_bcsr *bcsr_data =
|
||||
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
|
||||
char *s = getenv("serial#");
|
||||
|
||||
if (pvr_460ex()) {
|
||||
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
|
||||
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
|
||||
if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
|
||||
gd->board_type = BOARD_CANYONLANDS_PCIE;
|
||||
else
|
||||
gd->board_type = BOARD_CANYONLANDS_SATA;
|
||||
|
|
@ -268,7 +314,7 @@ int checkboard(void)
|
|||
break;
|
||||
}
|
||||
|
||||
printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
|
||||
printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
|
||||
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
|
|
|
|||
|
|
@ -27,12 +27,26 @@
|
|||
|
||||
struct ppc4xx_config ppc4xx_config_val[] = {
|
||||
{
|
||||
"600", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
|
||||
"600-67", "CPU: 600 PLB: 200 OPB: 67 EBC: 67",
|
||||
{
|
||||
0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
|
||||
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
|
||||
}
|
||||
},
|
||||
{
|
||||
"600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
|
||||
{
|
||||
0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
|
||||
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
|
||||
}
|
||||
},
|
||||
{
|
||||
"667", "CPU: 667 PLB: 166 OPB: 83 EBC: 83",
|
||||
{
|
||||
0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
|
||||
0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
|
||||
}
|
||||
},
|
||||
{
|
||||
"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
|
||||
{
|
||||
|
|
|
|||
|
|
@ -81,11 +81,13 @@ tlbtab:
|
|||
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
|
||||
|
||||
/* TLB-entry for FPGA(s) */
|
||||
tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4,
|
||||
tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4,
|
||||
tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
|
||||
CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4,
|
||||
tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
|
||||
AC_RW | SA_IG)
|
||||
|
||||
/* TLB-entry for OCM */
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ int board_early_init_f(void)
|
|||
mtdcr(UIC1SR, 0xffffffff); /* clear all */
|
||||
mtdcr(UIC1ER, 0x00000000); /* disable all */
|
||||
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
|
||||
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
|
||||
mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */
|
||||
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
|
||||
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
|
||||
mtdcr(UIC1SR, 0xffffffff); /* clear all */
|
||||
|
|
|
|||
|
|
@ -77,6 +77,13 @@
|
|||
#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
|
||||
#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
|
||||
|
||||
/*
|
||||
* BCSR bits as defined in the Canyonlands board user manual.
|
||||
*/
|
||||
#define BCSR_USBCTRL_OTG_RST 0x32
|
||||
#define BCSR_USBCTRL_HOST_RST 0x01
|
||||
#define BCSR_SELECT_PCIE 0x10
|
||||
|
||||
#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
|
||||
|
||||
/* base address of inbound PCIe window */
|
||||
|
|
@ -417,6 +424,7 @@
|
|||
#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
|
||||
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -202,6 +202,7 @@
|
|||
*/
|
||||
#define CONFIG_CMD_CHIP_CONFIG
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_ECCTEST
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_PCI
|
||||
|
|
|
|||
|
|
@ -74,8 +74,8 @@
|
|||
#define CONFIG_SYS_FLASH_SIZE (64 << 20)
|
||||
|
||||
#define CONFIG_SYS_FPGA1_BASE 0xe0000000
|
||||
#define CONFIG_SYS_FPGA2_BASE 0xe0100000
|
||||
#define CONFIG_SYS_FPGA3_BASE 0xe0200000
|
||||
#define CONFIG_SYS_FPGA2_BASE 0xe2000000
|
||||
#define CONFIG_SYS_FPGA3_BASE 0xe4000000
|
||||
|
||||
#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
|
||||
|
|
@ -84,14 +84,12 @@
|
|||
(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
|
||||
| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
|
||||
|
||||
#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
|
||||
#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */
|
||||
#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
|
||||
#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
|
||||
|
||||
#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */
|
||||
|
||||
#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
|
||||
|
||||
/*
|
||||
* Initial RAM & stack pointer (placed in OCM)
|
||||
*/
|
||||
|
|
@ -121,6 +119,7 @@
|
|||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
|
||||
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||
|
|
@ -144,10 +143,13 @@
|
|||
/*
|
||||
* DDR2 SDRAM
|
||||
*/
|
||||
#define CONFIG_SYS_MBYTES_SDRAM 256
|
||||
#define CONFIG_DDR_ECC
|
||||
#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
|
||||
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
|
||||
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
|
||||
#undef CONFIG_PPC4xx_DDR_METHOD_A
|
||||
#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */
|
||||
|
||||
/* DDR1/2 SDRAM Device Control Register Data Values */
|
||||
/* Memory Queue */
|
||||
|
|
@ -162,9 +164,6 @@
|
|||
#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
|
||||
#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
|
||||
|
||||
#define CONFIG_DDR_ECC
|
||||
#define CONFIG_SYS_MBYTES_SDRAM 256
|
||||
|
||||
#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK
|
||||
|
||||
/* DDR1/2 SDRAM Device Control Register Data Values */
|
||||
|
|
@ -360,6 +359,7 @@
|
|||
* Commands additional to the ones defined in amcc-common.h
|
||||
*/
|
||||
#define CONFIG_CMD_CHIP_CONFIG
|
||||
#define CONFIG_CMD_ECCTEST
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
|
|
@ -417,7 +417,7 @@
|
|||
#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
|
||||
EBC_BXAP_TWT_ENCODE(5) | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(4) | \
|
||||
EBC_BXAP_OEN_ENCODE(3) | \
|
||||
EBC_BXAP_WBN_ENCODE(0) | \
|
||||
EBC_BXAP_WBF_ENCODE(0) | \
|
||||
EBC_BXAP_TH_ENCODE(1) | \
|
||||
|
|
@ -426,7 +426,7 @@
|
|||
EBC_BXAP_BEM_RW | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
|
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BS_32MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_32BIT)
|
||||
|
||||
|
|
@ -434,7 +434,7 @@
|
|||
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
|
||||
EBC_BXAP_TWT_ENCODE(5) | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(4) | \
|
||||
EBC_BXAP_OEN_ENCODE(3) | \
|
||||
EBC_BXAP_WBN_ENCODE(0) | \
|
||||
EBC_BXAP_WBF_ENCODE(0) | \
|
||||
EBC_BXAP_TH_ENCODE(1) | \
|
||||
|
|
@ -443,7 +443,7 @@
|
|||
EBC_BXAP_BEM_RW | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
|
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BS_16MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_32BIT)
|
||||
|
||||
|
|
@ -451,7 +451,7 @@
|
|||
#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \
|
||||
EBC_BXAP_TWT_ENCODE(5) | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(4) | \
|
||||
EBC_BXAP_OEN_ENCODE(3) | \
|
||||
EBC_BXAP_WBN_ENCODE(0) | \
|
||||
EBC_BXAP_WBF_ENCODE(0) | \
|
||||
EBC_BXAP_TH_ENCODE(1) | \
|
||||
|
|
@ -460,7 +460,7 @@
|
|||
EBC_BXAP_BEM_RW | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
|
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BS_16MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_32BIT)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue