Commit graph

4612 commits

Author SHA1 Message Date
Ye Li
76c184fe3a misc: sentinel: s400_api: Add get_events API
Add get_events API to retrieve any singular events that has occurred
since the FW has started from sentinel

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 22:27:38 +02:00
Ye Li
f9288c60f4 imx: sentinel: Update S400 API get info message structure
From Sentinel FW v0.0.9-9df0f503, the response message of get info API
is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
With old structure, we get failure from sentinel due to the buffer
size can't fit with new response message. So update the API structure
to fix the issue.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
cf35290258 imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only
This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting.  So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.

We have to configure necessary PDAC and MSC for SPL before DDR
initialization.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
8b956bdddd imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.

The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.

The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29 20:15:42 +02:00
Ye Li
f3272355cd imx: imx8ulp: Get chip revision from Sentinel
In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29 20:15:41 +02:00
Jagan Teki
f5bc9929a2 arm: rockchip: Add RK3588 arch core support
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76
and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU,
Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2,
LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0,
PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM.

Add arch core support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
d8656cb647 arm: rockchip: Add ioc header for rk3588
Add IOC unit header include for rk3588.

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
b851c006a1 clk: rockchip: pll: Add pll_rk3588 type for rk3588
Add RK3588 pll set and get rate clock support.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
73a21ebf47 arm: rockchip: Add grf header for rk3588
Add GRF header for Rockchip RK3588.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
165d258386 arm: rockchip: Add cru header for rk3588
Add clock and reset unit header include for rk3588.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jonas Karlman
bde73b14f0 rockchip: sdram: add basic support for sdram reg info version 3
Newer DRAM initialization blobs from vendor can encode sdram info in a
new version 3 format. The new format makes use of more bits in sys_reg3
compared to the version 2 format.

Add basic support for detecting the version 3 format and decoding the
high bits used for ddrtype.

This fixes decode of sdram size on my RK3568 boards that have LPDDR4X.

Details on the new format was deciphered from vendor u-boot commit [1].

[1] c69667e0e2

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Svyatoslav Ryhel
bab087802a ARM: tegra: crypto: extend crypto functional
Add support for encryption, decryption and signinig with
non-zero key saving backward compatibility.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
4213d52b33 ARM: tegra: create common pre-dm i2c write
This implementation allows pwr i2c writing on early SPL
stages when DM is not yet setup.

Such writing is needed to configure main voltages of PMIC
on early SPL for bootloader to boot properly.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
1a7ce63c08 ARM: tegra: add late init support
Late init function allows passing values like identifiers and
perform device specific configurations of pre-boot stage.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
a81d792479 ARM: tegra: clock: add clock_decode_pair helper
Get periph clock id and its parent from device tree.
This works by looking up the peripheral's 'clocks' node and
reading out the second and fourth cells, which are the
peripheral and PLL clock numbers.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
65e02744ec ARM: tegra: clock: add clk_id_to_pll_id helper
This function allows to convert a device tree clock ID to PLL ID.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
fca18a2643 tegra30: clock: add EXTPERIPH
This mappings were missing for some reason.

Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Simon Glass
24f95e141e Correct SPL uses of IMX_MODULE_FUSE
This converts 6 usages of this option to the non-SPL form, since there is
no SPL_IMX_MODULE_FUSE defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:39 -05:00
Svyatoslav Ryhel
87a758652b ARM: tegra: remap clock_osc_freq for all Tegra family
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-02 10:16:41 -07:00
Tom Rini
3592a61fa8 For 2023.04
-----------
 
 - several conversion to DM_SERIAL and DM_I2C
 - fixes for Toradex boards
 - PSCI
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
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Merge tag 'u-boot-imx-20230201' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2023.04
-----------

- several conversion to DM_SERIAL and DM_I2C
- fixes for Toradex boards
- PSCI

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
2023-02-01 09:30:52 -05:00
Arnaud Ferraris
a437d14fc8 imx8mq_pins: fix configuration for UART4 on ECSPI2 pads
When routing UART4 using the ECSPI2 pads, register
IOMUXC_UART4_RXD_SELECT_INPUT (offset 0x050C) should be changed only
when dealing with RX, as its name suggests.

Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-31 19:44:23 +01:00
Ye Li
7246ec1934 imx8: scu_api: sync sc_rm_is_pad_owned api change
SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This
requires u-boot to update API implementation, since it will cause
compatible issue. Otherwise all pad checking will have problem and
cause pad setting not continue.

Due to the compatible issue, the new u-boot only works with new
SCFW (API version: 1.21 and later).

old scfw + old u-boot: API overflow issue
old scfw + new u-boot, or new scfw + old u-boot: API compatible issue
new scfw + new u-boot: Working

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Jason Liu <Jason.hui.liu@nxp.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-01-31 19:44:23 +01:00
Tom Rini
095d909cf1 - jethub j100: add rescue boot from microSD
- move meson sm command to cmd/meson and add efusedump sub-command
 - switch dwc2 otg to DM for G12A, GXL & AXG
 - Add new boards:
  - Odroid Go Ultra
  - Odroid-N2L
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Merge tag 'u-boot-amlogic-20230131' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- jethub j100: add rescue boot from microSD
- move meson sm command to cmd/meson and add efusedump sub-command
- switch dwc2 otg to DM for G12A, GXL & AXG
- Add new boards:
 - Odroid Go Ultra
 - Odroid-N2L
2023-01-31 10:15:39 -05:00
Marek Vasut
58552ab81b arm: imx: imx8m: Program CSU and TZASC if PSCI provider
In case U-Boot is the PSCI provider, it is necessary to correctly
program CSU and TZASC registers. Those are poorly documented, so
push in the correct values.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31 15:46:40 +01:00
Marek Vasut
191937134b arm: imx: imx8m: Define trampoline location if PSCI provider
The common code used to bring up secondary cores requires a final
jump location to be stored in some sort of memory location, define
this memory location to be the start of OCRAM, since it is available.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31 15:46:40 +01:00
Marek Vasut
68c0ce8a5c arm: imx: imx8m: Enable GICv3 support if PSCI provider
In case U-Boot is a PSCI provider, enable GICv3 support as this
is necessary to bring up secondary cores.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31 15:46:39 +01:00
Marek Vasut
11a1a3b73d arm: psci: Fix RESET2 hook
The RESET2 hook is a PSCI v1.1 functionality, rename the macro accordinly.
Add missing handler for the RESET2 hook, so it can be implemented by U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31 15:46:39 +01:00
Marek Vasut
46dcb31065 arm: psci: Add PSCI v1.1 macro
Add macro representing the PSCI v1.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31 15:46:39 +01:00
Marek Vasut
3f7afddc9c ARM: imx: bootaux: Fix LTO -Wlto-type-mismatch
Commit 56c2dbdaba ("imx: bootaux: cleanup code") introduces the
following LTO related warning:

"
arch/arm/mach-imx/imx_bootaux.c:24:31: warning: type of ‘hostmap’ does not match original declaration [-Wlto-type-mismatch]
   24 | const __weak struct rproc_att hostmap[] = { };
      |                               ^
arch/arm/mach-imx/imx8m/soc.c:1590:24: note: array types have different bounds
 1590 | const struct rproc_att hostmap[] = {
      |                        ^
arch/arm/mach-imx/imx8m/soc.c:1590:24: note: ‘hostmap’ was previously declared here
../aarch64-linux-gnu/bin/ld: warning: u-boot has a LOAD segment with RWX permissions
"

This is because the weak empty array of structures "hostmap" is eventually
replaced by non-empty array of structures with different number of elements.
Fix this by avoiding weak variable size array, instead use a weak function
which returns single pointer to the array.

Fixes: 56c2dbdaba ("imx: bootaux: cleanup code")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-01-30 23:23:02 +01:00
Jim Liu
337bc26f05 arm: npcm8xx: add security feature header
The NPCM driver can use on npcm7xx/npcm8xx
so add npcm8xx header for driver.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-01-27 12:51:26 -05:00
Tom Rini
6e7df1d151 global: Finish CONFIG -> CFG migration
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-20 12:27:24 -05:00
Jagan Teki
ffb191e458 arm: rockchip: Add RV1126 arch core support
Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.

Add arch core support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I22fde40ec375e3c6aba39808abf252edc45d4b04
2023-01-16 18:01:11 +08:00
Jagan Teki
43cecf7234 arm: rockchip: Add grf header for rv1126
Add GRF header for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
f4ca986e29 arch: rockchip: Add cru header for rv1126
Add clock and reset unit header include for rv1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
e869b3485c ram: rockchip: Add rv1126 ddr driver support
Add DDR driver for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Jagan Teki
5ab30c3176 ram: rockchip: Update ddr pctl regs for px30
Add full ddr pctl registers and bit masks for px30.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Jagan Teki
29c3148974 ram: rockchip: Compute ddr capacity based on grf split
DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.

Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Jim Liu
7ee1c4d1d1 pinctrl: nuvoton: add NPCM7xx/NPCM8xx reset type detect
add reset type detect and persist setting.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-01-10 15:39:06 -05:00
Alexey Romanov
12d7827349 asm/arch-meson: add missing meson_sm_write_efuse signature
This function can be used by other modules. Also add comments.

Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20230110105650.54580-2-avromanov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-10 15:25:48 +01:00
Tom Rini
e95bcfb56c bcmcygnus: Convert CONFIG_IPROC to Kconfig
Select this symbol as needed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
f5dd0c5e19 configs: Remove unused or redundant CONFIG symbols
A number of CONFIG symbols have crept in that are never referenced in
code, so drop them here. Further, we have two symbols being enabled
in headers while already enabled correctly in Kconfig, so these lines
can also be removed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
1d457dbb91 global: Migrate CONFIG_MAX_MEM_MAPPED to CFG
Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
d4e4bc898b global: Migrate CONFIG_KSNET_NETCP_BASE to CFG
Perform a simple rename of CONFIG_KSNET_NETCP_BASE to CFG_KSNET_NETCP_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
f060d1885c global: Migrate CONFIG_KSNET_MAC_ID_BASE to CFG
Perform a simple rename of CONFIG_KSNET_MAC_ID_BASE to CFG_KSNET_MAC_ID_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
21bd204239 global: Migrate CONFIG_KSNET_CPSW_NUM_PORTS to CFG
Perform a simple rename of CONFIG_KSNET_CPSW_NUM_PORTS to CFG_KSNET_CPSW_NUM_PORTS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:49 -05:00
Tom Rini
7b5f75cffa global: Migrate CONFIG_IRAM_BASE to CFG
Perform a simple rename of CONFIG_IRAM_BASE to CFG_IRAM_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
35661f86eb global: Migrate CONFIG_I2C_MVTWSI_BASE1 to CFG
Perform a simple rename of CONFIG_I2C_MVTWSI_BASE1 to CFG_I2C_MVTWSI_BASE1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
45ede979e8 global: Migrate CONFIG_I2C_MVTWSI_BASE0 to CFG
Perform a simple rename of CONFIG_I2C_MVTWSI_BASE0 to CFG_I2C_MVTWSI_BASE0

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
32b7e39db4 Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig
This converts the following to Kconfig:
   CONFIG_STANDALONE_LOAD_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
f55281665a arm: ti814x: Remove remaining support code
When the ti814x_evm config was removed most, but not all, of the
relevant support code was remove.  Get rid of what was missed.

Fixes: 50b5326868 ("ti814x: Remove platform")
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
308520b8f2 global: Remove unused CONFIG symbols
This removes the following unreferenced CONFIG symbols:
   CONFIG_FDTADDR
   CONFIG_FDTFILE
   CONFIG_FLASH_SECTOR_SIZE
   CONFIG_FSL_CPLD
   CONFIG_HDMI_ENCODER_I2C_ADDR
   CONFIG_I2C_MVTWSI
   CONFIG_I2C_RTC_ADDR
   CONFIG_IRAM_END
   CONFIG_IRAM_SIZE
   CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
   CONFIG_L1_INIT_RAM
   CONFIG_MACB_SEARCH_PHY
   CONFIG_MIU_2BIT_21_7_INTERLEAVED
   CONFIG_MTD_NAND_VERIFY_WRITE
   CONFIG_MVGBE_PORTS
   CONFIG_NETDEV
   CONFIG_NUM_DSP_CPUS
   CONFIG_PHY_BASE_ADR
   CONFIG_PHY_INTERFACE_MODE
   CONFIG_PSRAM_SCFG
   CONFIG_RAMBOOT_SPIFLASH
   CONFIG_RAMBOOT_TEXT_BASE
   CONFIG_RD_LVL
   CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
   CONFIG_SETUP_INITRD_TAG
   CONFIG_SH_QSPI_BASE
   CONFIG_SMDK5420
   CONFIG_SOCRATES
   CONFIG_SPI_ADDR
   CONFIG_SPI_FLASH_QUAD
   CONFIG_SPI_FLASH_SIZE
   CONFIG_SPI_HALF_DUPLEX
   CONFIG_SPI_N25Q256A_RESET
   CONFIG_TEGRA_SLINK_CTRLS
   CONFIG_TPM_TIS_BASE_ADDRESS
   CONFIG_UBOOT_SECTOR_COUNT
   CONFIG_UBOOT_SECTOR_START
   CONFIG_VAR_SIZE_SPL
   CONFIG_VERY_BIG_RAM

And also:
   BL1_SIZE
   PHY_NO
   RESERVE_BLOCK_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
3a581af21a Convert CONFIG_FLASH_SPANSION_S29WS_N et al to Kconfig
This converts the following to Kconfig:

   CONFIG_FLASH_SPANSION_S29WS_N
   CONFIG_FLASH_VERIFY
   CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
   CONFIG_FSL_ISBC_KEY_EXT
   CONFIG_FSL_TRUST_ARCH_v1
   CONFIG_FSL_SDHC_V2_3
   CONFIG_MAX_DSP_CPUS
   CONFIG_MIU_2BIT_INTERLEAVED
   CONFIG_SERIAL_BOOT
   CONFIG_SPI_BOOTING
   CONFIG_X86EMU_RAW_IO

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
14f43797d0 Prepare v2023.01-rc4
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Merge tag 'v2023.01-rc4' into next

Prepare v2023.01-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-21 13:09:01 -05:00
Sughosh Ganu
e86c789ca3 rockpi4: board: Add firmware image information for capsule updates
Add information that will be needed for enabling the UEFI capsule
update feature on the RockPi4 boards. With the feature enabled, it
would be possible to update the idbloader and u-boot.itb images on the
RockPi4B and RockPi4C variants.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Tom Rini
2f420f135f net: tsec: Remove non-DM_ETH support code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.  Doing this removes some board support code
which was also unused. Finally, this removes some CONFIG symbols that
otherwise needed to be migrated to Kconfig, but were unused in code now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:16 -05:00
Tom Rini
d5596cbc6e arm: lpc32xx: Remove unused hsuart driver
This driver is not enabled in any config currently, remove it.

Cc: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
c136a86105 Convert CONFIG_IOMUX_SHARE_CONF_REG et al to Kconfig
This converts the following to Kconfig:
   CONFIG_IOMUX_LPSR
   CONFIG_IOMUX_SHARE_CONF_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
65cc0e2a65 global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:08 -05:00
Tom Rini
aa6e94deab global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
ecc8d425fd global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and
CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many
cases they likely should come from the device tree instead. Move these
out of CONFIG namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
3408d96e6c Remove unused symbols
This commit removes the following unused symbols:
   CONFIG_SYS_NVRAM_BASE_ADDR
   CONFIG_SYS_NVRAM_SIZE
   CONFIG_SYS_PAXE_BASE
   CONFIG_SYS_PCCNT
   CONFIG_SYS_PCDAT
   CONFIG_SYS_PCDDR
   CONFIG_SYS_PCI1_ADDR
   CONFIG_SYS_PCI2_ADDR
   CONFIG_SYS_PCI1_IO_BUS
   CONFIG_SYS_PCI1_IO_SIZE
   CONFIG_SYS_PCI1_MEM_BUS
   CONFIG_SYS_PCI1_MEM_SIZE
   CONFIG_SYS_PCIE3_ADDR
   CONFIG_SYS_PCIE4_ADDR
   CONFIG_SYS_PCIE3_IO_PHYS
   CONFIG_SYS_PCIE3_IO_VIRT
   CONFIG_SYS_PCIE4_IO_PHYS
   CONFIG_SYS_PCIE4_IO_VIRT
   CONFIG_SYS_PLL_SETTLING_TIME
   CONFIG_SYS_QMAN_CENA_BASE
   CONFIG_SYS_QMAN_SP_CENA_SIZE
   CONFIG_SYS_RCAR_I2C0_BASE
   CONFIG_SYS_RCAR_I2C1_BASE
   CONFIG_SYS_RCAR_I2C2_BASE
   CONFIG_SYS_RCAR_I2C3_BASE
   CONFIG_SYS_SATA
   CONFIG_SYS_SDRAM_BASE2
   CONFIG_SYS_SGMII_REFCLK_MHZ
   CONFIG_SYS_SGMII_LINERATE_MHZ
   CONFIG_SYS_SGMII_RATESCALE
   CONFIG_SYS_SH_SDHI0_BASE
   CONFIG_SYS_SH_SDHI0_BASE
   CONFIG_SYS_SH_SDHI1_BASE
   CONFIG_SYS_SH_SDHI2_BASE
   CONFIG_SYS_SH_SDHI3_BASE
   CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
   CONFIG_SYS_SPI_U_BOOT_SIZE
   CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
   CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
   CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
   CONFIG_SYS_VCXK_BASE
   CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
   CONFIG_SYS_VCXK_DOUBLEBUFFERED
   CONFIG_SYS_VCXK_ENABLE_DDR
   CONFIG_SYS_VCXK_ENABLE_PIN
   CONFIG_SYS_VCXK_ENABLE_PORT
   CONFIG_SYS_VCXK_INVERT_DDR
   CONFIG_SYS_VCXK_INVERT_PIN
   CONFIG_SYS_VCXK_INVERT_PORT
   CONFIG_SYS_VCXK_REQUEST_DDR
   CONFIG_SYS_VCXK_REQUEST_PIN
   CONFIG_SYS_VCXK_REQUEST_PORT
   CONFIG_SYS_VSC7385_BR_PRELIM
   CONFIG_SYS_VSC7385_OR_PRELIM

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
cdc5ed8f1f global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
91092132ba global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
9591b63531 Convert CONFIG_SYS_NS16550_MEM32 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_NS16550_MIN_FUNCTIONS
   CONFIG_SYS_NS16550_MEM32
   CONFIG_SYS_NS16550_PORT_MAPPED
   CONFIG_SYS_NS16550_REG_SIZE
   CONFIG_SYS_NS16550_SERIAL

To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that
platforms can enable the legacy driver here for SPL.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:07 -05:00
Tom Rini
4e5909450e global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Dylan Hung
8c7b55724c ram: ast2600: Align the RL and WL setting
Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24 16:26:01 -05:00
Tom Rini
c4ee4fe92e For 2022.01
-----------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083
 
 - Fix UART
 - moved to binman (MX8 boards)
 - Toradex: sync DTS with Linux
 - Gateworks: fixes
 - New boards : MSC SM2S iMX8MP
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Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2022.01
-----------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083

- Fix UART
- moved to binman (MX8 boards)
- Toradex: sync DTS with Linux
- Gateworks: fixes
- New boards : MSC SM2S iMX8MP
2022-11-14 09:33:36 -05:00
Tom Rini
6cc04547cb global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Martyn Welch
c92c3a4453 ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP
The i.MX8MP SoC contains 2 more i2c buses. Add support for the
configuration of these buses.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-11-07 22:45:05 +01:00
Martyn Welch
03a7a82970 imx8m: USDHC3 base address definition for i.MX8MP
The i.MX8MP also has USDHC3, allow access to the relvant base address
definition.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-11-07 22:45:05 +01:00
Simon Glass
984639039f Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-31 11:01:31 -04:00
Tom Rini
3eebbd866b Merge tag 'fsl-qoriq-2022-10-18' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Layerscape update
 - support sysreset,
 - de-select FSL_IFC when booting from SD
 - disable unused parts of ICID tables
 - reduce ns_dev size for csu
 - enable dma snooping for ls104x
 - nand driver fixups for ls1043ardb rev 7.0 boards.
2022-10-24 21:28:47 -04:00
Quentin Schulz
d0af506625 rockchip: px30: support debug uart on UART0
UART0 can obviously also be used for debug uart in U-Boot, so let's add
its support.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Sean Anderson
3ed84e73fb arm: layerscape: Disable unused parts of ICID tables
Several parts of the ICID table are only necessary for U-Boot proper.
Disable them in SPL. This saves around 500 bytes.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-10-18 09:32:52 +08:00
Sean Anderson
0c3eec2aea arm64: ls104x: Enable eDMA snooping
This enables eDMA snooping on the LS1043A and LS1046A. This will allow
marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent.
Oddly, this bit is only documented for the LS1043A, and is marked as
"reserved" in the LS1046ARM. I have tested this patch on the LS1046A
and found that marking i2c0 as dma-coherent works without issue.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-10-17 15:17:56 +08:00
Michael Trimarchi
9f46b8637f imx: gpmi: Add register needed to control nand bus timing
It is used as delay for gpmi write strobe.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-09 10:42:26 +02:00
Jim Liu
9ca71c9c19 arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Add basic support for the Nuvoton NPCM845 EVB (Arbel).

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-10-06 21:05:17 -04:00
Tom Rini
01c88e3dcd - Increase SYS_MALLOC_F_LEN for STM32 MCU's board
- SPL fixes for STM32F7 MCUs
 - Device tree alignement with kernelv6.0-rc4 for MCU's board
 - Device tree alignement with kernelv6.0-rc3 for MPU's board
 - Update DDR node for STM32MP15
 - Cleanup config file for STM32MP1
 - Update for cmd_stm32key command
 - Fix compatible string to add partitions for STM32MP1
 - Update for stm32programmer tool
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Merge tag 'u-boot-stm32-20220927' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

- Increase SYS_MALLOC_F_LEN for STM32 MCU's board
- SPL fixes for STM32F7 MCUs
- Device tree alignement with kernelv6.0-rc4 for MCU's board
- Device tree alignement with kernelv6.0-rc3 for MPU's board
- Update DDR node for STM32MP15
- Cleanup config file for STM32MP1
- Update for cmd_stm32key command
- Fix compatible string to add partitions for STM32MP1
- Update for stm32programmer tool
2022-09-27 08:53:51 -04:00
Tom Rini
ffa2c88bcf Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next 2022-09-26 11:27:30 -04:00
Patrice Chotard
3cc471d30a configs: stm32f769-disco: Fix internal flash size
arch-stm32f7/stm32.h file is shared between STM32F746 and STM32F769
MCUs. But STM32F769 embeds 2MB of internal flash instead of 1MB for
STM32F746. The flash layout is quite similar between the 2 SoCs :

	STM32F746 			STM32F769
4 *  32KB sectors 			4 *  32KB sectors
1 * 128KB sector 			1 * 128KB sector
3 * 256KB sectors			7 * 256KB sectors

Update sect_sz_kb[] structure and SYS_MAX_FLASH_SECT accordingly.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26 17:21:02 +02:00
Marek Vasut
fdf6bbb260 ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock
Pull this LPGPR unlock into common code, since it is used in multiple
systems already.

Signed-off-by: Marek Vasut <marex@denx.de>
2022-09-20 18:30:02 +02:00
Tom Rini
e9a1ff9724 Merge branch 'master' into next
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-19 16:07:12 -04:00
Jesse Taube
67e2df581c imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK
This commit adds board support for i.MXRT1170-EVK from NXP. This board
is an evaluation kit provided by NXP for i.MXRT117x processor family.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-18 20:42:56 +02:00
Pali Rohár
5818198e6a arm: mvebu: Fix moving internal registers
Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") moved code from file cpu.c to lowlevel.c,
which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to
SOC_REGS_PHY_BASE.

But the steps describing how to do it correctly were documented only in
older U-Boot versions and commit cefd764222 ("arm: mvebu: Fix internal
register config on A38x") probably unintentionally removed important
details about MMU from code comments around.

Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") implemented code movement according to
(now incomplete) comments which resulted in semi-broken code.

The result is that I-cache is currently disabled for all Armada 38x boards
and maybe there are some other (unreported / undetected) issues.

Reimplement it correctly. First flush all caches, then disable MMU and L2
cache and then move Marvell internal registers. There is no need to
explicitly disable I-cache.

After this change lzmadec command with lzma image of 0x7000000 bytes is
doing decompression just 5 seconds. Before this change it was 30 seconds.

To make lowlevel.S code more readable, extend asm/pl310.h header file to be
compatible with assembler and use macros from this file.

Fixes: 5bb2c550b1 ("arm: mvebu: Move internal registers in arch_very_early_init() function")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13 09:04:22 +02:00
Simon Glass
a55014d09b Makefile: Allow LTO to be disabled for a build
LTO (Link-Time Optimisation) is an very useful feature which can
significantly reduce the size of U-Boot binaries. So far it has been
made available for selected ARM boards and sandbox.

However, incremental builds are much slower when LTO is used. For example,
an incremental build of sandbox takes 2.1 seconds on my machine, but 6.7
seconds with LTO enabled.

Add a NO_LTO parameter to the build, similar to NO_SDL, so it can be
disabled during development if needed, for faster builds.

Add some documentation about LTO while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-02 16:20:11 -04:00
Sergei Antonov
583f1b2f10 arm: ARMv4 assembly compatibility
There is currently a problem that U-Boot can not work on ARMv4
because assembly imlementations of memcpy() and some other functions
use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr"
should be used instead).

A working preprocessor-based solution to this problem is found in
arch/arm/lib/relocate.S. Move it to the "ret" macro in
arch/arm/include/asm/assembler.h and change all "bx lr" code
to "ret lr" in functions that may run on ARMv4. Linux source code
deals with this problem in the same manner.

v1 -> v2:
Comment update. Pointed out by Andre Przywara.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
CC: Samuel Holland <samuel@sholland.org>
CC: Ye Li <ye.li@nxp.com>
CC: Simon Glass <sjg@chromium.org>
CC: Andre Przywara <andre.przywara@arm.com>
CC: Marek Vasut <marex@denx.de>
CC: Sean Anderson <sean.anderson@seco.com>
CC: Tom Rini <trini@konsulko.com>
2022-09-02 13:40:42 -04:00
Tom Rini
9d7add8ac9 net: lpc32xx_eth.c ethernet driver
This driver has not been converted to DM_ETH.  The migration
deadline passed 2 years ago.

Cc: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Ramon Fried <rfried.dev@gmail.com>
2022-08-20 21:18:15 -04:00
Tom Rini
ff4e87c030 Convert CONFIG_SYS_FSL_QMAN_V3 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_NGPIXIS
   CONFIG_SYS_FSL_QMAN_V3
   CONFIG_SYS_FSL_RAID_ENGINE
   CONFIG_SYS_FSL_RMU
   CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
   CONFIG_SYS_FSL_SRIO_LIODN
   CONFIG_SYS_FSL_TBCLK_DIV
   CONFIG_SYS_FSL_USB1_PHY_ENABLE
   CONFIG_SYS_FSL_USB2_PHY_ENABLE
   CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
   CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Tom Rini
1de46d91dd Convert CONFIG_SYS_FSL_NUM_CC_PLLS to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_NUM_CC_PLLS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Tom Rini
c6eec0182a Convert CONFIG_SYS_FSL_MAX_NUM_OF_SEC to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_MAX_NUM_OF_SEC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Tom Rini
8b549c0b23 Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al
This removes the following symbols:
   CONFIG_SYS_FSL_DSPI_BE
   CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
   CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
   CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
   CONFIG_SYS_FSL_DSP_DDR_ADDR
   CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
   CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
   CONFIG_SYS_FSL_ERRATUM_A008751
   CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
   CONFIG_SYS_FSL_ESDHC_NUM
   CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
   CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
   CONFIG_SYS_FSL_ISBC_VER
   CONFIG_SYS_FSL_QSPI_LE
   CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
   CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET
   CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
   CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
   CONFIG_SYS_FSL_SRDS_NUM_PLLS
   CONFIG_SYS_FSL_WDOG_BE
   CONFIG_SYS_GP1DIR
   CONFIG_SYS_GP1ODR
   CONFIG_SYS_GP2DIR
   CONFIG_SYS_GP2ODR
   CONFIG_SYS_HALT_BEFOR_RAM_JUMP
   CONFIG_SYS_HMI_BASE
   FSL_QSPI_FLASH_NUM
   FSL_QSPI_FLASH_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Tom Rini
7da6a9e7df Convert CONFIG_SYS_FSL_CORES_PER_CLUSTER to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_CORES_PER_CLUSTER

As part of this, correct the dependencies on SYS_FSL_THREADS_PER_CORE.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04 16:18:48 -04:00
Tom Rini
612f7a61d5 Convert CONFIG_FSL_MEMAC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_MEMAC
   CONFIG_SYS_MEMAC_LITTLE_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04 16:18:48 -04:00
Tom Rini
923a855509 Convert CONFIG_SYS_FSL_CCSR_GUR_BE et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_CCSR_GUR_BE
   CONFIG_SYS_FSL_CCSR_SCFG_BE
   CONFIG_SYS_FSL_ESDHC_BE
   CONFIG_SYS_FSL_IFC_BE
   CONFIG_SYS_FSL_PEX_LUT_BE
   CONFIG_SYS_FSL_CCSR_GUR_LE
   CONFIG_SYS_FSL_CCSR_SCFG_LE
   CONFIG_SYS_FSL_ESDHC_LE
   CONFIG_SYS_FSL_IFC_LE
   CONFIG_SYS_FSL_PEX_LUT_LE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04 16:18:48 -04:00
Tom Rini
2d752b0d4a Convert CONFIG_SYS_FMAN_V3 to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FMAN_V3

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04 16:18:47 -04:00
Peng Fan
481f96068e board: freescale: imx93_evk: support ethernet
Add ethernet support

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
feaf8e0cf0 imx: imx93_evk: Set ARM clock to 1.7Ghz
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
99c7cc58e1 ddr: imx: Add i.MX9 DDR controller driver
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.

The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
e631185a20 imx: imx9: clock: Add DDR clock support
Implement the DDR driver clock interfaces for set DDR rate and
bypass DDR PLL

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
a8753afed7 imx: imx9: Add M33 release prepare function
To support on-demand booting M33 image from A core. SPL needs
to follow M33 kick up sequence to release M33 firstly,
then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick
M33 to run.

The prepare function also works around the M33 TCM ECC issue by
clean the TCM. Also enable sentinel handshake and WDOG1 clock
for M33 stop and reset.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
0256577a83 imx: imx9: Add MIX power init
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation
of MIPI DSI/CSI, USBPHY after the power up.

SPL should call the power init in its boot sequence before accessing
above three MIX and USB.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
12f2322736 imx: imx9: Add gpio registers structure
Add GPIO registers structure for iMX93, so that we can enable lpgpio
driver

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Alice Guo
31b3ca5527 misc: fuse: support to access fuse on i.MX93
i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables
for i.MX93. The offset address of FSB accessing OTP shadow registers is
different between i.MX8ULP and i.MX93, so use macro to define the offset
address instead of hardcode.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
1a55a633e0 misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
Use more generic name for S40x msg structure

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
989f73934d imx: imx9: Get the chip revision through S400 API
Update the get chip revision methond to use S400 API, also record
other information like lifecycle and UID to global data.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
5fda95fb94 imx: imx9: Add TRDC driver for TRDC init
Add TRDC driver to iMX9. The TRDC init splits to two phases:
1. Early init phase will release TRDC from Sentinel and open write
   permission to the memory where SPL image runs. Sentinel will set
   the memory to RX only after ROM authentication for the OEM
   closed part.
2. Init phase will configure TRDC to allow non-secure master to
   access DDR. So the peripherals can work in u-boot.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
2727245638 misc: s400_api: introduce ahab_release_m33_trout
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel
release M33 trout and make sure M33 could boot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
625473d6ce misc: S400_API: New API for FW status and chip info
Add new API to get sentinel FW status and SoC chip info

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Ye Li
e5fcf91348 misc: S400_API: Update release RDC API
To support more RDC instances on i.MX93, update API to latest
definition.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
45fed324b5 misc: s4mu: Support iMX93 with Sentinel MU
Support iMX93 communicate with Sentinel

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Ye Li
03fcf96651 misc: imx: S400_API: Move S400 MU and API to a common place
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400
MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
636c95f82b imx: imx9: support romapi
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function
prototype common and usable by i.MX9.

Also include mmc env functions that use ROM API.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Ye Li
2c5f5457bc imx: imx9: disable watchdog
Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Jian Li
53cf550d23 imx: imx9: Add function to initialize timer
Add timer_init to update ARM arch timer with correct frequency
from system counter and enable system counter.

Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
f79c162668 imx: imx9: Add CCM and clock API support
Add clock API to support CCM root clock and LPCG setting
Set the CCM AUTHEN register to allow non-secure world to set
root clock and lpcg.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
881df6ed84 imx: add basic i.MX9 support
Add i.MX9 Kconfig and basic files for the new SoC

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
787f04bb6a imx: add USB2_BOOT type
Add USB2_BOOT type for i.MX8ULP and i.MX9

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
b0a284a7c9 imx: move get_boot_device to common file
i.MX8MN/P/ULP supports ROM API, they have almost same get_boot_device
implementation, so move to a common file. And when support i.MX9,
no need to include the other function copy.

Since sys_proto.h is included in imx_romapi.c, there will be build
warning for i.MX8M because wdog_regs not defined, so include imx-regs.h
in i.MX8M sys_proro.h

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
1859b8b60d imx: move get_boot_device to common header
Most i.MX implements get_boot_device, move it to common header to
simplify code

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
793b760fb0 imx: simplify dependency with SPL_BOOTROM_SUPPORT
For SoCs support ROM API, CONFIG_SPL_BOOTROM_SUPPORT is needed,
so use this macro to guard the code to avoid extend the list.

And drop the guard with structure definition, there is no need.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Mamta Shukla
1c3a8e7753 configs: imx8mm: Define CONFIG_SYS_UBOOT_BASE for i.MX8m
The macro `CONFIG_SYS_UBOOT_BASE` is used by SPL loaders `"NOR"` and
`"XIP"` to determine the base address of u-boot.

For `"NOR"` on i.MX8MM it is the base address of QSPI0 plus the offset
of the flattened image tree blob.
Although `QSPI0_AMBA_BASE` is used to define CONFIG_SYS_UBOOT_BASE in
multiple board header files for i.MX8MM, it is not specified.

Specify offset of flattened image tree blob (needs to be set to same
value as specified in 'binman' node), base address of QSPI0 and size of
FlexSPI configuration block.

Signed-off-by: Mamta Shukla <mamta.shukla@leica-geosystems.com>
Signed-off-by: Thomas Haemmerle <thomas.haemmerle@leica-geosystems.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Andrey Zhizhikin  <andrey.zhizhikin@leica-geosystems.com>
2022-07-25 15:35:35 +02:00
Rasmus Villemoes
748da8abb0 imx8: add rom api wrappers
The ROM API is thoroughly undocumented, but apparently passing the xor
of the real arguments as an extra argument is required [1]. Also, we
need to do the "save gd/restore gd" dance. These are both error-prone,
and lead to a lot of code duplication.

Since both imx8m[np] and imx8ulp SOCs have this, add a separate
translation unit which is included precisely when the new
CONFIG_IMX8_ROMAPI symbol is set, which provide convenience wrappers
that take care of computing the xor value as well as doing the gd
dance, and that thus have a more intuitive API. Subsequent patches
will make use of these to reduce boilerplate.

[1] One wonders, for example, if the check is only applied to the
lower 32 bits, or if we're implicitly relying on all 64-bit pointer
values we're passing effectively have 0 in the upper 32 bits.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-25 15:35:34 +02:00
Rasmus Villemoes
de20c5d405 imx8: sys_proto.h: change guard logic around ROM API
This exposes the struct rom_api, the g_rom_api variable declaration
and the associated #defines to slightly fewer boards: namely, those
IMX8M which are not IMX8MN or IMX8MP. But the latter two are the only
IMX8M* ones where the g_rom_api variable is defined (in imx8m/soc.c),
so that should be fine.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-25 15:35:34 +02:00
Tom Rini
36b661dc91 Merge branch 'next' 2022-07-11 14:58:57 -04:00
Tom Rini
95cc3efcc1 arm: Remove strongarm support
There are no platforms using this architecture anymore, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-08 17:57:33 -04:00
Tom Rini
bb20a105e9 Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_BOOT_RAMDISK_HIGH

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 14:01:09 -04:00
Tom Rini
a457ebd786 arm: Remove PXA architecture support
With the last platform for this architecture removed, remove the rest of
the architecture support as well.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-07 09:29:08 -04:00
Tom Rini
f1c6dfa426 layerscape: Remove some unused CONFIG symbols
All of these symbols are not referenced anywhere else in the code, so
remove them.

Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
cd6a45a41f Convert CONFIG_USB_OHCI_NEW et al to Kconfig
This converts the following to Kconfig:
    CONFIG_SYS_OHCI_SWAP_REG_ACCESS
    CONFIG_SYS_USB_OHCI_CPU_INIT
    CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
    CONFIG_SYS_USB_OHCI_SLOT_NAME
    CONFIG_USB_ATMEL
    CONFIG_USB_ATMEL_CLK_SEL_PLLB
    CONFIG_USB_ATMEL_CLK_SEL_UPLL
    CONFIG_USB_OHCI_LPC32XX
    CONFIG_USB_OHCI_NEW

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
52aaa1840d nxp: config_fsl_chain_trust.h: Clean up and remove unused portions
The way that secure boot is implemented today on NXP ARM platforms does
not reuse the elements found in include/config_fsl_chain_trust.h to
construct CONFIG_SECBOOT but instead board header files have their
environment setup as needed and then fsl_setenv_chain_of_trust() will
set secureboot in the environment.  Remove a large number of unused
defines here.

Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:01 -04:00
Tom Rini
5aad0a14ba fsl_validate: Migrate SPL_UBOOT_KEY_HASH to Kconfig
Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig.  As
part of this, change fsl_secboot_validate(...) to check that it is
passed a non-empty string, rather than non-NULL.

Cc: Peng Fan <peng.fan@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:01 -04:00
Tom Rini
601483ffd5 Convert CONFIG_SYS_FSL_SFP_BE et al to Kconfig
This converts the following to Kconfig:
   CONFIG_KEY_REVOCATION
   CONFIG_SYS_FSL_SFP_BE
   CONFIG_SYS_FSL_SFP_LE
   CONFIG_SYS_FSL_SFP_VER_3_0
   CONFIG_SYS_FSL_SFP_VER_3_2
   CONFIG_SYS_FSL_SFP_VER_3_4
   CONFIG_SYS_FSL_SRK_LE

This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for
when CHAIN_OF_TRUST is enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:00 -04:00
Tom Rini
c9f85187e2 Convert CONFIG_SYS_FSL_SEC_MON et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_SEC_MON
   CONFIG_SYS_FSL_SEC_MON_BE
   CONFIG_SYS_FSL_SEC_MON_LE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:00 -04:00
Tom Rini
2b2817b5c8 Convert CONFIG_ESBC_HDR_LS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_ESBC_HDR_LS
   CONFIG_ESBC_ADDR_64BIT

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:02 -04:00
Tom Rini
3371eddaa1 Convert CONFIG_USB_MAX_CONTROLLER_COUNT to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_MAX_CONTROLLER_COUNT

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:11:48 -04:00
Tom Rini
24ec3dea4b arm: samsung: Migrate a number of symbols to Kconfig
- In a number of cases, use CONFIG_ARCH_EXYNOS[45] rather than
  CONFIG_EXYNOS[45]
- In other cases, test for CONFIG_ARCH_EXYNOS or CONFIG_ARCH_S5PC1XX
- Migrate specific SoC CONFIG values to Kconfig
- Use CONFIG_TARGET_x rather than CONFIG_x
- Migrate other CONFIG_EXYNOS_x symbols to Kconfig
- Reference CONFIG_EXYNOS_RELOCATE_CODE_BASE directly as EXYNOS_RELOCATE_CODE_BASE
- Rename CONFIG_S5P_PA_SYSRAM to CONFIG_SMP_PEN_ADDR to match the rest
  of U-Boot usage.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:04:37 -04:00
Tom Rini
093044735f usb: ehci-fsl: Remove non-DM code
The deadline for DM_USB migration has passed and all users have been
migrated.  Remove now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Janne Grunau
e44d59c6ad arm: apple: nvme: Add SART support and RTKit buffer management
The NVMe firmware in the macOS 13 beta blocks or crashes with u-boot's
current minimal RTKit implementation. It does not provide buffers for
the firmware's buffer requests. The ANS2 firmware included in macOS 11
and 12 tolerates this. The firmware included in the first macOS 13 beta
requires buffers for the crashlog and ioreport endpoints to function.

In the case of the NVMe the buffers are physical memory. Access to
physical memory is guarded by what Apple calls SART.
Import m1n1's SART driver (exclusively used for the NVMe controller).
Implement buffer management helpers for RTKit. These are generic since
other devices (none in u-boot so far) require different handling.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-23 08:24:49 -04:00
Jim Liu
0ae1c77199 misc: nuvoton: Add NPCM7xx otp controller driver
Add Nuvoton BMC npcm750 otp driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22 21:30:05 -04:00
Jim Liu
9e03b48dfa crypto: nuvoton: Add NPCM7xx AES driver
add nuvoton BMC npcm750 AES driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22 21:30:05 -04:00
Chia-Wei Wang
12770d0df0 ast2600: spl: Add boot mode detection
AST2600 supports boot from SPI(mmap), eMMC, and UART.
This patch adds the boot mode detection and return the
corresponding boot device type.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-06-22 21:30:05 -04:00
Tom Rini
52af0101be Merge branch 'master' into next
Merge in v2022.07-rc5.
2022-06-20 14:40:59 -04:00
Michael Walle
2a9cf320af armv8: layerscape: add missing RCW source defines
A board might need to get the source of the RCW word, which is also the
boot source in most cases.

These defines are taken from the LS1028A and I expect they are the same
across the SoCs with the same chassis, after all, there was already a
reset source for NOR flash.

Signed-off-by: Michael Walle <michael@walle.cc>
2022-06-20 15:52:45 +08:00
Andre Przywara
ce9c579e2b armv8: always use current exception level for TCR_ELx access
Currently get_tcr() takes an "el" parameter, to select the proper
version of the TCR_ELx system register.
This is problematic in case of the Apple M1, since it runs with
HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout,
and we get the wrong version.

For U-Boot's purposes the only sensible choice here is the current
exception level, and indeed most callers treat it like that, so let's
remove that parameter and read the current EL inside the function.
This allows us to check for the E2H bit, and pretend it's EL1 in this
case.

There are two callers which don't care about the EL, and they pass 0,
which looks wrong, but is irrelevant in these two cases, since we don't
use the return value there. So the change cannot affect those two.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-16 15:22:55 -04:00
Tom Rini
3135ba642f arm: pxa: Remove CONFIG_CPU_PXA25X
There are no platforms that set this, remove the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:12 -04:00
Tom Rini
6074a536d5 ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage
A number of PowerPC platforms define this, for SPL.  To move this to
Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use
CONFIG_IS_ENABLED() to check for usage.  A number of layerscape
platforms bring this logic from PowerPC, but only need a small part of
it, for the fman driver.  Remove their unused portion at least.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:12 -04:00
Tom Rini
12f613cf0e arm: omap2plus: Move CONFIG_SYS_PTV out of CONFIG namespace
This is always defined to 2, and referenced in two places.  Move the
define to <asm/omap_common.h> and make sure the code that uses this
includes that file.  Make <asm/arch-omap*/clock.h> not include that
file, as we don't need to be doing so.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:00 -04:00
Andre Przywara
2b641211c5 armv8: Fix TCR 64-bit writes
The AArch64 TCR_ELx register is a 64-bit register, and many newer
architecture features use bits in the upper half. So far U-Boot was
igorant of those bits, trying to leave them alone.
However, in an effort to set bit 31 to 1, it failed doing so, because
the compiler sign-extended "1 << 31", so that all bits[63:31] got set.

Older ARMv8.0 cores don't define anything dangerous up there, but newer
architecture revisions do, and setting all those bits will end badly:
=================
$ qemu-system-aarch64 -cpu max ....
U-Boot 2022.07-rc1 (May 09 2022 - 15:21:00 +0100)

DRAM:  1.5 GiB
=================  (hangs here)

Defining TCR_ELx_RSVD to "1U << 31" avoids the sign-extension, so all
upper bits stay at a safe 0 value. This means no more surprises when
U-Boot runs on a more capable CPU core.

Reported-by: Balaji Anandapadmanaban <Balaji.Anandapadmanaban@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Peter Collingbourne <pcc@google.com>
2022-06-03 11:15:24 -04:00
Gaurav Jain
cad77280c3 i.MX8ULP: add display_ele_fw_version api
implement get f/w version api.
print ele f/w version in spl.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
2022-05-20 12:36:47 +02:00
Rasmus Villemoes
290ffe5788 imx8m: fix reading of DDR4 MR registers
I was trying to employ lpddr4_mr_read() to something similar to what
the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM
type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c
differs from the private one used by that board in how it extracts the
byte value, and I was only getting zeroes. Adding a bit of debug
printf'ing gives me

 tmp = 0x00ffff00
 tmp = 0x00070700
 tmp = 0x00000000
 tmp = 0x00101000

and indeed I was expecting a (combined) value of 0xff070010 (0xff
being Manufacturer ID for Micron). I can't find any documentation that
says how the values are supposed to be read, but clearly the iot-gate
definition is the right one, both for its use case as well as my
imx8mp-based board.

So lift the private definition of lpddr4_mr_read() from the
imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration
in the ddr.h header where e.g. get_trained_CDD() is already declared.

This has only been compile-tested for the imx8mm-cl-iot-gate
board (since I don't have the hardware), but since I've merely moved
its definition of lpddr4_mr_read(), I'd be surprised if it changed
anything for that board.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:28 +02:00