Pantelis Antoniou stated:
AFAIK, it is still used but the products using PPC are long gone.
Nuke it plz (from orbit).
So remove it since it cleans up a usage of env_get_char outside of
the environment code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds Lime GDC support together with support for the PWM
backlight control through the w83782d chip. The reset pin of the
latter is attached to GPIO, so we need to reset it in
early_board_init_r.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
- Update the local bus ranges in the FDT for Linux for the various
devices connected to the local bus via chip-select.
- Set the LCRR_DBYP bit in the LCRR for local bus frequencies
lower than 66 MHz and uses I/O accessor functions consequently.
- UPM data update.
- Update of default environment and configuration. Use I2C multibus
as we do have two I2C buses. Also enable sdram and ext2 commands.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID
format, and so it obsoletes board/freescale/common/cds_eeprom.c. Freescale
86xx boards already use sys_eeprom.c, so this patch migrates the remaining
Freescale 85xx boards to use it as well. cds_eeprom.c is deleted.
Signed-off-by: Timur Tabi <timur@freescale.com>
This patch add FDT support and command line editing capabilities
for CPCI405 and CPCI405AB boards.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.
Signed-off-by: Stefan Roese <sr@denx.de>
Some of multi-function USB controllers (e.g. ISP1562) allow root hub
resetting only via EHCI registers. So, this patch adds the
corresponding kind of reset to OHCI's hc_reset() if the newly
introduced CONFIG_PCI_EHCI_DEVNO option is set (e.g. for Socrates
board).
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Acked-by: Markus Klotzbuecher <mk@denx.de>
This patch provides an unificated way of handling xilinx v5 ppc440 boards.
It unificates 3 different things:
1) Source code
A new board called ppc440-generic has been created. This board includes
a generic tlb initialization (Maps the whole memory into virtual) and
defines board_pre_init, checkboard, initdram and get_sys_info weakly,
so, they can be replaced by specific functions.
If a new board needs to redefine any of the previous functions
(specific initialization) it can create a new directory with the
specific initializations needed. (see the example ml507 board).
2) Configuration file
Common configurations are located under configs/xilinx-ppc440.h, this
header file interpretes the xparameters file generated by EDK and
configurates u-boot in correspondence. Example: if there is a Temac,
allows CMD_CONFIG_NET
Specific configuration are located under specific configuration file.
(see the example ml507 board)
3) Makefile
Some work has been done in order to not duplicate work in the Main
Makefile. Please see the attached code.
In order to support new boards they can be implemented in the next way:
a) Simple Generic Board (90% of the time)
Using EDK generates a new xparameters.h file, replace
ppc440-generic/xparameters.h and run make xilinx-ppc440-generic_config
&& make
b) Simple Boards with special u-boot parameters (9 % of the time)
Create a new file under configs for it (use ml507.h as example) and
change your paramaters. Create a new Makefile paragraph and compile
c) Complex boards (1% of the time)
Create a new folder for the board, like the ml507
Finally, it adds support for the Avnet FX30T Evaluation board, following
the new generic structure:
Cheap board by Avnet for evaluating the Virtex5 FX technology.
This patch adds support for:
- UartLite
- 16MB Flash
- 64MB RAM
Prior using U-boot in this board, read carefully the ERRATA by Avnet
to solve some memory initialization issues.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables the PCI-OHCI controller on PLU405 board.
Also the default CPU frequency is updated to 266 MHz and
command line editing is enabled.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The 8544DS and 8572DS platforms support an optional SGMII riser card to
expose ethernet over an SGMII interface. Once the card is in, it is also
necessary to configure the board such that it uses the card, rather than
the on-board ethernet ports. This can either be done by flipping dip switches
on the motherboard, or by modifying registers in the pixis. Either way
requires a reboot.
This adds a command to allow users to choose which ports are routed through
the SGMII card, and which through the onboard ports. It also allows users
to revert to the current switch settings.
This code does not work on the 8572, as the PIXIS is different.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The 8544DS and 8572DS systems have an optional SGMII riser card which
exposes new ethernet ports which are connected to the eTSECs via an
SGMII interface. The SGMII PHYs for this board are offset from the standard
PHY addresses, so this code modifies the passed in tsec_info structure to
use the SGMII PHYs on the card, instead.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This boards used old type preprocessor.
This patch fix compile error.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This boards used old type preprocessor.
This patch fix compile error.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
AP325RXA is SH7723's reference board.
This has SCIF, NOR Flash, Ethernet, USB host, LCDC, SD Host, Camera and other.
In this patch, support SCIF, NOR Flash, and Ethernet.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds initial support for the RTE RSK+ SH7203 board.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This board has SH7785, 512MB DDR2-SDRAM, NOR Flash,
Graphic, Ethernet, USB, SD, RTC, and I2C controller.
This patch supports the following functions:
- 128MB DDR2-SDRAM (29-bit address mode only)
- NOR Flash
- USB host
- Ethernet
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl
driver for it too. The board can also boot from the NOR flash, but due to
hardware limitations it can only address 64KiB on it, which is not enough
for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
This is needed since now with HUSH enabled (amcc-common.h) the image
read from NAND exceeds the previous limit.
Signed-off-by: Stefan Roese <sr@denx.de>
MPC5121 rev 2 silicon has a new register for controlling how long
CS is asserted after deassertion of ALE in multiplexed mode.
The default is to assert CS together with ALE. The alternative
is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.
The default is wrong for the NOR flash and CPLD on the ADS5121.
This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
it does so conditionally based on silicon rev 2.0 or greater.
Signed-off-by: Martha J Marx <mmarx@silicontkx.com>
Signed-off-by: John Rigby <jrigby@freescale.com>
Add FEC pin set and mii reset in __mii_init(). Change
legacy flash vendor from 2 to AMD LEGACY (0xFFF0),
change cfi_offset to 0, and change CFG_FLASH_CFI to
CONFIG_FLASH_CFI_LEGACY. Correct M54451EVB and
M54455EVB env settings in configuration file.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
fix mvBL-M7 config and move to matrix_vision subdir
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Add the ability for the MPC8349EMDS to run in PCI Agent mode, acting as a
PCI card rather than a host computer.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Change the MPC8349EMDS board to use the generic PCI initialization code
for the mpc83xx cpu.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The MIMC200 board is based on Atmel's NGW100 dev kit, but with an extra
8MByte FLASH and 128KByte FRAM.
Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Incorrect CFG_HZ value, change 1000000 to 1000.
Rename #waring to #warning. RAMBAR1 uses twice
in start.S, rename the later to FLASHBAR. Insert
nop for DRAM setup. And, env_offset in linker file.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Remove non-common flash driver in
board/freescale/m54455evb/flash.c. The non-cfi flash will
use CONFIG_FLASH_CFI_LEGACY to configure the flash
attribute.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Note that with older board revisions, NAND boot may only work after a
power-on reset, and not after a warm reset. I don't have a newer board
to test on; if you have a board with a 33MHz crystal, please let me know
if it works after a warm reset.
Signed-off-by: Scott Wood <scottwood@freescale.com>
When switching the TQM8xxL modules to use the CFI flash driver,
support for the second flash bank was broken because the CFI driver
did not support dynamically sized banks. This gets fixed now.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The Sequoia board has two UARTs in "4-pin" mode. This patch modifies the GPIO
configuration to match the schematic, and also sets the SDR0_PFC1 register to
select the corresponding mode for the UARTs.
Signed-off-by: Steven A. Falco <sfalco@harris.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for the Favr-32 board made by EarthLCD.
This kit, which is also called ezLCD-101 when running with EarthLCD firmware,
has a 10.4" touch screen LCD panel, 16 MB 32-bit SDRAM, 8 MB parallel flash,
Ethernet, audio out, USB device, SD-card slot, USART and various other
connectors for cennecting stuff to SPI, I2C, GPIO, etc.
Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
On ADS5121 when booting linux the following errors are seen:
Unable to update property /soc5121@80000000:bus-frequency, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:local-mac-address, err=FDT_ERR_NOTFOUND
Unable to update property /soc5121@80000000/ethernet@2800:address, err=FDT_ERR_NOTFOUND
This is caused by ft_cpu_setup trying to deal with
both old and new soc node naming. This patch
fixes this by being smarter about what to
fixup.
Also do soc node fixups by compatible instead of by path.
A new board config called OF_SOC_COMPAT defined
to be "fsl,mpc5121-immr" replaces the old
OF_SOC node path that was defined to be "soc@80000000".
Old device trees still work, but the compatiblity
is conditional on CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
which is on by default in include/configs/ads5121.h.
Signed-off-by: John Rigby <jrigby@freescale.com>
U-Boot allows for configurable prompt strings using the
CONFIG_AUTOBOOT_PROMPT resp. CONFIG_MENUPROMPT definitions. So far,
the assumption was that any such user defined problts would contain
exactly one "%d" format specifier. But some boards did not.
To allow for flexible boot prompts without adding too complex code we
now allow to specify the whole list of printf() arguments in the user
definition. This is powerful, but requires a responsible user who
really understands what he is doing, as he needs to know for exanple
which variables are available in the respective context.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Tried fixing NAND support for the at91rm9200dk board; untested.
Disabled NAND support in the csb637 board config file.
Signed-off-by: Wolfgang Denk <wd@denx.de>
- Relocate the location of U-Boot in the flash
- Save the environment in one sector of the flash memory
- MTD Support
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch allows booting from FLASH the ML507 board by Xilinx.
Previously, U-Boot needed to be loaded from JTAG or a Sytem ACE CF
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel. It offers versatile peripherals, such as ethernet, usb
device, usb host etc.
The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).
Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.
For more information see: http:///www.miromico.com/hammerhead
Signed-off-by: Julien May <mailinglist@miromico.ch>
[haavard.skinnemoen@atmel.com: various small fixes and adaptions]
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Due to increased space usage, U-Boot can no longer be stored in three sectors.
The current U-Boot use just over three flash sectors (197k), and U-Boot will
become corrupt after saving environment variables. This patch adds another 64k
to CFG_MONITOR_LEN.
Signed-off-by: Frank E. Svendsbøe <frank.svendsboe@gmail.com>
Support for the adsvix was originally provided by Applied Data
Systems (ADS), inc., now EuroTech, Inc.
The board never shipped aside from some sample boards.
Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
The Xilinx ML507 Board is a Virtex 5 prototyping board that includes,
among others:
-Virtex 5 FX FPGA (With a ppc440x5 in it)
-256MB of SDRAM2
-32MB of Flash
-I2C Eeprom
-System ACE chip
-Serial ATA connectors
-RS232 Level Conversors
-Ethernet Transceiver
This patch gives support to a standard design produced by EDK for this
board: ppc440, uartlite, xilinx_int and flash
- Includes Changes propossed by Stefan Roese and Michal Simek
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: Stefan Roese <sr@denx.de>
Freescale ships MPC8315E-RDB boards either with TSEC1 and USB UTMI
support, or without TSEC1 but with USB ULPI PHY support in addition.
With this patch user can specify desired USB PHY.
Also, it seems that we can't distinguish the two boards in software, so
user have to set `mpc8315erdb' environment variable to either 'tsec1'
(TSEC1 enabled) or `ulpi' (board with ULPI PHY, TSEC1 disabled), so that
Linux will not probe for TSEC1.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Update the sys_eeprom.c file to handle both NXID and CCID EEPROM formats. The
NXID format replaces the older CCID format, but it's important to support both
since most boards out there still use the CCID format. This change is in
preparation for using one file to handle both formats. This will also unify
EEPROM support for all Freescale 85xx and 86xx boards.
Also update the 86xx board header files to use the standard CFG_I2C_EEPROM_ADDR
instead of ID_EEPROM_ADDR.
Signed-off-by: Timur Tabi <timur@freescale.com>
The L2_INIT_RAM option was unused, and recent changes to the TLB code
meant that the INIT_RAM TLBs weren't being cleared out. In order to reduce
the amount of mapped space attached to nothing, we change things so the TLBs
get cleared.
Signed-off-by: Andy Fleming <afleming@freescale.com>
The fake flash bank was generating errors for anyone who didn't have a
PromJET hooked up to the board. As that constitutes the vast majority of
users, we remove it.
Signed-off-by: Andy Fleming <afleming@freescale.com>
This was proposed by Paul Gortmaker in response to Wolfgang's comments on
similar #defines in sbc8560.h.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add in the default fdt settings and the typical EXTRA_ENV
settings as borrowed from the mpc8560ads. Fix a couple
of stale references to the mpc8560ads dating back to the
original clone/fork.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The existing config doesn't define CONFIG_HAS_ETH0, and so the
fdt support doesn't update the zeros in the dtb local-mac with
real data from the u-boot env. Since the existing config is
tailored to just two interfaces, get rid of the ETH2 definitions
at the same time.
Also don't include any end user specific data into the environment
by default -- things like MAC address, network parameters etc. need
to come from the end user.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The definitions for the TSEC have become out of date. There is no
longer any such options like "CONFIG_MPC85xx_TSEC1" or similar.
Update to match those of other boards, like the MPC8560ADS.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch cleans up the 440SPe PCIe register usage. Now only defines
from the include/asm-ppc/4xx_pcie.h are used.
Signed-off-by: Stefan Roese <sr@denx.de>
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.
Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.
Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for placing the RGMII bridge on the
PPC405EX(r) into MII/GMII mode and allows a board-specific
configuration to specify the bridge mode at compile-time.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
controller registers (MODT and INITPLR) used by the
PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
peer values used for the INITPLR MR and EMR registers,
respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).
With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
Kilauea are replaced by equivalent mnemonics to make it easier to
compare and contrast other 405EX(r)-based boards (e.g. during board
bring-up).
Finally, unified the SDRAM controller register dump routine such that
it can be used across all processor variants that utilize the IBM DDR2
SDRAM controller core. It produces output of the form:
PPC4xx IBM DDR2 Register Dump:
...
SDRAM_MB0CF[40] = 0x00006701
...
which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
since it is not uncommon that the DCR values in header files get mixed
up and it helps to validate, at a glance, they match what is printed
in the user manual.
Tested on:
AMCC Kilauea/Haleakala:
- NFS Linux Boot: PASSED
- NAND Linux Boot: PASSED
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
ADS5121 Rev 3 board is now the default config
config targets are now
ads5121_config
Rev 3 board with
PCI
M41T62 on board RTC
512MB DRAM
ads5121_rev2_config
Rev 2 board with
No PCI
256MB DRAM
Signed-off-by: Martha Marx <mmarx@silicontkx.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: John Rigby <jrigby@freescale.com>
Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
To support such configurations, we "only" map the first 2GB via the TLB's. We
need some free virtual address space for the remaining peripherals like, SoC
devices, FLASH etc.
Note that ECC is currently not supported on configurations with more than 2GB
SDRAM. This is because we only map the first 2GB on such systems, and therefore
the ECC parity byte of the remaining area can't be written.
Signed-off-by: Stefan Roese <sr@denx.de>
ARM: Fix for incorrect version of patch applied when
adding support for the Lyrtech SFF-SDR board.
Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Signed-off-by: Philip Balister, OpenSDR <philip@opensdr.com>
After we move the atmel_mci driver into drivers/mmc, we can't select
it with CONFIG_MMC anymore. Introduce a new symbol specifically for
this driver so that there's no ambiguity.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Acked-by: Jean-Chritophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
The watchdog on 8610 board is enabled by setting sw[6]
to on. Once enabled, the watchdog can not be disabled
by software. So feed the dog in u-boot is necessary for
normal operation.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
New NOR Flash board support and remove old type flash board config.
And Remove network setting from config file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
New NOR Flash board support and remove network setting from config file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This change helps with better handling with others
Xilinx based platform.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stefan Roese <sr@denx.de>
update mvBL-M7 config file to use UBOOT_VERSION.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch adds support for the Lyrtech SFF-SDR board,
based on the TI DaVinci architecture (ARM926EJS).
Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Signed-off-by: Philip Balister <philip@balister.org>
Signed-off-by: Wolfgang Denk <wd@denx.de>
The ATNGW100 has 8MB DataFlash on board. Give users access to it through
the new SPI flash framework.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Make it so we keep track of which LAWs have allocated and provide
a function (set_next_law) which can allocate a LAW for us if one is
free.
In the future we will move to doing more "dynamic" LAW allocation
since the majority of users dont really care about what LAW number
they are at.
Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
A number of board ports have empty version of board_early_init_f
for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove unused and unconfigured DDR test code from FSL 85xx boards.
Besides, other common code exists.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash
memory. The current memory map only supports up to 128 MiB Flash.
This patch adds the configuration option CONFIG_TQM_BIGFLASH. If
set, up to 1 GiB flash is supported. To achieve this, the memory
map has to be adjusted in great parts (for example the CCSRBAR is
moved from 0xE0000000 to 0xA0000000).
If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new
memory map also has to be considered in the kernel (changed
CCSRBAR address, changed PCI IO base address, ...). Please use
an appropriate Flat Device Tree blob (tqm8548.dtb).
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds support for NAND FLASH on the TQM8548. It is disabled by
default and can be enabled for the TQM8548 modules. It is now based on
the re-written FSL NAND UPM driver. A patch has been posted earlier today
with the subject:
"NAND FSL UPM: driver re-write using the hwcontrol callback"
Note that the R/B pin is not supported by that module requiring to use
the specified maximum delay time.
Note: With NAND support enabled the size of the U-Boot image exceeds
256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk,
doubling the image size :-(.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds support for PCI express cards. The board support
now uses common FSL PCI init code, for both, PCI and PCIe on all
TQM85xx modules.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds basic support for the TQM8548 module from TQ-Components
(http://www.tqc.de/) including DDR2 SDRAM initialisation and support for
eTSEC 3 and 4
Furthermore Flash buffer write has been enabled to speed up output to
the Flash by approx. a factor of 10.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds support for Linux kernels using the Flat Device Tree.
It also re-defines the default environment settings for booting Linux
with the FDT blob.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds initialization of the UPMC RAM to support up to two
Intel 82527 compatible CAN controller on the TQM85xx modules.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
The 'N' type Spansion flashes (S29GLxxxN series) have bigger sectors,
than the formerly used 'M' types (S29GLxxxM series), so the flash layout
needs to be changed -> new start address of the environment. The macro
definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be
defined for boards with 'N' type flashes.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names
from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Add MPC8343 based board mvBlueLYNX-M7.
It's a single board stereo camera system.
Please read doc/README.mvblm7 for details.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
move the BRx_* and ORx_* left behind in mpc85xx.h
The same is needed for mpc8xx.h and mpc8260.h (defines are almost
the same, just few differences which needs some attention though).
But the bad news for mpc8xx and mpc8260 is that there are a lot of users
of these defines. So this cleanup I'll leave for the "better times".
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Use CONFIG_OF_LIBFDT instead to support flattened device trees. It is
cleaner, has better functionality, and is better supported.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change
to CONFIG_OF_LIBFDT.
WARNING: It appears that this board lost its ability to boot via a
flattened device tree prior to this changeset.
WARNING: This conversion was untested because I do not have a board to
test it on.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change
to CONFIG_OF_LIBFDT.
WARNING: This conversion is untested because I do not have a board to
test it on.
NOTE: The FDT blob (DTS) must have an /aliases/ethernet0 and (optionally)
/aliases/ethernet1 property for the ethernet to work.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
SH7763RDP has SCIF, NOR Flash, Ethernet, USB host, LCDC and MMC.
In this patch, support SCIF, NOR Flash, and Ethernet.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CONFIG_SOC_AU1X00
Common Alchemy Au1x00 stuff. All Alchemy processor based machines
need to have this config as a system type specifier.
CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200,
CONFIG_SOC_AU1500, CONFIG_SOC_AU1550
Machine type specifiers. Each port should have one of aboves.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This patch series unifies the AMCC eval board ports by introducing
a common include header for all AMCC eval boards:
include/configs/amcc-common.h
This header now includes all common configuration options/defines which
are removed from the board specific headers.
The reason for this is ease of maintenance and unified look and feel
of all AMCC boards.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch series unifies the AMCC eval board ports by introducing
a common include header for all AMCC eval boards:
include/configs/amcc-common.h
This header now includes all common configuration options/defines which
are removed from the board specific headers.
The reason for this is ease of maintenance and unified look and feel
of all AMCC boards.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch series unifies the AMCC eval board ports by introducing
a common include header for all AMCC eval boards:
include/configs/amcc-common.h
This header now includes all common configuration options/defines which
are removed from the board specific headers.
The reason for this is ease of maintenance and unified look and feel
of all AMCC boards.
Signed-off-by: Stefan Roese <sr@denx.de>
MIPS port has two problems in timer routines. One is now we assume CFG_HZ
equals to CP0 counter frequency, but this is wrong. CFG_HZ has to be 1000
in the U-Boot system.
The other is we don't have a proper time management counter like timestamp
other ARCHs have. We need the 32-bit millisecond clock counter.
This patch introduces timestamp and CYCLES_PER_JIFFY. timestamp is a
32-bit non-overflowing CFG_HZ counter, and CYCLES_PER_JIFFY is the number
of calculated CP0 counter cycles in a CFG_HZ.
STRATEGY:
* Fix improper CFG_HZ value to have 1000
* Use CFG_MIPS_TIMER_FREQ for timer counter frequency, instead.
* timer_init: initialize timestamp and set up the first timer expiration.
Note that we don't need to initialize CP0 count/compare registers here
as they have been already zeroed out on the system reset. Leave them as
they are.
* get_timer: calculate how many timestamps have been passed, then return
base-relative timestamp. Make sure we can easily count missed timestamps
regardless of CP0 count/compare value.
* get_ticks: return the current timestamp, that is get_timer(0).
Most parts are from good old Linux v2.6.16 kernel.
v2:
- Remove FIXME comments as they turned out to be trivial.
- Use CP0 compare register as a global variable for expirelo.
- Kill a global variable 'cycles_per_jiffy'. Use #define CYCLES_PER_JIFFY
instead.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
The U-boot DM9000x driver contains a compile time bus-width definition for
the databus connected to the network controller.
This compile check makes the code unclear, inflexible and is unneccessary.
It can be asked to the network controller what its bus-width is by reading bits
6 and 7 of the interrupt status register.
The linux kernel already uses a runtime mechanism to determine this bus-width,
so the implementation below looks somewhat like that implementation.
This change has been tested with DM9000A, DM9000E, DM9000EP.
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch removes some dead code from CPCI405 board's
config files. JFFS2 support is also removed. It's not used and
CPCI4052 does not build anymore without some size reduction.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This patch gets rid of the spi_chipsel table and adds a handful of new
functions that makes the SPI layer cleaner and more flexible.
Instead of the spi_chipsel table, each board that wants to use SPI
gets to implement three hooks:
* spi_cs_activate(): Activates the chipselect for a given slave
* spi_cs_deactivate(): Deactivates the chipselect for a given slave
* spi_cs_is_valid(): Determines if the given bus/chipselect
combination can be activated.
Not all drivers may need those extra functions however. If that's the
case, the board code may just leave them out (assuming they know what
the driver needs) or rely on the linker to strip them out (assuming
--gc-sections is being used.)
To set up communication parameters for a given slave, the driver needs
to call spi_setup_slave(). This returns a pointer to an opaque
spi_slave struct which must be passed as a parameter to subsequent SPI
calls. This struct can be freed by calling spi_free_slave(), but most
driver probably don't want to do this.
Before starting one or more SPI transfers, the driver must call
spi_claim_bus() to gain exclusive access to the SPI bus and initialize
the hardware. When all transfers are done, the driver must call
spi_release_bus() to make the bus available to others, and possibly
shut down the SPI controller hardware.
spi_xfer() behaves mostly the same as before, but it now takes a
spi_slave parameter instead of a spi_chipsel function pointer. It also
got a new parameter, flags, which is used to specify chip select
behaviour. This may be extended with other flags in the future.
This patch has been build-tested on all powerpc and arm boards
involved. I have not tested NIOS since I don't have a toolchain for it
installed, so I expect some breakage there even though I've tried
fixing up everything I could find by visual inspection.
I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and
DataFlash drivers posted as a follow-up. I'd like some help testing
other boards that use the existing SPI API.
But most of all, I'd like some comments on the new API. Is this stuff
usable for everyone? If not, why?
Changed in v4:
- Build fixes for various boards, drivers and commands
- Provide common struct spi_slave definition that can be extended by
drivers
- Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate
- Make default bus and mode build-time configurable
- Override default SPI bus ID and mode on mx32ads and imx31_litekit.
Changed in v3:
- Add opaque struct spi_slave for controller-specific data associated
with a slave.
- Add spi_claim_bus() and spi_release_bus()
- Add spi_free_slave()
- spi_setup() is now called spi_setup_slave() and returns a
struct spi_slave
- soft_spi now supports four SPI modes (CPOL|CPHA)
- Add bus parameter to spi_setup_slave()
- Convert the new i.MX32 SPI driver
- Convert the new MC13783 RTC driver
Changed in v2:
- Convert the mpc8xxx_spi driver and the mpc8349emds board to the
new API.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Tested-by: Guennadi Liakhovetski <lg@denx.de>
This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.
Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch (Part 2 of 2):
* Rolls up a suite of changes to enable correct primordial stack and
global data handling when the data cache is used for such a purpose
for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).
* Related to the first, unifies DDR2 SDRAM and ECC initialization by
eliminating redundant ECC initialization implementations and moving
redundant SDRAM initialization out of board code into shared 4xx
code.
* Enables MCSR visibility on the 405EX(r).
* Enables the use of the data cache for initial RAM on
both AMCC's Kilauea and Makalu and removes a redundant
CFG_POST_MEMORY flag from each board's CONFIG_POST value.
- Removed, per Stefan Roese's request, defunct memory.c file for
Makalu and rolled sdram_init from it into makalu.c.
With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Change all code that conditionally operates on high bat
registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS
instead of the myriad ways this is done now. Define the option
for every config for which high bats are supported (and
enabled by early boot, on parts where they're not always
enabled)
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
This cleans up the SDRAM initialization and related code a bit, and
allows faster booting.
* Add definitions for EBI and internal SRAM to asm/arch/memory-map.h
* Remove memory test from sdram_init() and make caller responsible
for verifying the SDRAM and determining its size.
* Remove base_address member from struct sdram_config (was sdram_info)
* Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT
* Add support for a common STK1000 hack: 16MB SDRAM instead of 8.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This is a replacement for ATSTK1002 with 64MB SDRAM and NAND flash on
board. It's currently in production and will be available soon.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Make STK1002 and NGW100 boards act more alike:
- STK boards can use as many arguments as NGW
- STK boards don't need to manage FPGAs either
- NGW commands should match STK ones
Also spell U-Boot right in prompts for STK1002 and NGW100.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
[haavard.skinnemoen@atmel.com: update STK100[34] as well]
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
