mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-sh
This commit is contained in:
Wolfgang Denk
commit
b77cddc7b5
12 changed files with 850 additions and 55 deletions
|
|
@ -722,6 +722,7 @@ Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
|||
MS7722SE SH7722
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||||
R7780MP SH7780
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||||
R2DPlus SH7751R
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||||
SH7763RDP SH7763
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||||
|
||||
Mark Jonas <mark.jonas@de.bosch.com>
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||||
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||||
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|
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1
MAKEALL
1
MAKEALL
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|
@ -751,6 +751,7 @@ LIST_sh4=" \
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|||
Migo-R \
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||||
r7780mp \
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r2dplus \
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||||
sh7763rdp \
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||||
"
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||||
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||||
LIST_sh=" \
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||||
|
|
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|||
5
Makefile
5
Makefile
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@ -2944,6 +2944,11 @@ r2dplus_config : unconfig
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|||
@echo "#define CONFIG_R2DPLUS 1" >> include/config.h
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||||
@./mkconfig -a $(@:_config=) sh sh4 r2dplus
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||||
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||||
sh7763rdp_config : unconfig
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||||
@ >include/config.h
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||||
@echo "#define CONFIG_SH7763RDP 1" >> include/config.h
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||||
@./mkconfig -a $(@:_config=) sh sh4 sh7763rdp
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|
||||
#========================================================================
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||||
# SPARC
|
||||
#========================================================================
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||||
|
|
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|||
47
board/sh7763rdp/Makefile
Normal file
47
board/sh7763rdp/Makefile
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# Copyright (C) 2008 Renesas Solutions Corp.
|
||||
# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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||||
# Copyright (C) 2007 Kenati Technologies, Inc.
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||||
#
|
||||
# board/sh7763rdp/Makefile
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||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
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||||
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LIB = lib$(BOARD).a
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OBJS := sh7763rdp.o
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SOBJS := lowlevel_init.o
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||||
|
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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|
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clean:
|
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rm -f $(SOBJS) $(OBJS)
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||||
|
||||
distclean: clean
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||||
rm -f $(LIB) core *.bak .depend
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||||
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#########################################################################
|
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||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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||||
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||||
-include .depend
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||||
|
||||
#########################################################################
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||||
11
board/sh7763rdp/config.mk
Normal file
11
board/sh7763rdp/config.mk
Normal file
|
|
@ -0,0 +1,11 @@
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|||
#
|
||||
# board/sh7763rdp/config.mk
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||||
#
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||||
# TEXT_BASE refers to image _after_ relocation.
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#
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||||
# NOTE: Must match value used in u-boot.lds (in this directory).
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||||
#
|
||||
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||||
TEXT_BASE = 0x8FFC0000
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||||
|
||||
# PLATFORM_CPPFLAGS += -DCONFIG_MULTIBOOT
|
||||
351
board/sh7763rdp/lowlevel_init.S
Normal file
351
board/sh7763rdp/lowlevel_init.S
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
* Copyright (C) 2007 Kenati Technologies, Inc.
|
||||
*
|
||||
* board/sh7763rdp/lowlevel_init.S
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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||||
*/
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||||
|
||||
#include <config.h>
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||||
#include <version.h>
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#include <asm/processor.h>
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||||
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.global lowlevel_init
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.text
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.align 2
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||||
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||||
lowlevel_init:
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||||
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||||
mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */
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||||
mov.l WDTCSR_D, r0
|
||||
mov.l r0, @r1
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||||
|
||||
mov.l WDTST_A, r1 /* Watchdog Stop Time Register */
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||||
mov.l WDTST_D, r0
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||||
mov.l r0, @r1
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||||
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||||
mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */
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||||
mov.l WDTBST_D, r0
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||||
mov.l r0, @r1
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||||
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||||
mov.l CCR_A, r1 /* Address of Cache Control Register */
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||||
mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */
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||||
mov.l r0, @r1
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||||
|
||||
mov.l MMUCR_A, r1 /* Address of MMU Control Register */
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||||
mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */
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||||
mov.l r0, @r1
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||||
|
||||
mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */
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||||
mov.l MSTPCR0_D, r0
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||||
mov.l r0, @r1
|
||||
|
||||
mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */
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||||
mov.l MSTPCR1_D, r0
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||||
mov.l r0, @r1
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||||
|
||||
mov.l RAMCR_A,r1
|
||||
mov.l RAMCR_D,r0
|
||||
mov.l r0, @r1
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||||
|
||||
mov.l MMSELR_A,r1
|
||||
mov.l MMSELR_D,r0
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||||
synco
|
||||
mov.l r0, @r1
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||||
|
||||
mov.l @r1,r2 /* execute two reads after setting MMSELR*/
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||||
mov.l @r1,r2
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||||
synco
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||||
|
||||
/* issue memory read */
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||||
mov.l DDRSD_START_A,r1 /* memory address to read*/
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||||
mov.l @r1,r0
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||||
synco
|
||||
|
||||
mov.l MIM8_A,r1
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||||
mov.l MIM8_D,r0
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||||
mov.l r0,@r1
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||||
|
||||
mov.l MIMC_A,r1
|
||||
mov.l MIMC_D1,r0
|
||||
mov.l r0,@r1
|
||||
|
||||
mov.l STRC_A,r1
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||||
mov.l STRC_D,r0
|
||||
mov.l r0,@r1
|
||||
|
||||
mov.l SDR4_A,r1
|
||||
mov.l SDR4_D,r0
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||||
mov.l r0,@r1
|
||||
|
||||
mov.l MIMC_A,r1
|
||||
mov.l MIMC_D2,r0
|
||||
mov.l r0,@r1
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||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
mov.l SCR4_A,r1
|
||||
mov.l SCR4_D3,r0
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||||
mov.l r0,@r1
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||||
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||||
mov.l SCR4_A,r1
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||||
mov.l SCR4_D2,r0
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||||
mov.l r0,@r1
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||||
|
||||
mov.l SDMR02000_A,r1
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||||
mov.l SDMR02000_D,r0
|
||||
mov.l r0,@r1
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||||
|
||||
mov.l SDMR00B08_A,r1
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||||
mov.l SDMR00B08_D,r0
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||||
mov.l r0,@r1
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||||
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||||
mov.l SCR4_A,r1
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||||
mov.l SCR4_D2,r0
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||||
mov.l r0,@r1
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||||
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||||
mov.l SCR4_A,r1
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||||
mov.l SCR4_D4,r0
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||||
mov.l r0,@r1
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||||
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||||
nop
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||||
nop
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||||
nop
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||||
nop
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||||
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||||
mov.l SCR4_A,r1
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||||
mov.l SCR4_D4,r0
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||||
mov.l r0,@r1
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||||
|
||||
nop
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||||
nop
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||||
nop
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||||
nop
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||||
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||||
mov.l SDMR00308_A,r1
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||||
mov.l SDMR00308_D,r0
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||||
mov.l r0,@r1
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||||
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||||
mov.l MIMC_A,r1
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||||
mov.l MIMC_D3,r0
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||||
mov.l r0,@r1
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||||
|
||||
mov.l SCR4_A,r1
|
||||
mov.l SCR4_D1,r0
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||||
mov.l DELAY60_D,r3
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||||
|
||||
delay_loop_60:
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||||
mov.l r0,@r1
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||||
dt r3
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||||
bf delay_loop_60
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||||
nop
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||||
|
||||
mov.l CCR_A, r1 /* Address of Cache Control Register */
|
||||
mov.l CCR_CACHE_D_2, r0
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||||
mov.l r0, @r1
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||||
|
||||
bsc_init:
|
||||
mov.l BCR_A, r1
|
||||
mov.l BCR_D, r0
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||||
mov.l r0, @r1
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||||
|
||||
mov.l CS0BCR_A, r1
|
||||
mov.l CS0BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS1BCR_A,r1
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||||
mov.l CS1BCR_D,r0
|
||||
mov.l r0,@r1
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||||
|
||||
mov.l CS2BCR_A, r1
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||||
mov.l CS2BCR_D, r0
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||||
mov.l r0, @r1
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||||
|
||||
mov.l CS4BCR_A, r1
|
||||
mov.l CS4BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS5BCR_A, r1
|
||||
mov.l CS5BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS6BCR_A, r1
|
||||
mov.l CS6BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS0WCR_A, r1
|
||||
mov.l CS0WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS1WCR_A, r1
|
||||
mov.l CS1WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS2WCR_A, r1
|
||||
mov.l CS2WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS4WCR_A, r1
|
||||
mov.l CS4WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS5WCR_A, r1
|
||||
mov.l CS5WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS6WCR_A, r1
|
||||
mov.l CS6WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS5PCR_A, r1
|
||||
mov.l CS5PCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l CS6PCR_A, r1
|
||||
mov.l CS6PCR_D, r0
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l DELAY200_D,r3
|
||||
|
||||
delay_loop_200:
|
||||
dt r3
|
||||
bf delay_loop_200
|
||||
nop
|
||||
|
||||
mov.l PSEL0_A,r1
|
||||
mov.l PSEL0_D,r0
|
||||
mov.w r0,@r1
|
||||
|
||||
mov.l PSEL1_A,r1
|
||||
mov.l PSEL1_D,r0
|
||||
mov.w r0,@r1
|
||||
|
||||
mov.l ICR0_A,r1
|
||||
mov.l ICR0_D,r0
|
||||
mov.l r0,@r1
|
||||
|
||||
stc sr, r0 /* BL bit off(init=ON) */
|
||||
mov.l SR_MASK_D, r1
|
||||
and r1, r0
|
||||
ldc r0, sr
|
||||
|
||||
rts
|
||||
nop
|
||||
|
||||
.align 2
|
||||
|
||||
DELAY60_D: .long 60
|
||||
DELAY200_D: .long 17800
|
||||
|
||||
CCR_A: .long 0xFF00001C
|
||||
MMUCR_A: .long 0xFF000010
|
||||
RAMCR_A: .long 0xFF000074
|
||||
|
||||
/* Low power mode control */
|
||||
MSTPCR0_A: .long 0xFFC80030
|
||||
MSTPCR1_A: .long 0xFFC80038
|
||||
|
||||
/* RWBT */
|
||||
WDTST_A: .long 0xFFCC0000
|
||||
WDTCSR_A: .long 0xFFCC0004
|
||||
WDTBST_A: .long 0xFFCC0008
|
||||
|
||||
/* BSC */
|
||||
MMSELR_A: .long 0xFE600020
|
||||
BCR_A: .long 0xFF801000
|
||||
CS0BCR_A: .long 0xFF802000
|
||||
CS1BCR_A: .long 0xFF802010
|
||||
CS2BCR_A: .long 0xFF802020
|
||||
CS4BCR_A: .long 0xFF802040
|
||||
CS5BCR_A: .long 0xFF802050
|
||||
CS6BCR_A: .long 0xFF802060
|
||||
CS0WCR_A: .long 0xFF802008
|
||||
CS1WCR_A: .long 0xFF802018
|
||||
CS2WCR_A: .long 0xFF802028
|
||||
CS4WCR_A: .long 0xFF802048
|
||||
CS5WCR_A: .long 0xFF802058
|
||||
CS6WCR_A: .long 0xFF802068
|
||||
CS5PCR_A: .long 0xFF802070
|
||||
CS6PCR_A: .long 0xFF802080
|
||||
DDRSD_START_A: .long 0xAC000000
|
||||
|
||||
/* INTC */
|
||||
ICR0_A: .long 0xFFD00000
|
||||
|
||||
/* DDR I/F */
|
||||
MIM8_A: .long 0xFE800008
|
||||
MIMC_A: .long 0xFE80000C
|
||||
SCR4_A: .long 0xFE800014
|
||||
STRC_A: .long 0xFE80001C
|
||||
SDR4_A: .long 0xFE800034
|
||||
SDMR00308_A: .long 0xFE900308
|
||||
SDMR00B08_A: .long 0xFE900B08
|
||||
SDMR02000_A: .long 0xFE902000
|
||||
|
||||
/* GPIO */
|
||||
PSEL0_A: .long 0xFFEF0070
|
||||
PSEL1_A: .long 0xFFEF0072
|
||||
|
||||
CCR_CACHE_ICI_D:.long 0x00000800
|
||||
CCR_CACHE_D_2: .long 0x00000103
|
||||
MMU_CONTROL_TI_D:.long 0x00000004
|
||||
RAMCR_D: .long 0x00000200
|
||||
MSTPCR0_D: .long 0x00000000
|
||||
MSTPCR1_D: .long 0x00000000
|
||||
|
||||
MMSELR_D: .long 0xa5a50000
|
||||
BCR_D: .long 0x00000000
|
||||
CS0BCR_D: .long 0x77777770
|
||||
CS1BCR_D: .long 0x77777670
|
||||
CS2BCR_D: .long 0x77777670
|
||||
CS4BCR_D: .long 0x77777670
|
||||
CS5BCR_D: .long 0x77777670
|
||||
CS6BCR_D: .long 0x77777670
|
||||
CS0WCR_D: .long 0x7777770F
|
||||
CS1WCR_D: .long 0x22000002
|
||||
CS2WCR_D: .long 0x7777770F
|
||||
CS4WCR_D: .long 0x7777770F
|
||||
CS5WCR_D: .long 0x7777770F
|
||||
CS6WCR_D: .long 0x7777770F
|
||||
CS5PCR_D: .long 0x77000000
|
||||
CS6PCR_D: .long 0x77000000
|
||||
ICR0_D: .long 0x00E00000
|
||||
MIM8_D: .long 0x00000000
|
||||
MIMC_D1: .long 0x01d10008
|
||||
MIMC_D2: .long 0x01d10009
|
||||
MIMC_D3: .long 0x01d10209
|
||||
SCR4_D1: .long 0x00000001
|
||||
SCR4_D2: .long 0x00000002
|
||||
SCR4_D3: .long 0x00000003
|
||||
SCR4_D4: .long 0x00000004
|
||||
STRC_D: .long 0x000f3980
|
||||
SDR4_D: .long 0x00000300
|
||||
SDMR00308_D: .long 0x00000000
|
||||
SDMR00B08_D: .long 0x00000000
|
||||
SDMR02000_D: .long 0x00000000
|
||||
PSEL0_D: .long 0x00000001
|
||||
PSEL1_D: .long 0x00000244
|
||||
SR_MASK_D: .long 0xEFFFFF0F
|
||||
WDTST_D: .long 0x5A000FFF
|
||||
WDTCSR_D: .long 0xA5000000
|
||||
WDTBST_D: .long 0x55000000
|
||||
|
||||
76
board/sh7763rdp/sh7763rdp.c
Normal file
76
board/sh7763rdp/sh7763rdp.c
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
* Copyright (C) 2007 Kenati Technologies, Inc.
|
||||
*
|
||||
* board/sh7763rdp/sh7763rdp.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#define CPU_CMDREG 0xB1000006
|
||||
#define PDCR 0xffef0006
|
||||
#define PECR 0xffef0008
|
||||
#define PFCR 0xffef000a
|
||||
#define PGCR 0xffef000c
|
||||
#define PHCR 0xffef000e
|
||||
#define PJCR 0xffef0012
|
||||
#define PKCR 0xffef0014
|
||||
#define PLCR 0xffef0016
|
||||
#define PMCR 0xffef0018
|
||||
#define PSEL1 0xffef0072
|
||||
#define PSEL2 0xffef0074
|
||||
#define PSEL3 0xffef0076
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("BOARD: Renesas SH7763 RDP\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
vu_short dat;
|
||||
|
||||
*(vu_short *)(CPU_CMDREG) |= 0x0001;
|
||||
|
||||
/* GPIO Setting (eth1) */
|
||||
dat = *(vu_short *)(PSEL1);
|
||||
*(vu_short *)PSEL1 = ((dat & ~0xff00) | 0x2400);
|
||||
*(vu_short *)PFCR = 0;
|
||||
*(vu_short *)PGCR = 0;
|
||||
*(vu_short *)PHCR = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_memstart = CFG_SDRAM_BASE;
|
||||
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
|
||||
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void led_set_state (unsigned short value)
|
||||
{
|
||||
}
|
||||
106
board/sh7763rdp/u-boot.lds
Normal file
106
board/sh7763rdp/u-boot.lds
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyrigth (c) 2007,2008
|
||||
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
|
||||
OUTPUT_ARCH(sh)
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*
|
||||
Base address of internal SDRAM is 0x0C000000.
|
||||
Although size of SDRAM can be either 16 or 32 MBytes,
|
||||
we assume 16 MBytes (ie ignore upper half if the full
|
||||
32 MBytes is present).
|
||||
|
||||
NOTE: This address must match with the definition of
|
||||
TEXT_BASE in config.mk (in this directory).
|
||||
|
||||
*/
|
||||
. = 0x8C000000 + (64*1024*1024) - (256*1024);
|
||||
|
||||
PROVIDE (reloc_dst = .);
|
||||
|
||||
PROVIDE (_ftext = .);
|
||||
PROVIDE (_fcode = .);
|
||||
PROVIDE (_start = .);
|
||||
|
||||
.text :
|
||||
{
|
||||
cpu/sh4/start.o (.text)
|
||||
. = ALIGN(8192);
|
||||
common/environment.o (.ppcenv)
|
||||
. = ALIGN(8192);
|
||||
common/environment.o (.ppcenvr)
|
||||
. = ALIGN(8192);
|
||||
*(.text)
|
||||
. = ALIGN(4);
|
||||
} =0xFF
|
||||
PROVIDE (_ecode = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_etext = .);
|
||||
|
||||
|
||||
PROVIDE (_fdata = .);
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_edata = .);
|
||||
|
||||
PROVIDE (_fgot = .);
|
||||
.got :
|
||||
{
|
||||
*(.got)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_egot = .);
|
||||
|
||||
PROVIDE (__u_boot_cmd_start = .);
|
||||
.u_boot_cmd :
|
||||
{
|
||||
*(.u_boot_cmd)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (__u_boot_cmd_end = .);
|
||||
|
||||
PROVIDE (reloc_dst_end = .);
|
||||
/* _reloc_dst_end = .; */
|
||||
|
||||
PROVIDE (bss_start = .);
|
||||
PROVIDE (__bss_start = .);
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (bss_end = .);
|
||||
|
||||
PROVIDE (_end = .);
|
||||
}
|
||||
|
||||
|
|
@ -26,6 +26,8 @@
|
|||
#define SCIF_BASE SCIF0_BASE
|
||||
#elif defined (CONFIG_CONS_SCIF1)
|
||||
#define SCIF_BASE SCIF1_BASE
|
||||
#elif defined (CONFIG_CONS_SCIF2)
|
||||
#define SCIF_BASE SCIF2_BASE
|
||||
#else
|
||||
#error "Default SCIF doesn't set....."
|
||||
#endif
|
||||
|
|
@ -36,17 +38,17 @@
|
|||
#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
|
||||
#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
|
||||
#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
|
||||
#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
|
||||
# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
|
||||
#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
|
||||
# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
|
||||
# define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
|
||||
# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
|
||||
#else
|
||||
# define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
|
||||
# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
|
||||
# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
|
||||
# define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SH7780) || \
|
||||
#if defined(CONFIG_CPU_SH7780) || \
|
||||
defined(CONFIG_CPU_SH7785)
|
||||
# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
|
||||
# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
|
||||
|
|
@ -54,20 +56,34 @@
|
|||
# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0xFF
|
||||
#elif defined(CONFIG_CPU_SH7763)
|
||||
# if defined (CONFIG_CONS_SCIF2)
|
||||
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0x1F
|
||||
# else
|
||||
# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
|
||||
# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
|
||||
# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0xFF
|
||||
# endif
|
||||
#elif defined(CONFIG_CPU_SH7750) || \
|
||||
defined(CONFIG_CPU_SH7751) || \
|
||||
defined(CONFIG_CPU_SH7722)
|
||||
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0x1F
|
||||
#elif defined(CONFIG_CPU_SH7720)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
|
||||
# define LSR_ORER 0x0200
|
||||
# define FIFOLEVEL_MASK 0x1F
|
||||
#elif defined(CONFIG_CPU_SH7710)
|
||||
#elif defined(CONFIG_CPU_SH7710) || \
|
||||
defined(CONFIG_CPU_SH7712)
|
||||
# define SCLSR SCFSR /* SCSSR */
|
||||
# define SCLSR SCFSR /* SCSSR */
|
||||
# define LSR_ORER 1
|
||||
# define FIFOLEVEL_MASK 0x1F
|
||||
#endif
|
||||
|
|
@ -75,34 +91,34 @@
|
|||
/* SCBRR register value setting */
|
||||
#if defined(CONFIG_CPU_SH7720)
|
||||
# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
|
||||
#else /* Generic SuperH */
|
||||
#else /* Generic SuperH */
|
||||
# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
|
||||
#endif
|
||||
|
||||
#define SCR_RE (1 << 4)
|
||||
#define SCR_TE (1 << 5)
|
||||
#define FCR_RFRST (1 << 1) /* RFCL */
|
||||
#define FCR_TFRST (1 << 2) /* TFCL */
|
||||
#define FSR_DR (1 << 0)
|
||||
#define FSR_RDF (1 << 1)
|
||||
#define FSR_FER (1 << 3)
|
||||
#define FSR_BRK (1 << 4)
|
||||
#define FSR_FER (1 << 3)
|
||||
#define FSR_TEND (1 << 6)
|
||||
#define FSR_ER (1 << 7)
|
||||
#define SCR_RE (1 << 4)
|
||||
#define SCR_TE (1 << 5)
|
||||
#define FCR_RFRST (1 << 1) /* RFCL */
|
||||
#define FCR_TFRST (1 << 2) /* TFCL */
|
||||
#define FSR_DR (1 << 0)
|
||||
#define FSR_RDF (1 << 1)
|
||||
#define FSR_FER (1 << 3)
|
||||
#define FSR_BRK (1 << 4)
|
||||
#define FSR_FER (1 << 3)
|
||||
#define FSR_TEND (1 << 6)
|
||||
#define FSR_ER (1 << 7)
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
void serial_setbrg (void)
|
||||
void serial_setbrg(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
*SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ);
|
||||
*SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
|
||||
}
|
||||
|
||||
int serial_init (void)
|
||||
int serial_init(void)
|
||||
{
|
||||
*SCSCR = (SCR_RE | SCR_TE);
|
||||
*SCSMR = 0 ;
|
||||
*SCSMR = 0;
|
||||
*SCSMR = 0;
|
||||
*SCFCR = (FCR_RFRST | FCR_TFRST);
|
||||
*SCFCR;
|
||||
|
|
@ -112,21 +128,21 @@ int serial_init (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int serial_rx_fifo_level (void)
|
||||
static int serial_rx_fifo_level(void)
|
||||
{
|
||||
#if defined(CONFIG_SH4A)
|
||||
#if defined(SCRFDR)
|
||||
return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
|
||||
#else
|
||||
return (*SCFDR >> 0) & FIFOLEVEL_MASK;
|
||||
#endif
|
||||
}
|
||||
|
||||
void serial_raw_putc (const char c)
|
||||
void serial_raw_putc(const char c)
|
||||
{
|
||||
unsigned int fsr_bits_to_clear;
|
||||
|
||||
while (1) {
|
||||
if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
|
||||
if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
|
||||
fsr_bits_to_clear = FSR_TEND;
|
||||
break;
|
||||
}
|
||||
|
|
@ -137,65 +153,67 @@ void serial_raw_putc (const char c)
|
|||
*SCFSR &= ~fsr_bits_to_clear;
|
||||
}
|
||||
|
||||
void serial_putc (const char c)
|
||||
void serial_putc(const char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
serial_raw_putc ('\r');
|
||||
serial_raw_putc (c);
|
||||
serial_raw_putc('\r');
|
||||
serial_raw_putc(c);
|
||||
}
|
||||
|
||||
void serial_puts (const char *s)
|
||||
void serial_puts(const char *s)
|
||||
{
|
||||
char c;
|
||||
while ((c = *s++) != 0)
|
||||
serial_putc (c);
|
||||
serial_putc(c);
|
||||
}
|
||||
|
||||
int serial_tstc (void)
|
||||
int serial_tstc(void)
|
||||
{
|
||||
return serial_rx_fifo_level() ? 1 : 0;
|
||||
return serial_rx_fifo_level()? 1 : 0;
|
||||
}
|
||||
|
||||
#define FSR_ERR_CLEAR 0x0063
|
||||
#define RDRF_CLEAR 0x00fc
|
||||
void handle_error( void ){
|
||||
#define FSR_ERR_CLEAR 0x0063
|
||||
#define RDRF_CLEAR 0x00fc
|
||||
void handle_error(void)
|
||||
{
|
||||
|
||||
(void)*SCFSR ;
|
||||
*SCFSR = FSR_ERR_CLEAR ;
|
||||
(void)*SCLSR ;
|
||||
*SCLSR = 0x00 ;
|
||||
(void)*SCFSR;
|
||||
*SCFSR = FSR_ERR_CLEAR;
|
||||
(void)*SCLSR;
|
||||
*SCLSR = 0x00;
|
||||
}
|
||||
|
||||
int serial_getc_check( void ){
|
||||
int serial_getc_check(void)
|
||||
{
|
||||
unsigned short status;
|
||||
|
||||
status = *SCFSR ;
|
||||
status = *SCFSR;
|
||||
|
||||
if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
|
||||
if (status & (FSR_FER | FSR_ER | FSR_BRK))
|
||||
handle_error();
|
||||
if( *SCLSR & LSR_ORER )
|
||||
if (*SCLSR & LSR_ORER)
|
||||
handle_error();
|
||||
return (status & ( FSR_DR | FSR_RDF ));
|
||||
return (status & (FSR_DR | FSR_RDF));
|
||||
}
|
||||
|
||||
int serial_getc (void)
|
||||
int serial_getc(void)
|
||||
{
|
||||
unsigned short status ;
|
||||
unsigned short status;
|
||||
char ch;
|
||||
while(!serial_getc_check());
|
||||
while (!serial_getc_check()) ;
|
||||
|
||||
ch = *SCFRDR;
|
||||
status = *SCFSR ;
|
||||
status = *SCFSR;
|
||||
|
||||
*SCFSR = RDRF_CLEAR ;
|
||||
*SCFSR = RDRF_CLEAR;
|
||||
|
||||
if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
|
||||
handle_error();
|
||||
|
||||
if( *SCLSR & LSR_ORER )
|
||||
if (*SCLSR & LSR_ORER)
|
||||
handle_error();
|
||||
|
||||
return ch ;
|
||||
return ch;
|
||||
}
|
||||
|
||||
#endif /* CFG_SCIF_CONSOLE */
|
||||
#endif /* CFG_SCIF_CONSOLE */
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@
|
|||
# include <asm/cpu_sh7750.h>
|
||||
#elif defined (CONFIG_CPU_SH7722)
|
||||
# include <asm/cpu_sh7722.h>
|
||||
#elif defined (CONFIG_CPU_SH7763)
|
||||
# include <asm/cpu_sh7763.h>
|
||||
#elif defined (CONFIG_CPU_SH7780)
|
||||
# include <asm/cpu_sh7780.h>
|
||||
#else
|
||||
|
|
|
|||
51
include/asm-sh/cpu_sh7763.h
Normal file
51
include/asm-sh/cpu_sh7763.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _ASM_CPU_SH7763_H_
|
||||
#define _ASM_CPU_SH7763_H_
|
||||
|
||||
/* CACHE */
|
||||
#define CACHE_OC_NUM_WAYS 1
|
||||
#define CCR 0xFF00001C
|
||||
#define CCR_CACHE_INIT 0x0000090b
|
||||
|
||||
/* SCIF */
|
||||
/* SCIF0 */
|
||||
#define SCIF0_BASE SCSMR0
|
||||
#define SCSMR0 0xFFE00000
|
||||
|
||||
/* SCIF1 */
|
||||
#define SCIF1_BASE SCSMR1
|
||||
#define SCSMR1 0xFFE08000
|
||||
|
||||
/* SCIF2 */
|
||||
#define SCIF2_BASE SCSMR2
|
||||
#define SCSMR2 0xFFE10000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WTCNT WDTST
|
||||
#define WDTST 0xFFCC0000
|
||||
|
||||
/* TMU */
|
||||
#define TSTR 0xFFD80004
|
||||
#define TCOR0 0xFFD80008
|
||||
#define TCNT0 0xFFD8000C
|
||||
#define TCR0 0xFFD80010
|
||||
|
||||
#endif /* _ASM_CPU_SH7763_H_ */
|
||||
126
include/configs/sh7763rdp.h
Normal file
126
include/configs/sh7763rdp.h
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Configuation settings for the Renesas SH7763RDP board
|
||||
*
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __SH7763RDP_H
|
||||
#define __SH7763RDP_H
|
||||
|
||||
#define CONFIG_SH 1
|
||||
#define CONFIG_SH4 1
|
||||
#define CONFIG_CPU_SH7763 1
|
||||
#define CONFIG_SH7763RDP 1
|
||||
#define __LITTLE_ENDIAN 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* SCIF */
|
||||
#define CFG_SCIF_CONSOLE 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_CONS_SCIF2 1
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
|
||||
#define CFG_PBSIZE 256 /* Buffer size for Console output */
|
||||
#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
|
||||
#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments
|
||||
passed to kernel */
|
||||
#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
|
||||
settings for this board */
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_SH_ETHER 1
|
||||
#define CONFIG_SH_ETHER_USE_PORT (1)
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
|
||||
#define CFG_RX_ETH_BUFFER (8)
|
||||
|
||||
/* SDRAM */
|
||||
#define CFG_SDRAM_BASE (0x8C000000)
|
||||
#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
|
||||
#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
|
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
|
||||
|
||||
/* Flash(NOR) */
|
||||
#define CFG_FLASH_BASE (0xA0000000)
|
||||
#define CFG_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
|
||||
#define CFG_MAX_FLASH_BANKS (1)
|
||||
#define CFG_MAX_FLASH_SECT (520)
|
||||
|
||||
/* U-boot setting */
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
|
||||
#define CFG_MONITOR_LEN (128 * 1024)
|
||||
/* Size of DRAM reserved for malloc() use */
|
||||
#define CFG_MALLOC_LEN (1024 * 1024)
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_SIZE (256)
|
||||
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#undef CFG_FLASH_QUIET_TEST
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
/* Timeout for Flash erase operations (in ms) */
|
||||
#define CFG_FLASH_ERASE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash write operations (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash set sector lock bit operations (in ms) */
|
||||
#define CFG_FLASH_LOCK_TOUT (3 * 1000)
|
||||
/* Timeout for Flash clear lock bit operations (in ms) */
|
||||
#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
|
||||
/* Use hardware flash sectors protection instead of U-Boot software protection */
|
||||
#undef CFG_FLASH_PROTECTION
|
||||
#undef CFG_DIRECT_FLASH_TFTP
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE))
|
||||
/* Offset of env Flash sector relative to CFG_FLASH_BASE */
|
||||
#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
|
||||
|
||||
/* Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
|
||||
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
|
||||
|
||||
#endif /* __SH7763RDP_H */
|
||||
Loading…
Reference in a new issue