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https://github.com/AsahiLinux/u-boot
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ppc4xx: Cleanup Katmai & Yucca PCIe register usage
This patch cleans up the 440SPe PCIe register usage. Now only defines from the include/asm-ppc/4xx_pcie.h are used. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
parent
5de851403b
commit
d9056b7913
3 changed files with 8 additions and 127 deletions
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@ -349,7 +349,7 @@ int is_pci_host(struct pci_controller *hose)
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return 1;
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}
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int katmai_pcie_card_present(int port)
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static int katmai_pcie_card_present(int port)
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{
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u32 val;
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@ -437,76 +437,6 @@ void pcie_setup_hoses(int busno)
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}
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#endif /* defined(CONFIG_PCI) */
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int misc_init_f (void)
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{
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uint reg;
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#if defined(CONFIG_STRESS)
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uint i ;
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uint disp;
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#endif
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/* minimal init for PCIe */
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#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
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/* pci express 0 Endpoint Mode */
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mfsdr(SDR0_PE0DLPSET, reg);
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reg &= (~0x00400000);
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mtsdr(SDR0_PE0DLPSET, reg);
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#else
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/* pci express 0 Rootpoint Mode */
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mfsdr(SDR0_PE0DLPSET, reg);
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reg |= 0x00400000;
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mtsdr(SDR0_PE0DLPSET, reg);
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#endif
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/* pci express 1 Rootpoint Mode */
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mfsdr(SDR0_PE1DLPSET, reg);
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reg |= 0x00400000;
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mtsdr(SDR0_PE1DLPSET, reg);
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/* pci express 2 Rootpoint Mode */
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mfsdr(SDR0_PE2DLPSET, reg);
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reg |= 0x00400000;
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mtsdr(SDR0_PE2DLPSET, reg);
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#if defined(CONFIG_STRESS)
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/*
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* All this setting done by linux only needed by stress an charac. test
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* procedure
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* PCIe 1 Rootpoint PCIe2 Endpoint
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* PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
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*/
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for (i=0,disp=0; i<8; i++,disp+=3) {
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mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
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reg |= 0x33000000;
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mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
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}
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/*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
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for (i=0,disp=0; i<4; i++,disp+=3) {
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mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
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reg |= 0x33000000;
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mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
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}
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/*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
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for (i=0,disp=0; i<4; i++,disp+=3) {
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mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
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reg |= 0x33000000;
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mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
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}
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reg = 0x21242222;
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mtsdr(SDR0_PE2UTLSET1, reg);
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reg = 0x11000000;
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mtsdr(SDR0_PE2UTLSET2, reg);
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/* pci express 1 Endpoint Mode */
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reg = 0x00004000;
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mtsdr(SDR0_PE2DLPSET, reg);
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mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
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#endif
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return 0;
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}
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#ifdef CONFIG_POST
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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@ -677,7 +677,7 @@ int is_pci_host(struct pci_controller *hose)
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return 1;
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}
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int yucca_pcie_card_present(int port)
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static int yucca_pcie_card_present(int port)
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{
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u16 reg;
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@ -879,10 +879,6 @@ void pcie_setup_hoses(int busno)
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int misc_init_f (void)
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{
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uint reg;
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#if defined(CONFIG_STRESS)
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uint i ;
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uint disp;
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#endif
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out16(FPGA_REG10, (in16(FPGA_REG10) &
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~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
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@ -897,67 +893,23 @@ int misc_init_f (void)
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/* minimal init for PCIe */
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/* pci express 0 Endpoint Mode */
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mfsdr(SDR0_PE0DLPSET, reg);
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mfsdr(SDRN_PESDR_DLPSET(0), reg);
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reg &= (~0x00400000);
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mtsdr(SDR0_PE0DLPSET, reg);
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mtsdr(SDRN_PESDR_DLPSET(0), reg);
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/* pci express 1 Rootpoint Mode */
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mfsdr(SDR0_PE1DLPSET, reg);
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mfsdr(SDRN_PESDR_DLPSET(1), reg);
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reg |= 0x00400000;
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mtsdr(SDR0_PE1DLPSET, reg);
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mtsdr(SDRN_PESDR_DLPSET(1), reg);
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/* pci express 2 Rootpoint Mode */
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mfsdr(SDR0_PE2DLPSET, reg);
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mfsdr(SDRN_PESDR_DLPSET(2), reg);
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reg |= 0x00400000;
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mtsdr(SDR0_PE2DLPSET, reg);
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mtsdr(SDRN_PESDR_DLPSET(2), reg);
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out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
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~FPGA_REG1C_PE0_ROOTPOINT &
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~FPGA_REG1C_PE1_ENDPOINT &
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~FPGA_REG1C_PE2_ENDPOINT));
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#if defined(CONFIG_STRESS)
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/*
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* all this setting done by linux only needed by stress an charac. test
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* procedure
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* PCIe 1 Rootpoint PCIe2 Endpoint
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* PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
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* Power Level
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*/
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for (i = 0, disp = 0; i < 8; i++, disp += 3) {
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mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
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reg |= 0x33000000;
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mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
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}
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/*
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* PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
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* Power Level
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*/
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for (i = 0, disp = 0; i < 4; i++, disp += 3) {
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mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
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reg |= 0x33000000;
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mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
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}
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/*
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* PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
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* Power Level
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*/
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for (i = 0, disp = 0; i < 4; i++, disp += 3) {
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mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
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reg |= 0x33000000;
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mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
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}
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reg = 0x21242222;
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mtsdr(SDR0_PE2UTLSET1, reg);
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reg = 0x11000000;
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mtsdr(SDR0_PE2UTLSET2, reg);
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/* pci express 1 Endpoint Mode */
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reg = 0x00004000;
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mtsdr(SDR0_PE2DLPSET, reg);
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mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
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#endif
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return 0;
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}
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@ -54,7 +54,6 @@
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/*-----------------------------------------------------------------------
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