Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 23:24:38 +00:00
Code Issues Projects Releases Packages Wiki Activity

FSL DDR: Convert PM856 to new DDR code.

Browse source 
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2008-08-26 23:52:07 -05:00
parent d53bd3e17b
commit 6bfa8f723c
4 changed files with 106 additions and 31 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
board/pm856/Makefile
View file

@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o law.o tlb.o
COBJS-y += $(BOARD).o
COBJS-y += law.o
COBJS-y += tlb.o
COBJS-$(CONFIG_FSL_DDR1) += ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)

70
board/pm856/ddr.c Normal file
View file

@ -0,0 +1,70 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
static void
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
{
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
}
unsigned int
fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void
fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num)
{
unsigned int i;
unsigned int i2c_address = 0;
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
if (ctrl_num == 0 && i == 0) {
i2c_address = SPD_EEPROM_ADDRESS;
}
get_spd(&(ctrl_dimms_spd[i]), i2c_address);
}
}
void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
{
/*
* Factors to consider for CPO:
* - frequency
* - ddr1 vs. ddr2
*/
popts->cpo_override = 0;
/*
* Factors to consider for write data delay:
* - number of DIMMs
*
* 1 = 1/4 clock delay
* 2 = 1/2 clock delay
* 3 = 3/4 clock delay
* 4 = 1 clock delay
* 5 = 5/4 clock delay
* 6 = 3/2 clock delay
*/
popts->write_data_delay = 3;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
}

6
board/pm856/pm856.c
View file

@ -28,7 +28,9 @@
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <miiphy.h>
@ -260,7 +262,9 @@ initdram(int board_type)
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#else
dram_size = fixed_sdram ();
#endif

52
include/configs/PM856.h
View file

@ -45,11 +45,6 @@
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
@ -97,33 +92,36 @@
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
/* DDR Setup */
#define CONFIG_FSL_DDR1
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_SPD
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CFG_DDR_SDRAM_BASE 0x00000000
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
*/
#define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#else
/*
* Manually set up DDR parameters
*/
#define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
#define CFG_DDR_CS0_CONFIG 0x80000102
#define CFG_DDR_TIMING_1 0x47444321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
#endif
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */
/* Manually set up DDR parameters */
#define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
#define CFG_DDR_CS0_CONFIG 0x80000102
#define CFG_DDR_TIMING_1 0x47444321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
/*
* SDRAM on the Local Bus