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[MIPS] Rename Alchemy processor configs into CONFIG_SOC_*
CONFIG_SOC_AU1X00 Common Alchemy Au1x00 stuff. All Alchemy processor based machines need to have this config as a system type specifier. CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200, CONFIG_SOC_AU1500, CONFIG_SOC_AU1550 Machine type specifiers. Each port should have one of aboves. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi
Shinya Kuribayashi
parent
7daf2ebe91
commit
8bde63eb3f
8 changed files with 26 additions and 26 deletions
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@ -23,7 +23,7 @@
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*/
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#include <config.h>
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#ifdef CONFIG_AU1X00
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#ifdef CONFIG_SOC_AU1X00
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#if defined(CFG_DISCOVER_PHY)
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#error "PHY not supported yet"
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@ -33,20 +33,20 @@
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/* I assume ethernet behaves like au1000 */
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#ifdef CONFIG_AU1000
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#ifdef CONFIG_SOC_AU1000
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/* Base address differ between cpu:s */
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#define ETH0_BASE AU1000_ETH0_BASE
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#define MAC0_ENABLE AU1000_MAC0_ENABLE
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#else
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#ifdef CONFIG_AU1100
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#ifdef CONFIG_SOC_AU1100
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#define ETH0_BASE AU1100_ETH0_BASE
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#define MAC0_ENABLE AU1100_MAC0_ENABLE
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#else
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#ifdef CONFIG_AU1500
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#ifdef CONFIG_SOC_AU1500
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#define ETH0_BASE AU1500_ETH0_BASE
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#define MAC0_ENABLE AU1500_MAC0_ENABLE
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#else
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#ifdef CONFIG_AU1550
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#ifdef CONFIG_SOC_AU1550
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#define ETH0_BASE AU1550_ETH0_BASE
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#define MAC0_ENABLE AU1550_MAC0_ENABLE
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#else
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@ -308,4 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){
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return 1;
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}
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#endif /* CONFIG_AU1X00 */
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#endif /* CONFIG_SOC_AU1X00 */
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@ -27,7 +27,7 @@
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#include <config.h>
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#ifdef CONFIG_AU1X00
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#ifdef CONFIG_SOC_AU1X00
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#include <common.h>
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#include <asm/au1x00.h>
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@ -132,4 +132,4 @@ int serial_tstc (void)
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}
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return 0;
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}
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#endif /* CONFIG_SERIAL_AU1X00 */
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#endif /* CONFIG_SOC_AU1X00 */
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@ -35,7 +35,7 @@
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#include <config.h>
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#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
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#if defined(CONFIG_SOC_AU1X00) && defined(CONFIG_USB_OHCI)
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/* #include <pci.h> no PCI on the AU1x00 */
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@ -131,13 +131,13 @@
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* Returns the uncached address of a sdram address
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*/
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#ifndef __ASSEMBLY__
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#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
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#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
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/* We use a 36 bit physical address map here and
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cannot access physical memory directly from core */
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#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
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#else /* !CONFIG_AU1X00 */
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#else /* !CONFIG_SOC_AU1X00 */
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#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
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#endif /* CONFIG_AU1X00 */
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#endif /* CONFIG_SOC_AU1X00 */
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#endif /* __ASSEMBLY__ */
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/*
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@ -137,7 +137,7 @@ static __inline__ int au_ffs(int x)
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#define CP0_DEBUG $23
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/* SDRAM Controller */
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#ifdef CONFIG_AU1550
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#ifdef CONFIG_SOC_AU1550
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#define MEM_SDMODE0 0xB4000800
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#define MEM_SDMODE1 0xB4000808
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@ -156,7 +156,7 @@ static __inline__ int au_ffs(int x)
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#define MEM_SDWRMD1 0xB4000888
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#define MEM_SDWRMD2 0xB4000890
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#else /* CONFIG_AU1550 */
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#else /* CONFIG_SOC_AU1550 */
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#define MEM_SDMODE0 0xB4000000
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#define MEM_SDMODE1 0xB4000004
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@ -174,7 +174,7 @@ static __inline__ int au_ffs(int x)
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#define MEM_SDWRMD1 0xB4000028
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#define MEM_SDWRMD2 0xB400002C
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#endif /* CONFIG_AU1550 */
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#endif /* CONFIG_SOC_AU1550 */
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#define MEM_SDSLEEP 0xB4000030
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#define MEM_SDSMCKE 0xB4000034
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@ -30,21 +30,21 @@
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#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_DBAU1X00 1
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#define CONFIG_AU1X00 1 /* alchemy series cpu */
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#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
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#ifdef CONFIG_DBAU1000
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/* Also known as Merlot */
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#define CONFIG_AU1000 1
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#define CONFIG_SOC_AU1000 1
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#else
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#ifdef CONFIG_DBAU1100
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#define CONFIG_AU1100 1
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#define CONFIG_SOC_AU1100 1
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#else
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#ifdef CONFIG_DBAU1500
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#define CONFIG_AU1500 1
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#define CONFIG_SOC_AU1500 1
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#else
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#ifdef CONFIG_DBAU1550
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/* Cabernet */
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#define CONFIG_AU1550 1
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#define CONFIG_SOC_AU1550 1
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#else
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#error "No valid board set"
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#endif
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@ -30,9 +30,9 @@
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#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_GTH2 1
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#define CONFIG_AU1X00 1 /* alchemy series cpu */
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#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
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#define CONFIG_AU1000 1
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#define CONFIG_SOC_AU1000 1
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#define CONFIG_MISC_INIT_R 1
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@ -30,16 +30,16 @@
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#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_PB1X00 1
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#define CONFIG_AU1X00 1 /* alchemy series cpu */
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#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
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#ifdef CONFIG_PB1000
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#define CONFIG_AU1000 1
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#define CONFIG_SOC_AU1000 1
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#else
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#ifdef CONFIG_PB1100
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#define CONFIG_AU1100 1
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#define CONFIG_SOC_AU1100 1
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#else
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#ifdef CONFIG_PB1500
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#define CONFIG_AU1500 1
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#define CONFIG_SOC_AU1500 1
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#else
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#error "No valid board set"
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#endif
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