mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 00:21:06 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-net
This commit is contained in:
commit
32d4e38eeb
40 changed files with 384 additions and 341 deletions
15
README
15
README
|
@ -786,6 +786,21 @@ The following options need to be configured:
|
|||
Define this to use i/o functions instead of macros
|
||||
(some hardware wont work with macros)
|
||||
|
||||
CONFIG_DRIVER_SMC911X
|
||||
Support for SMSC's LAN911x and LAN921x chips
|
||||
|
||||
CONFIG_DRIVER_SMC911X_BASE
|
||||
Define this to hold the physical address
|
||||
of the device (I/O space)
|
||||
|
||||
CONFIG_DRIVER_SMC911X_32_BIT
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||||
Define this if data bus is 32 bits
|
||||
|
||||
CONFIG_DRIVER_SMC911X_16_BIT
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||||
Define this if data bus is 16 bits. If your processor
|
||||
automatically converts one 32 bit word to two 16 bit
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||||
words you may also try CONFIG_DRIVER_SMC911X_32_BIT.
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||||
|
||||
- USB Support:
|
||||
At the moment only the UHCI host controller is
|
||||
supported (PIP405, MIP405, MPC5200); define
|
||||
|
|
|
@ -26,8 +26,6 @@
|
|||
#include <command.h>
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||||
#include <net.h>
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||||
|
||||
#ifdef CONFIG_DRIVER_3C589
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||||
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||||
#include "3c589.h"
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||||
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||||
|
@ -514,6 +512,3 @@ int eth_send(volatile void *packet, int length) {
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|||
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||||
return length;
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||||
}
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||||
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||||
|
||||
#endif /* CONFIG_DRIVER_3C589 */
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||||
|
|
|
@ -25,45 +25,45 @@ include $(TOPDIR)/config.mk
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|||
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||||
LIB := $(obj)libnet.a
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||||
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||||
COBJS-y += 3c589.o
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||||
COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o
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||||
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
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||||
COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
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||||
COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
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||||
COBJS-y += cs8900.o
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||||
COBJS-y += dc2114x.o
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||||
COBJS-y += dm9000x.o
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||||
COBJS-y += e1000.o
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||||
COBJS-y += eepro100.o
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||||
COBJS-y += enc28j60.o
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||||
COBJS-y += fsl_mcdmafec.o
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||||
COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
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COBJS-$(CONFIG_TULIP) += dc2114x.o
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||||
COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
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||||
COBJS-$(CONFIG_E1000) += e1000.o
|
||||
COBJS-$(CONFIG_EEPRO100) += eepro100.o
|
||||
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
|
||||
COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o
|
||||
COBJS-$(CONFIG_GRETH) += greth.o
|
||||
COBJS-y += inca-ip_sw.o
|
||||
COBJS-y += ks8695eth.o
|
||||
COBJS-y += lan91c96.o
|
||||
COBJS-y += macb.o
|
||||
COBJS-y += mcffec.o
|
||||
COBJS-y += natsemi.o
|
||||
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
|
||||
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
|
||||
COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o
|
||||
COBJS-$(CONFIG_MACB) += macb.o
|
||||
COBJS-$(CONFIG_MCFFEC) += mcffec.o
|
||||
COBJS-$(CONFIG_NATSEMI) += natsemi.o
|
||||
ifeq ($(CONFIG_DRIVER_NE2000),y)
|
||||
COBJS-y += ne2000.o
|
||||
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o
|
||||
endif
|
||||
COBJS-y += netarm_eth.o
|
||||
COBJS-y += netconsole.o
|
||||
COBJS-y += ns7520_eth.o
|
||||
COBJS-y += ns8382x.o
|
||||
COBJS-y += ns9750_eth.o
|
||||
COBJS-y += pcnet.o
|
||||
COBJS-y += plb2800_eth.o
|
||||
COBJS-y += rtl8019.o
|
||||
COBJS-y += rtl8139.o
|
||||
COBJS-y += rtl8169.o
|
||||
COBJS-y += s3c4510b_eth.o
|
||||
COBJS-y += smc91111.o
|
||||
COBJS-y += smc911x.o
|
||||
COBJS-y += tigon3.o
|
||||
COBJS-y += tsec.o
|
||||
COBJS-y += tsi108_eth.o
|
||||
COBJS-y += uli526x.o
|
||||
COBJS-y += vsc7385.o
|
||||
COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
|
||||
COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
|
||||
COBJS-$(CONFIG_DRIVER_NS7520_ETHERNET) += ns7520_eth.o
|
||||
COBJS-$(CONFIG_NS8382X) += ns8382x.o
|
||||
COBJS-$(CONFIG_DRIVER_NS9750_ETHERNET) += ns9750_eth.o
|
||||
COBJS-$(CONFIG_PCNET) += pcnet.o
|
||||
COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
|
||||
COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o
|
||||
COBJS-$(CONFIG_RTL8139) += rtl8139.o
|
||||
COBJS-$(CONFIG_RTL8169) += rtl8169.o
|
||||
COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
|
||||
COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o
|
||||
COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o
|
||||
COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o
|
||||
COBJS-$(CONFIG_TSEC_ENET) += tsec.o
|
||||
COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
|
||||
COBJS-$(CONFIG_ULI526X) += uli526x.o
|
||||
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
|
||||
COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o
|
||||
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
|
||||
|
||||
|
|
|
@ -6,9 +6,6 @@
|
|||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET) \
|
||||
&& (!defined(CONFIG_NET_MULTI)) && defined(CONFIG_BCM570x)
|
||||
|
||||
#ifdef CONFIG_BMW
|
||||
#include <mpc824x.h>
|
||||
#endif
|
||||
|
@ -1599,5 +1596,3 @@ PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx)
|
|||
|
||||
return pQueue->Array[Idx];
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -41,10 +41,6 @@
|
|||
#include "cs8900.h"
|
||||
#include <net.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_CS8900
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
/* packet page register access functions */
|
||||
|
@ -315,7 +311,3 @@ int cs8900_e2prom_write(unsigned char addr, unsigned short value)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
#endif /* CONFIG_DRIVER_CS8900 */
|
||||
|
|
|
@ -19,10 +19,6 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET) \
|
||||
&& defined(CONFIG_NET_MULTI) && defined(CONFIG_TULIP)
|
||||
|
||||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <pci.h>
|
||||
|
@ -766,5 +762,3 @@ static void update_srom(struct eth_device *dev, bd_t *bis)
|
|||
}
|
||||
}
|
||||
#endif /* UPDATE_SROM */
|
||||
|
||||
#endif
|
||||
|
|
|
@ -36,7 +36,24 @@ v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
|
|||
|
||||
--------------------------------------
|
||||
|
||||
12/15/2003 Initial port to u-boot by Sascha Hauer <saschahauer@web.de>
|
||||
12/15/2003 Initial port to u-boot by
|
||||
Sascha Hauer <saschahauer@web.de>
|
||||
|
||||
06/03/2008 Remy Bohmer <linux@bohmer.net>
|
||||
- Fixed the driver to work with DM9000A.
|
||||
(check on ISR receive status bit before reading the
|
||||
FIFO as described in DM9000 programming guide and
|
||||
application notes)
|
||||
- Added autodetect of databus width.
|
||||
- Made debug code compile again.
|
||||
- Adapt eth_send such that it matches the DM9000*
|
||||
application notes. Needed to make it work properly
|
||||
for DM9000A.
|
||||
- Adapted reset procedure to match DM9000 application
|
||||
notes (i.e. double reset)
|
||||
- some minor code cleanups
|
||||
These changes are tested with DM9000{A,EP,E} together
|
||||
with a 200MHz Atmel AT91SAM92161 core
|
||||
|
||||
TODO: Homerun NIC and longrun NIC are not functional, only internal at the
|
||||
moment.
|
||||
|
@ -47,8 +64,6 @@ TODO: Homerun NIC and longrun NIC are not functional, only internal at the
|
|||
#include <net.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_DM9000
|
||||
|
||||
#include "dm9000x.h"
|
||||
|
||||
/* Board/System/Debug information/definition ---------------- */
|
||||
|
@ -59,10 +74,22 @@ TODO: Homerun NIC and longrun NIC are not functional, only internal at the
|
|||
/* #define CONFIG_DM9000_DEBUG */
|
||||
|
||||
#ifdef CONFIG_DM9000_DEBUG
|
||||
#define DM9000_DBG(fmt,args...) printf(fmt ,##args)
|
||||
#else /* */
|
||||
#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
|
||||
#define DM9000_DMP_PACKET(func,packet,length) \
|
||||
do { \
|
||||
int i; \
|
||||
printf(func ": length: %d\n", length); \
|
||||
for (i = 0; i < length; i++) { \
|
||||
if (i % 8 == 0) \
|
||||
printf("\n%s: %02x: ", func, i); \
|
||||
printf("%02x ", ((unsigned char *) packet)[i]); \
|
||||
} printf("\n"); \
|
||||
} while(0)
|
||||
#else
|
||||
#define DM9000_DBG(fmt,args...)
|
||||
#endif /* */
|
||||
#define DM9000_DMP_PACKET(func,packet,length)
|
||||
#endif
|
||||
|
||||
enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD =
|
||||
1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO =
|
||||
8, DM9000_1M_HPNA = 0x10
|
||||
|
@ -84,8 +111,11 @@ typedef struct board_info {
|
|||
u8 device_wait_reset; /* device state */
|
||||
u8 nic_type; /* NIC type */
|
||||
unsigned char srom[128];
|
||||
void (*outblk)(volatile void *data_ptr, int count);
|
||||
void (*inblk)(void *data_ptr, int count);
|
||||
void (*rx_status)(u16 *RxStatus, u16 *RxLen);
|
||||
} board_info_t;
|
||||
board_info_t dmfe_info;
|
||||
static board_info_t dm9000_info;
|
||||
|
||||
/* For module input parameter */
|
||||
static int media_mode = DM9000_AUTO;
|
||||
|
@ -124,10 +154,85 @@ dump_regs(void)
|
|||
DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
|
||||
DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
|
||||
DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
|
||||
DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR));
|
||||
DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
|
||||
DM9000_DBG("\n");
|
||||
}
|
||||
#endif /* */
|
||||
#endif
|
||||
|
||||
static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < count; i++)
|
||||
DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
|
||||
}
|
||||
|
||||
static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
|
||||
{
|
||||
int i;
|
||||
u32 tmplen = (count + 1) / 2;
|
||||
|
||||
for (i = 0; i < tmplen; i++)
|
||||
DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
|
||||
}
|
||||
static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
|
||||
{
|
||||
int i;
|
||||
u32 tmplen = (count + 3) / 4;
|
||||
|
||||
for (i = 0; i < tmplen; i++)
|
||||
DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
|
||||
}
|
||||
|
||||
static void dm9000_inblk_8bit(void *data_ptr, int count)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < count; i++)
|
||||
((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
|
||||
}
|
||||
|
||||
static void dm9000_inblk_16bit(void *data_ptr, int count)
|
||||
{
|
||||
int i;
|
||||
u32 tmplen = (count + 1) / 2;
|
||||
|
||||
for (i = 0; i < tmplen; i++)
|
||||
((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
|
||||
}
|
||||
static void dm9000_inblk_32bit(void *data_ptr, int count)
|
||||
{
|
||||
int i;
|
||||
u32 tmplen = (count + 3) / 4;
|
||||
|
||||
for (i = 0; i < tmplen; i++)
|
||||
((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
|
||||
}
|
||||
|
||||
static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
|
||||
{
|
||||
u32 tmpdata;
|
||||
|
||||
DM9000_outb(DM9000_MRCMD, DM9000_IO);
|
||||
|
||||
tmpdata = DM9000_inl(DM9000_DATA);
|
||||
*RxStatus = tmpdata;
|
||||
*RxLen = tmpdata >> 16;
|
||||
}
|
||||
|
||||
static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
|
||||
{
|
||||
DM9000_outb(DM9000_MRCMD, DM9000_IO);
|
||||
|
||||
*RxStatus = DM9000_inw(DM9000_DATA);
|
||||
*RxLen = DM9000_inw(DM9000_DATA);
|
||||
}
|
||||
|
||||
static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
|
||||
{
|
||||
DM9000_outb(DM9000_MRCMD, DM9000_IO);
|
||||
|
||||
*RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
|
||||
*RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
|
||||
}
|
||||
|
||||
/*
|
||||
Search DM9000 board, allocate space and register it
|
||||
|
@ -236,7 +341,7 @@ program_dm9802(void)
|
|||
static void
|
||||
identify_nic(void)
|
||||
{
|
||||
struct board_info *db = &dmfe_info; /* Point a board information structure */
|
||||
struct board_info *db = &dm9000_info;
|
||||
u16 phy_reg3;
|
||||
DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
|
||||
phy_reg3 = phy_read(3);
|
||||
|
@ -263,9 +368,35 @@ identify_nic(void)
|
|||
static void
|
||||
dm9000_reset(void)
|
||||
{
|
||||
DM9000_DBG("resetting\n");
|
||||
DM9000_iow(DM9000_NCR, NCR_RST);
|
||||
udelay(1000); /* delay 1ms */
|
||||
DM9000_DBG("resetting DM9000\n");
|
||||
|
||||
/* Reset DM9000,
|
||||
see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
|
||||
|
||||
/* DEBUG: Make all GPIO pins outputs */
|
||||
DM9000_iow(DM9000_GPCR, 0x0F);
|
||||
/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
|
||||
DM9000_iow(DM9000_GPR, 0);
|
||||
/* Step 2: Software reset */
|
||||
DM9000_iow(DM9000_NCR, 3);
|
||||
|
||||
do {
|
||||
DM9000_DBG("resetting the DM9000, 1st reset\n");
|
||||
udelay(25); /* Wait at least 20 us */
|
||||
} while (DM9000_ior(DM9000_NCR) & 1);
|
||||
|
||||
DM9000_iow(DM9000_NCR, 0);
|
||||
DM9000_iow(DM9000_NCR, 3); /* Issue a second reset */
|
||||
|
||||
do {
|
||||
DM9000_DBG("resetting the DM9000, 2nd reset\n");
|
||||
udelay(25); /* Wait at least 20 us */
|
||||
} while (DM9000_ior(DM9000_NCR) & 1);
|
||||
|
||||
/* Check whether the ethernet controller is present */
|
||||
if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
|
||||
(DM9000_ior(DM9000_PIDH) != 0x90))
|
||||
printf("ERROR: resetting DM9000 -> not responding\n");
|
||||
}
|
||||
|
||||
/* Initilize dm9000 board
|
||||
|
@ -274,12 +405,46 @@ int
|
|||
eth_init(bd_t * bd)
|
||||
{
|
||||
int i, oft, lnk;
|
||||
u8 io_mode;
|
||||
struct board_info *db = &dm9000_info;
|
||||
|
||||
DM9000_DBG("eth_init()\n");
|
||||
|
||||
/* RESET device */
|
||||
dm9000_reset();
|
||||
dm9000_probe();
|
||||
|
||||
/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
|
||||
io_mode = DM9000_ior(DM9000_ISR) >> 6;
|
||||
|
||||
switch (io_mode) {
|
||||
case 0x0: /* 16-bit mode */
|
||||
printf("DM9000: running in 16 bit mode\n");
|
||||
db->outblk = dm9000_outblk_16bit;
|
||||
db->inblk = dm9000_inblk_16bit;
|
||||
db->rx_status = dm9000_rx_status_16bit;
|
||||
break;
|
||||
case 0x01: /* 32-bit mode */
|
||||
printf("DM9000: running in 32 bit mode\n");
|
||||
db->outblk = dm9000_outblk_32bit;
|
||||
db->inblk = dm9000_inblk_32bit;
|
||||
db->rx_status = dm9000_rx_status_32bit;
|
||||
break;
|
||||
case 0x02: /* 8 bit mode */
|
||||
printf("DM9000: running in 8 bit mode\n");
|
||||
db->outblk = dm9000_outblk_8bit;
|
||||
db->inblk = dm9000_inblk_8bit;
|
||||
db->rx_status = dm9000_rx_status_8bit;
|
||||
break;
|
||||
default:
|
||||
/* Assume 8 bit mode, will probably not work anyway */
|
||||
printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
|
||||
db->outblk = dm9000_outblk_8bit;
|
||||
db->inblk = dm9000_inblk_8bit;
|
||||
db->rx_status = dm9000_rx_status_8bit;
|
||||
break;
|
||||
}
|
||||
|
||||
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
|
||||
identify_nic();
|
||||
|
||||
|
@ -289,15 +454,22 @@ eth_init(bd_t * bd)
|
|||
/* Set PHY */
|
||||
set_PHY_mode();
|
||||
|
||||
/* Program operating register */
|
||||
DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
|
||||
DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
|
||||
DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
|
||||
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
|
||||
DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
|
||||
DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
|
||||
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
|
||||
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
|
||||
/* Program operating register, only intern phy supported by now */
|
||||
DM9000_iow(DM9000_NCR, 0x0);
|
||||
/* TX Polling clear */
|
||||
DM9000_iow(DM9000_TCR, 0);
|
||||
/* Less 3Kb, 200us */
|
||||
DM9000_iow(DM9000_BPTR, 0x3f);
|
||||
/* Flow Control : High/Low Water */
|
||||
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
|
||||
/* SH FIXME: This looks strange! Flow Control */
|
||||
DM9000_iow(DM9000_FCR, 0x0);
|
||||
/* Special Mode */
|
||||
DM9000_iow(DM9000_SMCR, 0);
|
||||
/* clear TX status */
|
||||
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
|
||||
/* Clear interrupt status */
|
||||
DM9000_iow(DM9000_ISR, 0x0f);
|
||||
|
||||
/* Set Node address */
|
||||
#ifndef CONFIG_AT91SAM9261EK
|
||||
|
@ -333,8 +505,11 @@ eth_init(bd_t * bd)
|
|||
DM9000_DBG("\n");
|
||||
|
||||
/* Activate DM9000 */
|
||||
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
|
||||
DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
|
||||
/* RX enable */
|
||||
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
|
||||
/* Enable TX/RX interrupt mask */
|
||||
DM9000_iow(DM9000_IMR, IMR_PAR);
|
||||
|
||||
i = 0;
|
||||
while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
|
||||
udelay(1000);
|
||||
|
@ -376,54 +551,37 @@ eth_init(bd_t * bd)
|
|||
int
|
||||
eth_send(volatile void *packet, int length)
|
||||
{
|
||||
char *data_ptr;
|
||||
u32 tmplen, i;
|
||||
int tmo;
|
||||
DM9000_DBG("eth_send: length: %d\n", length);
|
||||
for (i = 0; i < length; i++) {
|
||||
if (i % 8 == 0)
|
||||
DM9000_DBG("\nSend: 02x: ", i);
|
||||
DM9000_DBG("%02x ", ((unsigned char *) packet)[i]);
|
||||
} DM9000_DBG("\n");
|
||||
struct board_info *db = &dm9000_info;
|
||||
|
||||
DM9000_DMP_PACKET("eth_send", packet, length);
|
||||
|
||||
DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
|
||||
|
||||
/* Move data to DM9000 TX RAM */
|
||||
data_ptr = (char *) packet;
|
||||
DM9000_outb(DM9000_MWCMD, DM9000_IO);
|
||||
DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
|
||||
|
||||
#ifdef CONFIG_DM9000_USE_8BIT
|
||||
/* Byte mode */
|
||||
for (i = 0; i < length; i++)
|
||||
DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_16BIT
|
||||
tmplen = (length + 1) / 2;
|
||||
for (i = 0; i < tmplen; i++)
|
||||
DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_32BIT
|
||||
tmplen = (length + 3) / 4;
|
||||
for (i = 0; i < tmplen; i++)
|
||||
DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
/* push the data to the TX-fifo */
|
||||
(db->outblk)(packet, length);
|
||||
|
||||
/* Set TX length to DM9000 */
|
||||
DM9000_iow(DM9000_TXPLL, length & 0xff);
|
||||
DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
|
||||
|
||||
/* Issue TX polling command */
|
||||
DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
|
||||
DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
|
||||
|
||||
/* wait for end of transmission */
|
||||
tmo = get_timer(0) + 5 * CFG_HZ;
|
||||
while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) {
|
||||
while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
|
||||
!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
|
||||
if (get_timer(0) >= tmo) {
|
||||
printf("transmission timeout\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
|
||||
|
||||
DM9000_DBG("transmit done\n\n");
|
||||
return 0;
|
||||
}
|
||||
|
@ -452,86 +610,67 @@ eth_rx(void)
|
|||
{
|
||||
u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
|
||||
u16 RxStatus, RxLen = 0;
|
||||
u32 tmplen, i;
|
||||
#ifdef CONFIG_DM9000_USE_32BIT
|
||||
u32 tmpdata;
|
||||
#endif
|
||||
struct board_info *db = &dm9000_info;
|
||||
|
||||
/* Check packet ready or not */
|
||||
DM9000_ior(DM9000_MRCMDX); /* Dummy read */
|
||||
rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */
|
||||
if (rxbyte == 0)
|
||||
/* Check packet ready or not, we must check
|
||||
the ISR status first for DM9000A */
|
||||
if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
|
||||
return 0;
|
||||
|
||||
/* Status check: this byte must be 0 or 1 */
|
||||
if (rxbyte > 1) {
|
||||
DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
|
||||
DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
|
||||
DM9000_DBG("rx status check: %d\n", rxbyte);
|
||||
}
|
||||
DM9000_DBG("receiving packet\n");
|
||||
DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
|
||||
|
||||
/* A packet ready now & Get status/length */
|
||||
DM9000_outb(DM9000_MRCMD, DM9000_IO);
|
||||
/* There is _at least_ 1 package in the fifo, read them all */
|
||||
for (;;) {
|
||||
DM9000_ior(DM9000_MRCMDX); /* Dummy read */
|
||||
|
||||
#ifdef CONFIG_DM9000_USE_8BIT
|
||||
RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
|
||||
RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
|
||||
/* Get most updated data,
|
||||
only look at bits 0:1, See application notes DM9000 */
|
||||
rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_16BIT
|
||||
RxStatus = DM9000_inw(DM9000_DATA);
|
||||
RxLen = DM9000_inw(DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_32BIT
|
||||
tmpdata = DM9000_inl(DM9000_DATA);
|
||||
RxStatus = tmpdata;
|
||||
RxLen = tmpdata >> 16;
|
||||
|
||||
#endif /* */
|
||||
DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
|
||||
|
||||
/* Move data from DM9000 */
|
||||
/* Read received packet from RX SRAM */
|
||||
#ifdef CONFIG_DM9000_USE_8BIT
|
||||
for (i = 0; i < RxLen; i++)
|
||||
rdptr[i] = DM9000_inb(DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_16BIT
|
||||
tmplen = (RxLen + 1) / 2;
|
||||
for (i = 0; i < tmplen; i++)
|
||||
((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_32BIT
|
||||
tmplen = (RxLen + 3) / 4;
|
||||
for (i = 0; i < tmplen; i++)
|
||||
((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
if ((RxStatus & 0xbf00) || (RxLen < 0x40)
|
||||
|| (RxLen > DM9000_PKT_MAX)) {
|
||||
if (RxStatus & 0x100) {
|
||||
printf("rx fifo error\n");
|
||||
/* Status check: this byte must be 0 or 1 */
|
||||
if (rxbyte > DM9000_PKT_RDY) {
|
||||
DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
|
||||
DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
|
||||
printf("DM9000 error: status check fail: 0x%x\n",
|
||||
rxbyte);
|
||||
return 0;
|
||||
}
|
||||
if (RxStatus & 0x200) {
|
||||
printf("rx crc error\n");
|
||||
}
|
||||
if (RxStatus & 0x8000) {
|
||||
printf("rx length error\n");
|
||||
}
|
||||
if (RxLen > DM9000_PKT_MAX) {
|
||||
printf("rx length too big\n");
|
||||
dm9000_reset();
|
||||
}
|
||||
} else {
|
||||
|
||||
/* Pass to upper layer */
|
||||
DM9000_DBG("passing packet to upper layer\n");
|
||||
NetReceive(NetRxPackets[0], RxLen);
|
||||
return RxLen;
|
||||
if (rxbyte != DM9000_PKT_RDY)
|
||||
return 0; /* No packet received, ignore */
|
||||
|
||||
DM9000_DBG("receiving packet\n");
|
||||
|
||||
/* A packet ready now & Get status/length */
|
||||
(db->rx_status)(&RxStatus, &RxLen);
|
||||
|
||||
DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
|
||||
|
||||
/* Move data from DM9000 */
|
||||
/* Read received packet from RX SRAM */
|
||||
(db->inblk)(rdptr, RxLen);
|
||||
|
||||
if ((RxStatus & 0xbf00) || (RxLen < 0x40)
|
||||
|| (RxLen > DM9000_PKT_MAX)) {
|
||||
if (RxStatus & 0x100) {
|
||||
printf("rx fifo error\n");
|
||||
}
|
||||
if (RxStatus & 0x200) {
|
||||
printf("rx crc error\n");
|
||||
}
|
||||
if (RxStatus & 0x8000) {
|
||||
printf("rx length error\n");
|
||||
}
|
||||
if (RxLen > DM9000_PKT_MAX) {
|
||||
printf("rx length too big\n");
|
||||
dm9000_reset();
|
||||
}
|
||||
} else {
|
||||
DM9000_DMP_PACKET("eth_rx", rdptr, RxLen);
|
||||
|
||||
DM9000_DBG("passing packet to upper layer\n");
|
||||
NetReceive(NetRxPackets[0], RxLen);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
@ -592,12 +731,12 @@ phy_read(int reg)
|
|||
/* Fill the phyxcer register into REG_0C */
|
||||
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
|
||||
DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
|
||||
udelay(100); /* Wait read complete */
|
||||
udelay(100); /* Wait read complete */
|
||||
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
|
||||
val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
|
||||
|
||||
/* The read data keeps on REG_0D & REG_0E */
|
||||
DM9000_DBG("phy_read(%d): %d\n", reg, val);
|
||||
DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
|
@ -615,8 +754,7 @@ phy_write(int reg, u16 value)
|
|||
DM9000_iow(DM9000_EPDRL, (value & 0xff));
|
||||
DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
|
||||
DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
|
||||
udelay(500); /* Wait write complete */
|
||||
udelay(500); /* Wait write complete */
|
||||
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
|
||||
DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value);
|
||||
DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
|
||||
}
|
||||
#endif /* CONFIG_DRIVER_DM9000 */
|
||||
|
|
|
@ -44,9 +44,6 @@ tested on both gig copper and gig fiber boards
|
|||
|
||||
#include "e1000.h"
|
||||
|
||||
#if defined(CONFIG_CMD_NET) \
|
||||
&& defined(CONFIG_NET_MULTI) && defined(CONFIG_E1000)
|
||||
|
||||
#define TOUT_LOOP 100000
|
||||
|
||||
#undef virt_to_bus
|
||||
|
@ -83,6 +80,7 @@ static struct pci_device_id supported[] = {
|
|||
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
|
||||
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
|
||||
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
|
||||
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
|
||||
};
|
||||
|
||||
/* Function forward declarations */
|
||||
|
@ -646,6 +644,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
|
|||
hw->mac_type = e1000_82546;
|
||||
break;
|
||||
case E1000_DEV_ID_82541ER:
|
||||
case E1000_DEV_ID_82541GI_LF:
|
||||
hw->mac_type = e1000_82541_rev_2;
|
||||
break;
|
||||
default:
|
||||
|
@ -3059,5 +3058,3 @@ e1000_initialize(bd_t * bis)
|
|||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -222,7 +222,8 @@ struct e1000_phy_stats {
|
|||
#define E1000_DEV_ID_82546EB_COPPER 0x1010
|
||||
#define E1000_DEV_ID_82546EB_FIBER 0x1012
|
||||
#define E1000_DEV_ID_82541ER 0x1078
|
||||
#define NUM_DEV_IDS 14
|
||||
#define E1000_DEV_ID_82541GI_LF 0x107C
|
||||
#define NUM_DEV_IDS 15
|
||||
|
||||
#define NODE_ADDRESS_SIZE 6
|
||||
#define ETH_LENGTH_OF_ADDRESS 6
|
||||
|
|
|
@ -30,9 +30,6 @@
|
|||
|
||||
#undef DEBUG
|
||||
|
||||
#if defined(CONFIG_CMD_NET) \
|
||||
&& defined(CONFIG_NET_MULTI) && defined(CONFIG_EEPRO100)
|
||||
|
||||
/* Ethernet chip registers.
|
||||
*/
|
||||
#define SCBStatus 0 /* Rx/Command Unit Status *Word* */
|
||||
|
@ -944,5 +941,3 @@ static void read_hw_addr (struct eth_device *dev, bd_t * bis)
|
|||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -17,7 +17,6 @@
|
|||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#ifdef CONFIG_ENC28J60
|
||||
#include <net.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/spi.h>
|
||||
|
@ -979,5 +978,3 @@ static void phyWrite(unsigned char addr, unsigned short data)
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ENC28J60 */
|
||||
|
|
|
@ -31,7 +31,6 @@
|
|||
#include <net.h>
|
||||
#include <miiphy.h>
|
||||
|
||||
#ifdef CONFIG_FSLDMAFEC
|
||||
#undef ET_DEBUG
|
||||
#undef MII_DEBUG
|
||||
|
||||
|
@ -49,7 +48,6 @@
|
|||
#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
|
||||
BD_ENET_RX_OV | BD_ENET_RX_TR)
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#include <asm/immap.h>
|
||||
#include <asm/fsl_mcdmafec.h>
|
||||
|
||||
|
@ -586,6 +584,3 @@ int mcdmafec_initialize(bd_t * bis)
|
|||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET && CONFIG_NET_MULTI */
|
||||
#endif /* CONFIG_FSLDMAFEC */
|
||||
|
|
|
@ -26,9 +26,6 @@
|
|||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET) \
|
||||
&& defined(CONFIG_NET_MULTI) && defined(CONFIG_INCA_IP_SWITCH)
|
||||
|
||||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <asm/inca-ip.h>
|
||||
|
@ -813,5 +810,3 @@ Fail:
|
|||
return -1;
|
||||
}
|
||||
#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */
|
||||
|
||||
#endif
|
||||
|
|
|
@ -21,8 +21,6 @@
|
|||
/****************************************************************************/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_KS8695ETH
|
||||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <asm/io.h>
|
||||
|
@ -234,5 +232,3 @@ int eth_send(volatile void *packet, int len)
|
|||
|
||||
return len;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_DRIVER_KS8695ETH */
|
||||
|
|
|
@ -63,10 +63,6 @@
|
|||
#include "lan91c96.h"
|
||||
#include <net.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_LAN91C96
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
|
||||
/*------------------------------------------------------------------------
|
||||
*
|
||||
* Configuration options, for the experienced user to change.
|
||||
|
@ -865,9 +861,6 @@ static int smc_hw_init ()
|
|||
}
|
||||
#endif /* 0 */
|
||||
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
|
||||
/* smc_get_ethaddr (bd_t * bd)
|
||||
*
|
||||
* This checks both the environment and the ROM for an ethernet address. If
|
||||
|
@ -963,5 +956,3 @@ int get_rom_mac (unsigned char *v_rom_mac)
|
|||
return (1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_DRIVER_LAN91C96 */
|
||||
|
|
|
@ -17,9 +17,6 @@
|
|||
*/
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_MACB) \
|
||||
&& (defined(CONFIG_CMD_NET) || defined(CONFIG_CMD_MII))
|
||||
|
||||
/*
|
||||
* The u-boot networking stack is a little weird. It seems like the
|
||||
* networking core allocates receive buffers up front without any
|
||||
|
@ -593,5 +590,3 @@ int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
|
|||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_MACB */
|
||||
|
|
|
@ -27,8 +27,6 @@
|
|||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
|
||||
#ifdef CONFIG_MCFFEC
|
||||
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
|
@ -51,8 +49,6 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
|
||||
struct fec_info_s fec_info[] = {
|
||||
#ifdef CFG_FEC0_IOBASE
|
||||
{
|
||||
|
@ -125,11 +121,17 @@ void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
|
|||
}
|
||||
|
||||
if ((dup_spd & 0xFFFF) == _100BASET) {
|
||||
#ifdef CONFIG_MCF5445x
|
||||
fecp->rcr &= ~0x200; /* disabled 10T base */
|
||||
#endif
|
||||
#ifdef MII_DEBUG
|
||||
printf("100Mbps\n");
|
||||
#endif
|
||||
bd->bi_ethspeed = 100;
|
||||
} else {
|
||||
#ifdef CONFIG_MCF5445x
|
||||
fecp->rcr |= 0x200; /* enabled 10T base */
|
||||
#endif
|
||||
#ifdef MII_DEBUG
|
||||
printf("10Mbps\n");
|
||||
#endif
|
||||
|
@ -599,6 +601,3 @@ int mcffec_initialize(bd_t * bis)
|
|||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
#endif /* CONFIG_MCFFEC */
|
||||
|
|
|
@ -56,9 +56,6 @@
|
|||
#include <asm/io.h>
|
||||
#include <pci.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET) \
|
||||
&& defined(CONFIG_NET_MULTI) && defined(CONFIG_NATSEMI)
|
||||
|
||||
/* defines */
|
||||
#define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
|
||||
|
||||
|
@ -878,5 +875,3 @@ natsemi_disable(struct eth_device *dev)
|
|||
/* Restore PME enable bit */
|
||||
OUTL(dev, SavedClkRun, ClkRun);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -22,15 +22,11 @@
|
|||
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_NETARMETH
|
||||
#include <command.h>
|
||||
#include <net.h>
|
||||
#include "netarm_eth.h"
|
||||
#include <asm/arch/netarm_registers.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
|
||||
static int na_mii_poll_busy (void);
|
||||
|
||||
static void na_get_mac_addr (void)
|
||||
|
@ -352,7 +348,3 @@ extern int eth_send (volatile void *packet, int length)
|
|||
printf ("eth_send timeout\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
#endif /* CONFIG_DRIVER_NETARMETH */
|
||||
|
|
|
@ -22,9 +22,6 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_NETCONSOLE
|
||||
|
||||
#include <command.h>
|
||||
#include <devices.h>
|
||||
#include <net.h>
|
||||
|
@ -263,5 +260,3 @@ int drv_nc_init (void)
|
|||
|
||||
return (rc == 0) ? 1 : rc;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_NETCONSOLE */
|
||||
|
|
|
@ -15,8 +15,6 @@
|
|||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
|
||||
|
||||
#include <net.h> /* NetSendPacket */
|
||||
#include <asm/arch/netarm_registers.h>
|
||||
#include <asm/arch/netarm_dma_module.h>
|
||||
|
@ -846,14 +844,11 @@ extern int ns7520_miiphy_write(char *devname, unsigned char const addr,
|
|||
return (ret);
|
||||
}
|
||||
#endif /* defined(CONFIG_MII) */
|
||||
#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
|
||||
|
||||
int ns7520_miiphy_initialize(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
|
||||
#if defined(CONFIG_MII)
|
||||
miiphy_register("ns7520phy", ns7520_miiphy_read, ns7520_miiphy_write);
|
||||
#endif
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -56,9 +56,6 @@
|
|||
#include <asm/io.h>
|
||||
#include <pci.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET) \
|
||||
&& defined(CONFIG_NET_MULTI) && defined(CONFIG_NS8382X)
|
||||
|
||||
/* defines */
|
||||
#define DSIZE 0x00000FFF
|
||||
#define ETH_ALEN 6
|
||||
|
@ -859,5 +856,3 @@ ns8382x_disable(struct eth_device *dev)
|
|||
/* Restore PME enable bit */
|
||||
OUTL(dev, SavedClkRun, ClkRun);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -37,8 +37,6 @@
|
|||
|
||||
#include "ns9750_eth.h" /* for Ethernet and PHY */
|
||||
|
||||
#ifdef CONFIG_DRIVER_NS9750_ETHERNET
|
||||
|
||||
/* some definition to make transistion to linux easier */
|
||||
|
||||
#define NS9750_DRIVER_NAME "eth"
|
||||
|
@ -793,5 +791,3 @@ static unsigned int ns9750_mii_poll_busy (void)
|
|||
|
||||
return unTimeout;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_DRIVER_NS9750_ETHERNET */
|
||||
|
|
|
@ -45,9 +45,6 @@
|
|||
#define PCNET_DEBUG2(fmt,args...)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_NET) \
|
||||
&& defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET)
|
||||
|
||||
#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
|
||||
#error "Macro for PCnet chip version is not defined!"
|
||||
#endif
|
||||
|
@ -537,4 +534,3 @@ static void pcnet_halt (struct eth_device *dev)
|
|||
printf ("%s: TIMEOUT: controller reset failed\n", dev->name);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -24,10 +24,6 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET) \
|
||||
&& defined(CONFIG_NET_MULTI) && defined(CONFIG_PLB2800_ETHER)
|
||||
|
||||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
@ -392,5 +388,3 @@ static unsigned char * plb2800_get_mac_addr(void)
|
|||
|
||||
return addr;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PLB2800_ETHER */
|
||||
|
|
|
@ -32,10 +32,6 @@
|
|||
#include "rtl8019.h"
|
||||
#include <net.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_RTL8019
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
|
||||
/* packet page register access functions */
|
||||
|
||||
static unsigned char get_reg (unsigned int regno)
|
||||
|
@ -271,7 +267,3 @@ extern int eth_send (volatile void *packet, int length)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
#endif /* CONFIG_DRIVER_RTL8019 */
|
||||
|
|
|
@ -77,9 +77,6 @@
|
|||
#include <asm/io.h>
|
||||
#include <pci.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
|
||||
defined(CONFIG_RTL8139)
|
||||
|
||||
#define RTL_TIMEOUT 100000
|
||||
|
||||
#define ETH_FRAME_LEN 1514
|
||||
|
@ -545,4 +542,3 @@ static void rtl_disable(struct eth_device *dev)
|
|||
udelay (100); /* wait 100us */
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -58,9 +58,6 @@
|
|||
#include <asm/io.h>
|
||||
#include <pci.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
|
||||
defined(CONFIG_RTL8169)
|
||||
|
||||
#undef DEBUG_RTL8169
|
||||
#undef DEBUG_RTL8169_TX
|
||||
#undef DEBUG_RTL8169_RX
|
||||
|
@ -887,5 +884,3 @@ int rtl8169_initialize(bd_t *bis)
|
|||
}
|
||||
return card_number;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -25,9 +25,6 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_S3C4510_ETH
|
||||
|
||||
#include <command.h>
|
||||
#include <net.h>
|
||||
#include <asm/hardware.h>
|
||||
|
@ -242,5 +239,3 @@ void eth_halt(void)
|
|||
/* disable MAC */
|
||||
PUT_REG( REG_MACCON, ETH_HaltReg);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -65,8 +65,6 @@
|
|||
#include "smc91111.h"
|
||||
#include <net.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_SMC91111
|
||||
|
||||
/* Use power-down feature of the chip */
|
||||
#define POWER_DOWN 0
|
||||
|
||||
|
@ -1620,4 +1618,3 @@ int get_rom_mac (uchar *v_rom_mac)
|
|||
return (valid_mac ? 1 : 0);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_DRIVER_SMC91111 */
|
||||
|
|
|
@ -23,13 +23,16 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_SMC911X
|
||||
|
||||
#include <command.h>
|
||||
#include <net.h>
|
||||
#include <miiphy.h>
|
||||
|
||||
#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \
|
||||
defined (CONFIG_DRIVER_SMC911X_16_BIT)
|
||||
#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \
|
||||
CONFIG_DRIVER_SMC911X_16_BIT shall be set"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DRIVER_SMC911X_32_BIT
|
||||
static inline u32 reg_read(u32 addr)
|
||||
{
|
||||
|
@ -39,9 +42,20 @@ static inline void reg_write(u32 addr, u32 val)
|
|||
{
|
||||
*(volatile u32*)addr = val;
|
||||
}
|
||||
#elif CONFIG_DRIVER_SMC911X_16_BIT
|
||||
static inline u32 reg_read(u32 addr)
|
||||
{
|
||||
volatile u16 *addr_16 = (u16 *)addr;
|
||||
return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
|
||||
}
|
||||
static inline void reg_write(u32 addr, u32 val)
|
||||
{
|
||||
*(volatile u16*)addr = (u16)val;
|
||||
*(volatile u16*)(addr + 2) = (u16)(val >> 16);
|
||||
}
|
||||
#else
|
||||
#error "SMC911X: Only 32-bit bus is supported"
|
||||
#endif
|
||||
#error "SMC911X: undefined bus width"
|
||||
#endif /* CONFIG_DRIVER_SMC911X_16_BIT */
|
||||
|
||||
#define mdelay(n) udelay((n)*1000)
|
||||
|
||||
|
@ -682,5 +696,3 @@ int eth_rx(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_DRIVER_SMC911X */
|
||||
|
|
|
@ -12,8 +12,7 @@
|
|||
/******************************************************************************/
|
||||
#include <common.h>
|
||||
#include <asm/types.h>
|
||||
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_MULTI) && \
|
||||
defined(CONFIG_TIGON3)
|
||||
|
||||
#ifdef CONFIG_BMW
|
||||
#include <mpc824x.h>
|
||||
#endif
|
||||
|
@ -5695,5 +5694,3 @@ LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
|
|||
}
|
||||
return LM_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -17,7 +17,6 @@
|
|||
#include <net.h>
|
||||
#include <command.h>
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#include "tsec.h"
|
||||
#include "miiphy.h"
|
||||
|
||||
|
@ -1128,6 +1127,36 @@ struct phy_info phy_info_M88E1111S = {
|
|||
},
|
||||
};
|
||||
|
||||
struct phy_info phy_info_M88E1118 = {
|
||||
0x01410e1,
|
||||
"Marvell 88E1118",
|
||||
4,
|
||||
(struct phy_cmd[]){ /* config */
|
||||
/* Reset and configure the PHY */
|
||||
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
||||
{0x16, 0x0002, NULL}, /* Change Page Number */
|
||||
{0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
|
||||
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
|
||||
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
|
||||
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
||||
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
|
||||
{miim_end,}
|
||||
},
|
||||
(struct phy_cmd[]){ /* startup */
|
||||
{0x16, 0x0000, NULL}, /* Change Page Number */
|
||||
/* Status is read once to clear old link state */
|
||||
{MIIM_STATUS, miim_read, NULL},
|
||||
/* Auto-negotiate */
|
||||
/* Read the status */
|
||||
{MIIM_88E1011_PHY_STATUS, miim_read,
|
||||
&mii_parse_88E1011_psr},
|
||||
{miim_end,}
|
||||
},
|
||||
(struct phy_cmd[]){ /* shutdown */
|
||||
{miim_end,}
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
|
||||
{
|
||||
uint mii_data = read_phy_reg(priv, mii_reg);
|
||||
|
@ -1492,6 +1521,7 @@ struct phy_info *phy_info[] = {
|
|||
&phy_info_BCM5464S,
|
||||
&phy_info_M88E1011S,
|
||||
&phy_info_M88E1111S,
|
||||
&phy_info_M88E1118,
|
||||
&phy_info_M88E1145,
|
||||
&phy_info_M88E1149S,
|
||||
&phy_info_dm9161,
|
||||
|
@ -1710,5 +1740,3 @@ tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
|
|||
return 0;
|
||||
}
|
||||
#endif /* Multicast TFTP ? */
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
|
|
@ -27,9 +27,6 @@
|
|||
|
||||
#include <config.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) \
|
||||
&& defined(CONFIG_TSI108_ETH)
|
||||
|
||||
#if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2)
|
||||
#error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2"
|
||||
#endif
|
||||
|
@ -1032,5 +1029,3 @@ static void tsi108_eth_halt (struct eth_device *dev)
|
|||
/* Put MAC into reset state. */
|
||||
reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -22,9 +22,6 @@
|
|||
|
||||
/* some kernel function compatible define */
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
|
||||
defined(CONFIG_ULI526X)
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
/* Board/System/Debug information/definition */
|
||||
|
@ -993,4 +990,3 @@ static void set_mac_addr(struct eth_device *dev)
|
|||
udelay(10);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -13,9 +13,6 @@
|
|||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#ifdef CONFIG_VSC7385_ENET
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
|
@ -97,5 +94,3 @@ int vsc7385_upload_firmware(void *firmware, unsigned int size)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -256,14 +256,10 @@
|
|||
#define CFG_CS5U_VAL 0x00008400
|
||||
#define CFG_CS5L_VAL 0x00000D03
|
||||
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DM9000_BASE 0x16000000
|
||||
#define DM9000_IO CONFIG_DM9000_BASE
|
||||
#define DM9000_DATA (CONFIG_DM9000_BASE+4)
|
||||
/* #define CONFIG_DM9000_USE_8BIT */
|
||||
#define CONFIG_DM9000_USE_16BIT
|
||||
/* #define CONFIG_DM9000_USE_32BIT */
|
||||
|
||||
/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
|
||||
f_ref=16,777MHz
|
||||
|
|
|
@ -275,14 +275,10 @@
|
|||
#define CFG_MCIO0_VAL 0x00008407
|
||||
#define CFG_MCIO1_VAL 0x0000c108
|
||||
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DM9000_BASE 0x08000000
|
||||
#define DM9000_IO CONFIG_DM9000_BASE
|
||||
#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
|
||||
/* #define CONFIG_DM9000_USE_8BIT */
|
||||
/* #define CONFIG_DM9000_USE_16BIT */
|
||||
#define CONFIG_DM9000_USE_32BIT
|
||||
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define CFG_USB_OHCI_BOARD_INIT 1
|
||||
|
|
|
@ -1812,7 +1812,8 @@
|
|||
#define PCI_DEVICE_ID_INTEL_82434 0x04a3
|
||||
#define PCI_DEVICE_ID_INTEL_I960 0x0960
|
||||
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
|
||||
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
|
||||
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
|
||||
#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
|
||||
#define PCI_DEVICE_ID_INTEL_82542 0x1000
|
||||
#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001
|
||||
#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004
|
||||
|
|
|
@ -1407,6 +1407,10 @@ NetReceive(volatile uchar * inpkt, int len)
|
|||
if (ip->ip_off & htons(0x1fff)) { /* Can't deal w/ fragments */
|
||||
return;
|
||||
}
|
||||
/* can't deal with headers > 20 bytes */
|
||||
if ((ip->ip_hl_v & 0x0f) > 0x05) {
|
||||
return;
|
||||
}
|
||||
if (!NetCksumOk((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2)) {
|
||||
puts ("checksum bad\n");
|
||||
return;
|
||||
|
|
Loading…
Reference in a new issue