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Update Freescale 85xx boards to sys_eeprom.c
The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID format, and so it obsoletes board/freescale/common/cds_eeprom.c. Freescale 86xx boards already use sys_eeprom.c, so this patch migrates the remaining Freescale 85xx boards to use it as well. cds_eeprom.c is deleted. Signed-off-by: Timur Tabi <timur@freescale.com>
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aab2bf0202
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5 changed files with 22 additions and 67 deletions
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@ -30,7 +30,6 @@ endif
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LIB = $(obj)lib$(VENDOR).a
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COBJS-${CONFIG_FSL_CADMUS} += cadmus.o
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COBJS-${CONFIG_FSL_CDS_EEPROM} += cds_eeprom.o
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COBJS-${CONFIG_FSL_VIA} += cds_via.o
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COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
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COBJS-${CONFIG_FSL_PIXIS} += pixis.o
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@ -1,60 +0,0 @@
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/*
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* Copyright 2004 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include "eeprom.h"
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typedef struct {
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char idee_pcbid[4]; /* "CCID" for CDC v1.X */
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u8 idee_major;
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u8 idee_minor;
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char idee_serial[10];
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char idee_errata[2];
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char idee_date[8]; /* yyyymmdd */
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/* The rest of the EEPROM space is reserved */
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} id_eeprom_t;
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unsigned int
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get_cpu_board_revision(void)
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{
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uint major = 0;
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uint minor = 0;
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id_eeprom_t id_eeprom;
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i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
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(uchar *) &id_eeprom, sizeof(id_eeprom));
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major = id_eeprom.idee_major;
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minor = id_eeprom.idee_minor;
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if (major == 0xff && minor == 0xff) {
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major = minor = 0;
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}
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return MPC85XX_CPU_BOARD_REV(major,minor);
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}
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@ -44,7 +44,6 @@
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#define CONFIG_FSL_CDS_EEPROM
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@ -328,11 +327,17 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CFG_I2C_EEPROM_CCID
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#define CFG_ID_EEPROM
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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@ -50,7 +50,6 @@
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#define CONFIG_FSL_CDS_EEPROM
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@ -352,11 +351,17 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CFG_I2C_EEPROM_CCID
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#define CFG_ID_EEPROM
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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@ -43,7 +43,7 @@
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#define CONFIG_FSL_CDS_EEPROM
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@ -325,11 +325,17 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CFG_I2C_EEPROM_CCID
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#define CFG_ID_EEPROM
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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/*
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* General PCI
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* Addresses are mapped 1-1.
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