mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
ppc4xx: Change Kilauea to use the common DDR2 init function
This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
17ceb069b8
commit
ec724f883e
8 changed files with 29 additions and 271 deletions
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@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o cmd_pll.o memory.o
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SOBJS = init.o
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COBJS = $(BOARD).o cmd_pll.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -1,167 +0,0 @@
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/*
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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*
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* (C) Copyright 2007-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Originally based on code provided from UDTech and AMCC
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#define mtsdram_as(reg, value) \
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addi r4,0,reg ; \
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mtdcr memcfga,r4 ; \
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addis r4,0,value@h ; \
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ori r4,r4,value@l ; \
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mtdcr memcfgd,r4 ;
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#if defined(CONFIG_DDR_ECC)
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.extern ecc_init
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#endif /* defined(CONFIG_DDR_ECC) */
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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#if !defined(CFG_INIT_DCACHE_CS)
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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/*
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* DDR2 SDRAM Controller Setup
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*/
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/* Set Memory Bank Configuration Registers */
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mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
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mtsdram_as(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
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mtsdram_as(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
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mtsdram_as(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
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/* Set Memory Clock Timing Register */
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mtsdram_as(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
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/* Set Refresh Time Register */
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mtsdram_as(SDRAM_RTR, CFG_SDRAM0_RTR);
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/* Set SDRAM Timing Registers */
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mtsdram_as(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
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mtsdram_as(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
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mtsdram_as(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
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/* Set Mode and Extended Mode Registers */
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mtsdram_as(SDRAM_MMODE, CFG_SDRAM0_MMODE);
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mtsdram_as(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
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/* Set Memory Controller Options 1 Register */
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mtsdram_as(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
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/* Set Manual Initialization Control Registers */
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mtsdram_as(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
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mtsdram_as(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
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mtsdram_as(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
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mtsdram_as(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
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mtsdram_as(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
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mtsdram_as(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
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mtsdram_as(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
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mtsdram_as(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
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mtsdram_as(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
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mtsdram_as(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
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mtsdram_as(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
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mtsdram_as(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
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mtsdram_as(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
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mtsdram_as(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
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mtsdram_as(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
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mtsdram_as(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
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/* Set On-Die Termination Registers */
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mtsdram_as(SDRAM_CODT, CFG_SDRAM0_CODT);
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mtsdram_as(SDRAM_MODT0, CFG_SDRAM0_MODT0);
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mtsdram_as(SDRAM_MODT1, CFG_SDRAM0_MODT1);
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/* Set Write Timing Register */
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mtsdram_as(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
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/*
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* Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
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* SDRAM0_MCOPT2[IPTR] = 1
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*/
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mtsdram_as(SDRAM_MCOPT2, SDRAM_MCOPT2_SREN_EXIT | \
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SDRAM_MCOPT2_IPTR_EXECUTE);
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/*
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* Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
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* completion of initialization.
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*
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* do {
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* mfsdram(SDRAM_MCSTAT, val);
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* } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
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*/
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li r4,SDRAM_MCSTAT
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lis r2,SDRAM_MCSTAT_MIC_COMP@h
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ori r2,r2,SDRAM_MCSTAT_MIC_COMP@l
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0: mtdcr memcfga,r4
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mfdcr r3,memcfgd
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clrrwi r3,r3,31
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cmpw cr7,r3,r2
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bne+ cr7,0b
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/* Set Delay Control Registers */
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mtsdram_as(SDRAM_DLCR, CFG_SDRAM0_DLCR);
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mtsdram_as(SDRAM_RDCC, CFG_SDRAM0_RDCC);
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mtsdram_as(SDRAM_RQDC, CFG_SDRAM0_RQDC);
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mtsdram_as(SDRAM_RFDC, CFG_SDRAM0_RFDC);
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/*
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* Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
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*
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* mcopt2 = mfsdram(SDRAM_MCOPT2);
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*/
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li r4,SDRAM_MCOPT2
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mtdcr memcfga,r4
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mfdcr r3,memcfgd
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/*
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* mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE);
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*/
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mtdcr memcfga,r4
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oris r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@h
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ori r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@l
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mtdcr memcfgd,r3
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#if defined(CONFIG_DDR_ECC)
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/*
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* ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
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*/
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mflr r13
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lis r3,CFG_SDRAM_BASE@h
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ori r3,r3,CFG_SDRAM_BASE@l
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lis r4,(CFG_MBYTES_SDRAM << 20)@h
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ori r4,r4,(CFG_MBYTES_SDRAM << 20)@l
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bl ecc_init
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mtlr r13
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#endif /* defined(CONFIG_DDR_ECC) */
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#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
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#endif /* !defined(CFG_INIT_DCACHE_CS) */
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blr
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@ -1,84 +0,0 @@
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/*
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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void sdram_init(void)
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{
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return;
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}
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#if defined(CONFIG_NAND_U_BOOT)
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long int initdram(int board_type)
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{
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return (CFG_MBYTES_SDRAM << 20);
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}
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#endif /* defined(CONFIG_NAND_U_BOOT) */
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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printf ("testdram\n");
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#if defined (CONFIG_NAND_U_BOOT)
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return 0;
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#endif
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uint *pstart = (uint *) 0x00000000;
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uint *pend = (uint *) 0x00001000;
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uint *p;
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for (p = pstart; p < pend; p++) {
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*p = 0xaaaaaaaa;
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}
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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#if !defined (CONFIG_NAND_SPL)
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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#endif
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return 1;
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}
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}
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for (p = pstart; p < pend; p++) {
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*p = 0x55555555;
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}
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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#if !defined (CONFIG_NAND_SPL)
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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#endif
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return 1;
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}
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}
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#if !defined (CONFIG_NAND_SPL)
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printf ("SDRAM test passed!!!\n");
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#endif
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return 0;
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}
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#endif
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@ -3083,6 +3083,16 @@ static void ppc440sp_sdram_register_dump(void)
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*---------------------------------------------------------------------------*/
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long initdram(int board_type)
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{
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/*
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* Only run this SDRAM init code once. For NAND booting
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* targets like Kilauea, we call initdram() early from the
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* 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
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* Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
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* which calls initdram() again. This time the controller
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* mustn't be reconfigured again since we're already running
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* from SDRAM.
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*/
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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unsigned long val;
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/* Set Memory Bank Configuration Registers */
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@ -3178,6 +3188,7 @@ long initdram(int board_type)
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#if defined(CONFIG_DDR_ECC)
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ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
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#endif /* defined(CONFIG_DDR_ECC) */
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#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
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return (CFG_MBYTES_SDRAM << 20);
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}
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@ -170,9 +170,9 @@
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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* On 440EPx the SPL is copied to SDRAM before the NAND controller is
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* set up. While still running from cache, I experienced problems accessing
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* the NAND controller. sr - 2006-08-25
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* On 405EX the SPL is copied to SDRAM before the NAND controller is
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* set up. While still running from location 0xfffff000...0xffffffff the
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* NAND controller cannot be accessed since it is attached to CS0 too.
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*/
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#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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@ -511,7 +511,7 @@
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/* Memory Bank 2 (FPGA) initialization */
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#define CFG_EBC_PB2AP 0x9400C800
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#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
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#define CFG_EBC_PB2CR (CFG_FPGA_BASE | 0x18000)
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#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
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@ -29,8 +29,8 @@ LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
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AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o init.o resetvec.o cache.o
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COBJS = memory.o nand_boot.o nand_ecc.o ndfc.o
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SOBJS = start.o resetvec.o cache.o
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COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -57,10 +57,18 @@ $(nandobj)u-boot-spl: $(OBJS)
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# create symbolic links for common files
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# from cpu directory
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$(obj)44x_spd_ddr2.c: ecc.h
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@rm -f $(obj)44x_spd_ddr2.c
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ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
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$(obj)cache.S:
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@rm -f $(obj)cache.S
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ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S
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$(obj)ecc.h:
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@rm -f $(obj)ecc.h
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ln -s $(SRCTREE)/cpu/ppc4xx/ecc.h $(obj)ecc.h
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$(obj)ndfc.c:
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@rm -f $(obj)ndfc.c
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ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
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@ -73,15 +81,6 @@ $(obj)start.S:
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@rm -f $(obj)start.S
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ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
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# from board directory
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$(obj)init.S:
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@rm -f $(obj)init.S
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ln -s $(SRCTREE)/board/amcc/kilauea/init.S $(obj)init.S
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$(obj)memory.c:
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@rm -f $(obj)memory.c
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ln -s $(SRCTREE)/board/amcc/kilauea/memory.c $(obj)memory.c
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# from nand_spl directory
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$(obj)nand_boot.c:
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@rm -f $(obj)nand_boot.c
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@ -29,8 +29,9 @@
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#
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# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
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# in the last 4kBytes of memory space in cache.
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# We will copy this SPL into instruction-cache in start.S. So we set
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# TEXT_BASE to starting address in i-cache here.
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# We will copy this SPL into SDRAM since we can't access the NAND
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# controller at CS0 while running from this location. So we set
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# TEXT_BASE to starting address in SDRAM here.
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#
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TEXT_BASE = 0x00800000
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@ -32,7 +32,6 @@ SECTIONS
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.text :
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{
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start.o (.text)
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init.o (.text)
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nand_boot.o (.text)
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ndfc.o (.text)
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