Commit graph

899 commits

Author SHA1 Message Date
Michael Walle
b1c41231c4 armv8: layerscape: fix alignment for spin table
Fix the alignment so it will match the comments. The spin table has to
be 8 byte aligned, so ".align 3" is enough.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
2eca7b9704 armv8: layerscape: load function pointer using ADR
Don't use LDR to load a pointer to a function. This will generate a
literal which cannot be relocated. Use ADR which is PC-relative and
therefore can easily be relocated.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
f6c62f1c9e armv8: layerscape: move spin table into own module
Move it out of lowlevel.S into spintable.S. On layerscape, the secondary
CPUs are brought up in main u-boot. This will make it possible to only
compile the spin table code for the main u-boot and omit it in SPL.

This saves about 720 bytes in the SPL.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
3d3fe8b12d armv8: layerscape: properly use CPU_RELEASE_ADDR
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.

Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
ae846a6119 armv8: layerscape: pretty print info about SMP cores
Make the print of the starting address a debug output and pretty print
the info about online cores.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
b27f48540e armv8: layerscape: fix spin-table support
Spin tables are broken with bootefi. This is because - in contrast to
the booti call chain - there is no call to smp_kick_all_cpus(). Due to
this missing call the secondary CPUs are never released from their "wait
for interrupt state", see secondary_boot_func() in lowlevel.S.

Originally, this "wait for interrupt" is there to make sure, the spin
table is cleared before the secondary cores read it for the first time.
But the boot flow for the layerscape architecture is different from
that. The CPUs are release from their BootROM _after_ U-Boot's
spin-table is cleared, see fsl_layerscape_wake_seconday_cores() in mp.c.
Thus, there is no need to wait for this interrupt and no need for
kicking all cores on cpu_release. An atomic 64bit write to the
spin-table and a "sev" is sufficient.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
f8c5815c1b armv8: ls1028a: move FSL_LAYERSCAPE to kconfig
CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to
define it per board; the ls1028a_common.h is really board dependent and
only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE
when ARCH_LS1028A is selected.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:26 +05:30
Masahiro Yamada
b75d8dc564 treewide: convert bd_t to struct bd_info by coccinelle
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-17 09:30:13 -04:00
Volodymyr Babchuk
f8ddd8cbb5 arm64: issue ISB after updating system registers
ARM Architecture reference manual clearly states that PE pipeline
should be flushed after changes to some system registers. Refer to
paragraph "B2.3.5 Memory Barriers" at page B2-92 of "Arm Architecture
Reference Manual ARMv8 for ARMv8-A Architecture Profile" (ARM DDI
0487B.a).

Failing to issue instruction synchronization barrier can lead to
spurious errors, like synchronous exception when accessing FPU
registers. This is very prominent on CPUs with long instruction
pipeline, like ARM Cortex A72.

This change fixes the following U-Boot panic:

 "Synchronous Abort" handler, esr 0x1fe00000
 elr: 00000000800948cc lr : 0000000080091e04
 x0 : 00000000801ffdc8 x1 : 00000000000000c8
 x2 : 00000000800979d4 x3 : 00000000801ffc60
 x4 : 00000000801ffd40 x5 : ffffff80ffffffd8
 x6 : 00000000801ffd70 x7 : 00000000801ffd70
 x8 : 000000000000000a x9 : 0000000000000000
 x10: 0000000000000044 x11: 0000000000000000
 x12: 0000000000000000 x13: 0000000000000000
 x14: 0000000000000000 x15: 0000000000000000
 x16: 000000008008b2e0 x17: 0000000000000000
 x18: 00000000801ffec0 x19: 00000000800957b0
 x20: 00000000000000c8 x21: 00000000801ffdc8
 x22: 000000008009909e x23: 0000000000000000
 x24: 0000000000000000 x25: 0000000000000000
 x26: 0000000000000000 x27: 0000000000000000
 x28: 0000000000000000 x29: 00000000801ffc50

 Code: a94417e4 a90217e4 a9051fe6 a90617e4 (3d801fe0)

While executing instruction

 str     q0, [sp, #112]

in vsnprintf() prologue. This panic was observed only on Cortex A72 so
far.

This patch places ISBs on other strategic places as well.

Also, this probably is the right fix for the issue workarounded in the
commit 45f41c134b ("ARM: uniphier: add weird workaround code for LD20")

Reported-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Suggested-by: Julien Grall <julien.grall.oss@gmail.com>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
CC: Tom Rini <trini@konsulko.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Julien Grall <julien@xen.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-07 11:01:52 -04:00
Peng Fan
b4b2619211 armv8: cache_v8: fix mmu_set_region_dcache_behaviour
The enum dcache_optoion contains a shift left 2 bits in the armv8 case
already.  The PMD_ATTRINDX(option) macro will perform a left shift of 2
bits.  Perform a right shift so that in the end we get the correct
value.

[trini: Reword the commit message]
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-25 11:54:53 -04:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
25a5818ff8 common: Drop asm/ptrace.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
0914011310 command: Remove the cmd_tbl_t typedef
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.

Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.

This requires quite a few header-file additions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 18:36:55 -04:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
4d72caa5b9 common: Drop image.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
52f2423804 common: Drop bootstage.h from common header
Move this fairly uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
90526e9fba common: Drop net.h from common header
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:31 -04:00
Simon Glass
c3dc39a2f8 arm: Don't include common.h in header files
It is bad practice to include common.h in other header files since it can
bring in any number of superfluous definitions. It implies that some C
files don't include it and thus may be missing CONFIG options that are set
up by that file. The C files should include these themselves.

Update some header files in arch/arm to drop this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 14:54:24 -04:00
Michael Walle
714497e327 efi_loader: round the memory area in efi_add_memory_map()
Virtually all callers of this function do the rounding on their own.
Some do it right, some don't. Instead of doing this in each caller,
do the rounding in efi_add_memory_map(). Change the size parameter
to bytes instead of pages and remove aligning and size calculation in
all callers.

There is no more need to make the original efi_add_memory_map() (which
takes pages as size) available outside the module. Thus rename it to
efi_add_memory_map_pg() and make it static to prevent further misuse
outside the module.

Signed-off-by: Michael Walle <michael@walle.cc>
Add missing comma in sunxi_display.c.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-17 21:59:53 +02:00
Peng Fan
6aead23323 imx: imx8qm/qxp: Recover SPL data section for partition reboot
When doing partition reboot, the boot image won't be reloaded by ROM,
it is just CPU reset to boot entry. The SW has to keep the boot image
inside the RAM unchanged. It includes both the TEXT section and DATA
section.

For SPL, the problem is DATA section will be updated at runtime, so in
next partition reboot the data is not same as the initial value from
cold boot. If any code depends on the initial value, then it will have
problem.

This patch introduces a mechanism to recover the data section
for partition reboot. It adds a new section in image for saving
data section. When from cold boot, the data section will be saved
to that new section at SPL early phase. When from partition reboot,
the data section will be restored from the new section.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Madalin Bucur
6eb32a03e0 driver: net: fm: add DM ETH support
Probe the FMan MACs based on the device tree while
retaining the legacy code/functionality.
One notable change introduced here is that, for DM_ETH,
the name of the interfaces is corrected to the fmX-macY
format, that avoids the referral to the MAC block names
which were incorrect for FMan v3 devices (i.e. DTSEC,
TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1).
The legacy code is left unchanged in this respect.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Hou Zhiqiang
f40b120e93 fsl-layerscape: Move GIC RD tables init to soc.c
Move GIC redistributor tables initialization to CPU setup function.

This patch introduces a GIC redistributor tables init function, and
moves the function of reserving memory for GIC redistributor tables
to soc.c and adds a argument for the memory size to reserve, BTW
rename the function so that it is more readable.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 17:46:46 +05:30
Hou Zhiqiang
0d5b0711e9 fsl-layerscape: Kconfig: Select RESV_RAM if GIC_V3_ITS
The GIC redistributor tables initialization depends on RESV_RAM config,
so select RESV_RAM if GIC_V3_ITS is enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 17:46:46 +05:30
Hou Zhiqiang
6ebd48835f fsl-layerscape: Add RESV_RAM check in resv_ram addr
The initialization of gd->arch.resv_ram pointer should depend on if the
RESV_RAM config is enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 17:46:46 +05:30
Florinel Iordache
5d3bcdb12f phy: add support for backplane kr mode
Add generic support for backplane kr modes currently available:
10gbase-kr, 40gbase-kr4. Remove platform generic fixups
(armv8/layerscape and powerpc) for ethernet interfaces specified
in device tree as supported backplane modes.

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-20 13:35:11 +05:30
JC Kuo
d491dc09e4 t210: do not enable PLLE and UPHY PLL HW PWRSEQ
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.

Adds call to board_cleanup_before_linux to facilitate this.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-02 14:30:01 -07:00
Biwen Li
bb1165f900 dm: arm64: ls1046a: add i2c DM support
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1046A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:12:13 +05:30
Biwen Li
fefac937fb dm: arm64: ls1043a: add i2c DM support
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1043A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:12:13 +05:30
Biwen Li
a0affb367a dm: arm64: ls1012a: add i2c DM support
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1012A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-02-04 16:20:25 +05:30
Biwen Li
beadf4f28c armv8: fsl-layerscape: spl: fix build error when DM_I2C is enabled
Fix below SPL build error when DM_I2C is enabled,
- arch/arm/cpu/armv8/built-in.o: In function `board_init_f:
  arch/arm/cpu/armv8/fsl-layerscape/spl.c:74: undefined reference to `i2c_init_all'
  arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:(.text.board_init_f+0x30):
  relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
  `i2c_init_all'
  make[2]: *** [spl/u-boot-spl] Error 1
  make[1]: *** [spl/u-boot-spl] Error 2
  make: *** [sub-make] Error 2
  arch/arm/cpu/armv8/fsl-layerscape/spl.c: In function 'board_init_f':
  arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:2: warning: implicit
  declaration of function 'i2c_init_all'; did you mean 'misc_init_r'?
  [-Wimplicit-function-declaration]`

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-02-04 16:20:25 +05:30
Alex Marginean
0d9d557de5 arch: armv8: fsl-layerscape: export serdes config to environment
Exports the serdes configuration as an environment variable for LS gen 3
SoCs, so it can be used in u-boot command line.  It should particularly
be useful for applying Linux DT overlays for the given serdes
configuration.
This code is called from arch_misc_init and not from the existing
serdes_init function because it depends on U-Boot environment being set
up.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Alex Marginean
430a5542f3 armv8: ls1028a_serdes: Add few missing serdes protocols
Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list.
These protocols are supported and functional but they trigger a warning
in U-Boot console at boot because they are not on this list.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Pramod Kumar
0b7435107b armv8: fsl-layerscape: LS1044A/1048A: enable Only 1x 10GE port
LS1088A has four personalities, LS1088A, LS1084A, LS1048A and LS1044A.
LS1044A, LS1048A are LS1088A personalities, which support only one
1x 10GE port.
MAC1 and MAC2 are associated with 1G SGMII, 2.5G SGMII, and XFI.
Disable MAC1 to have only one 1x 10GE port for LS1044A, LS1048A.

Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Ran Wang
d085c9ad06 armv8: ls1012a: Make USB masters snoopable
Program register bit of SCFG_SNPCNFGCR_USBRDSNP and
SCFG_SNPCNFGCR_USBWRSNP to drive USB read/write
snoop signal on LS1012A.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Simon Glass
db41d65a97 common: Move hang() to the same header as panic()
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Migrate a few more files]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17 17:53:40 -05:00
Simon Glass
9b4a205f45 common: Move RAM-sizing functions to init.h
These functions relate to memory init so move them into the init
header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 14:02:35 -05:00
Simon Glass
9a3b4ceb37 common: Move reset_cpu() to the CPU header
Move this function out of common.h and into a relevant header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 14:02:31 -05:00
Simon Glass
d96c26040e common: Move clock functions into a new file
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:27:29 -05:00
Yangbo Lu
f1bce08426 Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage
The eSDHC reference clocks should be provided by speed.c in arch/.
And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to
select which clock to use. Because we can make the driver to select
the periperhal clock which is better (provides higher frequency)
automatically if its value is provided by speed.c.

This patch is to drop this option and make driver to select clock
automatically. Also fix peripheral clock calculation issue in
fsl_lsch2_speed.c/fsl_lsch3_speed.c.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16 13:20:33 +08:00
Rajesh Ravi
41acbc53f4 arm: cpu: armv8: add support for arm psci reset2.
Current U-Boot has only support for psci reset.
Adding support for arm psci reset2 allows passing of reset level
and other platform sepcific parameters like strap settings
to lowlevel psci implementation.

Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
2020-01-10 14:18:26 -05:00
Pankaj Bansal
ba7c966c0f pci: layerscape: move PCIE related CONFIG to PCI Kconfig
move the PCIE related config from arch Kconfig to PCI Kconfig.
As the PCI_LAYERSCAPE driver is being used in platform other than
fsl-layerscape platforms like ls102xa.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02 14:36:57 +05:30
Kuldeep Singh
ce3bead608 fsl-lsch3: soc: Enable AHB read support for Flexspi controller
Enable AHB support for Flexspi controller interface meaning
memory can be accessed via md command using absolute addresses

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Alex Marginean
3499dd033c ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Ran Wang
0cfa00cdb9 armv8: Add workaround for USB erratum A-050106
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Michael Walle
055aa33ff9 armv8: layerscape: fix SPL multi DTB loading
Mark board_fit_config_name_match() as weak so a board can overwrite the
empty function.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Thomas Hebb
9f67b56772 Fix typo in macros, "FIRMEWARE" -> "FIRMWARE"
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-12-05 10:28:39 -05:00
Thomas Hebb
32f2ca2a7e cosmetic: Fix spelling and whitespace errors
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-12-03 08:43:23 -05:00
Simon Glass
5255932f01 common: Move some board functions out of common.h
A number of board function belong in init.h with the others. Move them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:21 -05:00
Simon Glass
36bf446b64 common: Move enable/disable_interrupts out of common.h
Move these two functions into the irq_funcs.h header file. Also move
interrupt_handler_t as this is used by the irq_install_handler() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:01 -05:00
Simon Glass
1eb69ae498 common: Move ARM cache operations out of common.h
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:24:58 -05:00
Simon Glass
9edefc2776 common: Move some cache and MMU functions out of common.h
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.

Move them over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:55 -05:00
Simon Glass
b5981474f1 common: Move some CPU functions out of common.h
These functions belong in cpu_func.h since they do not use driver model.
Move them over. Don't bother adding comments since these functions should
be deleted.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
68a6aa85ec common: Move mii_init() function out of common.h
This function belongs in mii.h so move it over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
6887c5bed9 common: Move some time functions out of common.h
These functions belong in time.h so move them over and add comments.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:11 -05:00
Simon Glass
2189d5f1e8 Move strtomhz() to vsprintf.h
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.

Use the vsprintf.h include file explicitly where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:09 -05:00
Simon Glass
62f9b65447 common: Move older CPU functions to their own header
These should be moved to driver model, but in the meantime, move them
out of the common header to help reduce its size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:06 -05:00
Yangbo Lu
d3eb317ea5 arm: drop eSDHC clock getting in mxc_get_clock() for layerscape
Although layerscape platforms reuse mxc_get_clock() of i.MX platforms,
eSDHC clock getting do not have to use it. It uses global data
gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more
than one eSDHC controllers on SoC, they use same reference clock.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27 16:55:56 +08:00
Tom Rini
a09fea1d28 env: Finish migration of common ENV options
- In ARMv8 NXP Layerscape platforms we also need to make use of
  CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so.
- On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define
  to 0.
- Add Kconfig entry for ENV_ADDR.
- Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it.
- Add ENV_xxx_REDUND options that depend on their primary option and
  SYS_REDUNDAND_ENVIRONMENT
- On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR
  for the pre-main-U-Boot environment location.
- On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but
  rather it being non-zero, as it will now be zero by default.
- Rework the env_offset absolute in env/embedded.o to not use
  CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within
  ENV_IS_IN_FLASH.
- Migrate all platforms.

Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: uboot-stm32@st-md-mailman.stormreply.com
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-20 18:32:09 -05:00
Udit Agarwal
5536c3c9d0 freescale/layerscape: Rename the config CONFIG_SECURE_BOOT name
Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict
with UEFI secure boot.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 16:32:08 +05:30
Pankaj Bansal
812ff53c3e fsl-layerscape: fix warning if no hwconfig is defined
While getting the 'subarg' of 'hwconfig' env variable in
config_core_prefetch(), if no hwconfig variable is defined,
below warning is received:
WARNING: Calling __hwconfig without a buffer and
	before environment is ready

Fix this by checking 'hwconfig' env variable.
If not found return without further processing.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
2019-11-08 15:50:12 +05:30
Michael Walle
762ee522e2 armv8: fsl-layerscape: introduce fsl_board_late_init()
The fsl-layerscape already occupies board_late_init(), therefore it is
not possible for a board to have its own board_late_init(). Introduce
fsl_board_late_init() which can be implemented in the board specific
code.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:39 +05:30
Michael Walle
065ee175e0 armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x
The clocks are not dependent on the target but only on the SoC.
Therefore, convert the CONFIG_TARGET_x macros to the corresponding
CONFIG_ARCH_x. This will allow other targets to automatically use the
common code. Otherwise every new target would have to add itself to the
"#if defined(CONFIG_TARGET_x) || .." macros.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:39 +05:30
Laurentiu Tudor
b4a59115e2 armv8: ls1028a: add erratum A-050382 workaround
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Laurentiu Tudor
30449aea50 armv8: lx2160a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Laurentiu Tudor
e33938acc9 armv8: ls2088a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Laurentiu Tudor
db49c1b2de armv8: fsl-layerscape: guard caam specific defines
These macros should only be used when CONFIG_FSL_CAAM is present.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Mathew McBride
28f9393b1a fsl-layerscape: do not use layerscape EFI reset if PSCI used
If the secure world reset handlers are used (via CONFIG_PSCI_RESET),
then do not use the layerscape-specific implementation.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Yuantian Tang
54d5c06cb9 armv8: ls1028a: disable multimedia for ls1027a, ls1017a
ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a.
Both ls1027a and ls1017a personalities are lower functionality version
which doesn't support the multimedia subsystems, like LCD, GPU.

To disable multimedia feature on non-multimedia version,
set the status property to disabled in dts nodes.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21 15:34:17 +05:30
Ran Wang
3d23b6c583 armv8: fsl-layerscape: Make USB masters snoopable
Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and
SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write
snoop signal on LS1043A and LS1046A.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21 15:34:17 +05:30
Yuantian Tang
6ed6952383 armv8: ls1028a: Add more personalities support
Add LS1027A, LS1018A and LS1017A personalities support to
LS1028A SoC family.

LS1028A is the prime personality of LS1028A SoC family.
LS1027A is a lower funtionality version of QorIQ LS1028A
which does not support the multimedia subsystems, such as LCD
controller, GPU, and eDP PHY.

The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72
core, low power versions of the QorIQ LS1028A and LS1027A
SoCs respectively.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-21 15:34:17 +05:30
Heiko Schocher
ca51ef7c0c watchdog: move WATCHDOG_TIMEOUT_MSECS to Kconfig
move WATCHDOG_TIMEOUT_MSECS to Kconfig and fix
all board defconfigs.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Martyn Welch <martyn.welch@collabora.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-10-08 07:46:38 +02:00
Hou Zhiqiang
116f75c7b3 armv8: ls1028a: Updated serdes configuration for 0x13BB
In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2

Fixes: 36f50b7523 ("armv8: ls1028a: Add other serdes
		     protocal support")

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Hou Zhiqiang
c9ba88bafc armv8: fsl-layerscape: Fix typo in Layerscape PCIe config entry
The correct config entry is CONFIG_PCIE_LAYERSCAPE and this
typo results in skipping the fixup of Linux PCIe DT nodes.

Also enable the fixup when Layerscape Gen4 controller driver
is enabled.

Fixes: 4da0e52c9d (armv8: fsl-layerscape: fix config dependency
		     for layerscape pci code)

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Chuanhua Han
2f2a19757b armv8: fsl-layerscape: Update I2C clock divider
By default, i2c input clock is programmed at
platform clk / 2 in u-boot, but this is not
correct for all the platforms,
Update I2C clock divider's default values as per
SoC (LS1012A, LS1028A, LX2160A and LS1088A).

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Thomas Schaefer
0490cab584 armv8: ls1028a: configure PMU's PCTBENR to enable WDT
The SP805-WDT module on LS1028A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.

Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Yinbo Zhu
24cb6f2295 fsl-layerscape: Add fsl_esdhc peripheral clock support
Add esdhc peripheral clock support
for NXP layerscape platforms: LS1046ARDB, LS1043ARDB,
LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:00:35 +05:30
Florinel Iordache
1bad991205 drivers/fsl-mc: Create Kconfig file to manage driver specific configs better
Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs
from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-04 11:37:19 -05:00
Laurentiu Tudor
b249fcba00 armv8: ls1028a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, edma, qdma, gpu, display and sec.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
5c6dc6c9a9 armv8: ls1088a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Laurentiu Tudor
aef654a2ed armv8: fsl-layerscape: make icid setup endianness aware
The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
71a2da3fa9 armv8: kconfig: Fix some platforms incorrect I2C clock divider
By default, i2c input clock is platform clk / 2, but some of the
platform of i2c clock divider does not meet this kind of circumstance,
so alone to set default values for these platforms.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
67d3a815cb configs: ls1088a: Enable DM support for pcf2127 rtc
Enable related configs on all ls1088aqds boards to support pcf2127
rtc DM function.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
292370df1c configs: ls2088a: Enable DM support for ds3231 rtc
Enable related configs on all ls2088aqds boards to support ds3231
rtc DM function.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:36 +05:30
Chuanhua Han
21d5e964da configs: ls1028a: Enable DM support for pcf2127 rtc
Enable related configs on all ls1028aqds boards to support pcf2127
rtc DM function.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Tested-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Chuanhua Han
7abf9c16aa configs: lx2160: enable DM support for pcf2127 rtc
Enable related configs on all lx2160ardb boards to support pcf2127
rtc DM feature.

Also remove SYS_I2C_MXC_I2Cx, where x is from 1 to 8 from
Kconfig.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22 09:07:35 +05:30
Simon Glass
f3998fdc4d env: Rename environment.h to env_internal.h
This file contains lots of internal details about the environment. Most
code can include env.h instead, calling the functions there as needed.

Rename this file and add a comment at the top to indicate its internal
nature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
[trini: Fixup apalis-tk1.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-11 19:27:31 -04:00
Simon Glass
9fb625ce05 env: Move env_set() to env.h
Move env_set() over to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
4bfd1f5d62 env: Move env_init() to env.h
Move env_init() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
3a7d55716d env: Move env_get_f() to env.h
Move this function over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
AKASHI Takahiro
6324d50679 arm: move CONFIG_TFABOOT to generic Kconfig
Currently, CONFIG_TFABOOT is located in armv8/fsl-layerscape Kconfig,
but it will be also useful for other targets if some additional
configuration are necessary.
So move it to arch/arm/Kconfig.

Please note that CONFIG_TFABOOT still depends on
CONFIG_ARCH_SUPPORT_TFABOOT and so the menu won't come up
if any target doesn't need its own customization for TF-A boot.
This will maintain the compatibility.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Sriram Dash <sriram.dash@nxp.com>
Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Cc: Peng Ma <peng.ma@nxp.com>
Cc: Yuantian Tang <andy.tang@nxp.com>
Cc: Pankit Garg <pankit.garg@nxp.com>
2019-07-18 11:31:27 -04:00
Masahiro Yamada
382de4a7e9 arm64: add an option to switch visibility of CONFIG_SYS_INIT_SP_BSS_OFFSET
By default, CONFIG_SYS_INIT_SP_BSS_OFFSET was made invisible by not
giving a prompt to it.

The only way to define it is to hard-code an extra entry in SoC/board
Kconfig, like arch/arm/mach-tegra/tegra{186,210}/Kconfig.

Add a prompt to it in order to allow defconfig files to specify the
value of CONFIG_SYS_INIT_SP_BSS_OFFSET.

With this, CONFIG_SYS_INIT_SP_BSS_OFFSET would become always visible.
So, we need a new bool option to turn it off by default.

I move the 'default 524288' to the common place. This value is not too
big, but is big enough to avoid the overwrap of DT in most platforms.
If 512KB is not a suitable choice for your platform, you can change it
from your defconfig or menuconfig etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2019-07-10 22:37:23 +09:00
Yangbo Lu
e37ac717d7 Convert to use fsl_esdhc_imx for i.MX platforms
Converted to use fsl_esdhc_imx for i.MX platforms.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
2019-06-23 14:18:34 +08:00
Mian Yousaf Kaukab
f2f83b2fd0 armv8: fix typo in LINUX_KERNEL_IMAGE_HEADER check
Fixes: 8163faf952 ARMv8: add optional Linux kernel image header

Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Andreas Färber <afaerber@suse.de>
2019-06-20 10:57:08 -04:00
Vabhav Sharma
d90c7ac7a9 armv8: ls1046afrwy: Add support for LS1046AFRWY platform
LS1046AFRWY board supports LS1046A family SoCs. This patch
add base support for this board.
Board support's 4GB ddr memory, i2c, micro-click module,microSD card,
serial console,qspi nor flash,ifc nand flash,qsgmii network interface,
usb 3.0 and serdes interface to support two x1gen3 pcie interface.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Yinbo Zhu
0dd74ec2df armv8: fsl-lsch2: add clock support for the second eSDHC
Layerscape began to use two eSDHC controllers, for example,
LS1012A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Maciej Pijanowski
c34d8dcb3e arm: fsl-layerscape: add 0x3040 serdes1 settings for LS1046A
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Cc: piotr.krol@3mdeb.com
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Maciej Pijanowski
73420f0220 arm: fsl-layerscape: fix 0x3363 serdes1 settings for ls1046a
As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on
lane D and lane C respectively for 0x3363 protocol.

So fix serdes1 settings for ls1046a.

Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Alex Marginean
4da0e52c9d armv8: fsl-layerscape: fix config dependency for layerscape pci code
Fixes a link error on layerscape platform, linking fails with CONFIG_PCI
set and CONFIG_PCI_LAYERSCAPE unset.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Pankit Garg
ab748801ef armv8: fsl-layerscape: Change bootcmd update logic
Change bootcmd update logic when CONFIG_ENV_ADDR is not defined

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Pankit Garg
293d75c0b1 armv8: fsl-layerscape: Update qspi clk cfg
Update qspi clock configuration in TFABOOT in case
of all boot sources except qspi boot source.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Meenakshi Aggarwal
1dff14c87d armv8/fsl-layerscape: Add loop to check L3 dcache status
Flushing L3 cache may need variable time depending upon cache line
allocation.

Coming up with a proper timeout value would be best handled by
simulations under multiple scenarios in your actual system.
>From the purely HN-F point of view, the flush would take ~15 cycles for
a clean line, and ~22 cycles for a dirty line.  For the dirty line case,
there are many variables outside the HN-F that will increase the
duration per line.  For example, a *DBIDResp from the SN-F/SBSX,
memory controller latency, SN-F/SBSX RetryAck responses, CCN ring
congestion, CCN ring hops, etc, etc.  The worst-case timeout would
have to factor in all of these variables plus the HN-F cycles for
every line in the L3, and assuming all lines are dirty

In case if L3 is not flushed properly, system behaviour will be
erratic, so remove timeout and add loop to check status of L3 cache.

System will stuck in while loop if there is some issue in L3 cache
flushing.

Signed-off-by: Udit Kumar <udit.kumar@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:57 +05:30
Yangbo Lu
087bfe67ac armv8: fsl-lsch3: add clock support for the second eSDHC
Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Xiaowei Bao
36f50b7523 armv8: ls1028a: Add other serdes protocal support
Add other serdes protocal support.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Yinbo Zhu
123fbbbe84 armv8: ls1028a: enable workaround for USB errarum A-009007
Rx Compliance tests may fail intermittently at high jitter
frequencies using default register values.

So program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Ran Wang
3458a4198c armv8: ls1028a: enable workaround for USB erratum A-008997
Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL
registers has been moved to DSCR as compared to other Layerscape SoCs
where it was in SCFG.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Udit Agarwal
d9532e8092 armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE.
ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on
CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE
is enabled

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Yuantian Tang
f278a21749 armv8: ls1028aqds: Add support of LS1028AQDS
LS1028AQDS Development System is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Yuantian Tang
353f36d96e armv8: ls1028ardb: Add support for LS1028ARDB
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Yuantian Tang
d4ad111dc4 armv8: ls1028a: Add NXP LS1028A SoC support
Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
 ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Hou Zhiqiang
20eae4c810 kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPAT
The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead
of PCIE_LAYERSCAPE.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Hou Zhiqiang
059d942283 armv8: lx2160a: add MMU table entries for PCIe
The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Hou Zhiqiang
8348e79865 armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry
Change to use PCIe address macro to determine if precompile the PCIe
MMU table entry.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Trevor Woerner
1001502545 CONFIG_SPL_SYS_[DI]CACHE_OFF: add
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-18 08:15:35 -04:00
Kever Yang
dc23c27aa5 arm: remove ARCH_ROCKCHIP macro in common code
This is fix to:
e2a12f590d rockchip: use 'arch-rockchip' as header file path

The V2 of origin patch set has fix this, but we merge V1 by
mistake, so lets correct it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Vignesh Raghavendra
add4967124 arch: armv8: Provide a way to disable cache maintenance ops
On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
maintenance operations being done to support non-coherent platforms
causes issues.

For example, here is how U-Boot prepares/handles a buffer to receive
data from a device (DMA Write). This may vary slightly depending on the
driver framework:

	Start DMA to write to destination buffer
	Wait for DMA to be done (dma_receive()/dma_memcpy())
	Invalidate destination buffer (invalidate_dcache_range())
	Read from destination buffer

The invalidate after the DMA is needed in order to read latest data from
memory that’s updated by DMA write. Also, in case random prefetch has
pulled in buffer data during the “wait for DMA” before the DMA has
written to it. This works well for non-coherent architectures.

In case of coherent architecture with L3 cache, DMA write would directly
update L3 cache contents (assuming cacheline is present in L3) without
updating the DDR memory. So invalidate after “wait for DMA” in above
sequence would discard latest data and read will cause stale data to be
fetched from DDR. Therefore invalidate after “wait for DMA” is not
always correct on coherent architecture.

Therefore, provide a Kconfig option to disable cache maintenance ops on
coherent architectures. This has added benefit of improving the
performance of DMA transfers as we no longer need to invalidate/flush
individual cache lines(especially for buffer thats several KBs in size).

In order to facilitate use of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
flush_dcache_all() and invalidate_dcache_all() are exclusively used
during enabling/disabling dcache and hence are not disabled.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-05-05 08:48:50 -04:00
Kever Yang
6916dad511 rockchip: arm: use 'arch-rockchip' for common header
rockchip platform header file is in 'arch-rockchip'
instead of arch-$(SOC) for all SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Lars Povlsen
25c07c72fd ARMv8: PSCI: Fix PSCI_TABLE relocation issue
This fixes relaction isses with the PSCI_TABLE entries in
the psci_32_table and psci_64_table.

When using 32-bit adress pointers relocation was not being applied to
the tables, causing PSCI handlers to point to the un-relocated code
area. By using 64-bit data relocation is properly applied. The
handlers are thus in the "secure data" area, which is protected by
/memreserve/ in the FDT.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-04-23 17:57:28 -04:00
Ibai Erkiaga
1721b82c1f arm: fix hvc call
HVC call makes use of 6 mandatory arguments rather than 7 in the same way
as SMC calls. The 7th argument is optional (Client ID) for both HVC and
SMC but is implemented as 16-bit parameter and register R7 or W7. The aim
of this patch is just fix compilation error due to an invalid asm code in
the HVC call so that's why the 7th argument is removed.

The issue does not report any error in a normal build as hvc_call is not
used at all and is optimized by the compiler. Using -O0 triggers the
error so the patch is intended to fix issues on a ongoing effor to build
U-Boot with -O0.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
2019-04-22 18:13:22 -04:00
Ang, Chee Hong
fd50eac910 ARMv8: Disable fwcall when PSCI is enabled
When PSCI is enabled, we are expecting U-Boot which now act
as EL3 software will handle all the PSCI calls. We won't need
fwcall as no further HVC or SMC are needed.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-04-22 18:13:21 -04:00
Chee Hong Ang
f6b0115a96 ARMv8: Allow SiP service extensions on top of PSCI code
Allow PSCI layer to handle any SiP service functions added by
platform vendors. PSCI layer will look for SiP service function
in the SiP function table located in '._secure_svc_tbl_entries'
section if the SMC function identifier is not found in the PSCI
standard functions table. Use DECLARE_SECURE_SVC macro to declare
and add platform specific SiP service function.
This new section '._secure_svc_tbl_entries' is located next to
'._secure.text' section. Refer to arch/arm/cpu/armv8/u-boot.lds.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2019-04-22 18:13:21 -04:00
Alexander Graf
ef331e3685 armv8: Disable exception vectors in SPL by default
Commit 1416e2d225 ("armv8: make SPL exception vectors optional") had a
typo in it which effectively disabled exception handling in SPL code always.

Since nobody complained, I guess we may as well disable exception handling
in SPL always by default.

So fix the bug to make the config option effective, but disable exception
handling in SPL by default. This gets us to the same functionality as before
by default, but with much less code included in the binary.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-22 12:15:03 -04:00
Laurentiu Tudor
e82d9ee73a armv8: fsl-layerscape: fix SEC QI ICID setup
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:09 +05:30
Peng Ma
f11e492aea armv8: ls1043a: move SCSI_AHCI and SCSI to arm/Kconfig
remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface
support.
this changed is to fixed the ls1043ardb compile warning as fallows:

===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the
v2019.07 release. Failure to update by the deadline may
result in board removal.See doc/driver-model/MIGRATION.txt
for more info.
====================================================

Signed-off-by: Peng Ma <peng.ma@nxp.com>
[PK: reword the patch subject]
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Rajesh Bhagat
5c08d96f3a armv8: layerscape: move CONFIG_LAYERSCAPE to Kconfig
Moves CONFIG_LAYERSCAPE for all NXP Layerscape platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Rajesh Bhagat
bbf5b25282 armv8: layerscape: move TZASC and TZPC configs to Kconfig
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig
for LS1088A and LS2088A platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Pankaj Bansal
1eba723c72 lx2160aqds : Add support for LX2160AQDS platform
LX2160AQDS is a development board that supports LX2160A
family SoCs. This patch add base support for this board.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[PK: Sqaush patch for "secure boot defconfig" & add maintainer]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:44 +05:30
Meenakshi Aggarwal
e088e587ed armv8: emc2305: add support for fan controller
Add support for fan controller emc2305.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Priyanka Jain
58c3e62040 armv8: lx2160ardb : Add support for LX2160ARDB platform
LX2160ARDB is an evaluation board that supports LX2160A
family SoCs. This patch add base support for this board.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han
and re-arrange defconfig]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Pankaj Bansal
2e53759dc6 armv8: fsl-layerscape: reorder rgmii dpmacs' enablement
some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.

Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
or not? if it is (fsl_serdes_init has already enabled the dpmac), then
don't enable it.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Priyanka Jain
8c4875395b armv8, lx2160a: Initialize ethernet array in serdes_init
Add code to initial ethernet interface arrays
with corresponding dpmac-id values in serdes_init function
for LX2160A.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Alexander Graf
2f8ab1218f arm: Leave smccc calls in .text when efi_loader=n
Commit 81ea00838c ("efi_loader: PSCI reset and shutdown") put the SMCCC
assembly code into the efi specific code section. This is wrong when we
do not have EFI_LOADER enabled, as that strips efi runtime sections from
the output binary

Reported-by: Michal Simek <monstr@monstr.eu>
Reported-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tested-by: Michal Simek <monstr@monstr.eu>
Fixes: 81ea00838c ("efi_loader: PSCI reset and shutdown")
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Heinrich Schuchardt
f6c6df7ebc efi_loader: refactor switch to non-secure mode
Refactor the switch from supervisor to hypervisor to a new function called
at the beginning of do_bootefi().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Tom Rini
2f41ade79e linker: Modify linker scripts to be more generic
Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than
CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE.  This lets us re-use the
same script for both SPL and TPL.  Add logic to scripts/Makefile.spl to
pass in the right value when preprocessing the script.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Adam Ford <aford173@gmail.com> #da850evm & omap3_logic_somlv
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-26 22:55:53 -05:00
Michal Simek
274ccb5b11 arm64: zynqmp: Move SoC sources to mach-zynqmp
Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.

Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.

Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Michal Simek
f11d4ab0b3 arm64: zynqmp: Do not protect zynqmp_pmufw_version()
There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version()
but also FPGA code is calling this function which is possible to use
without actual CLK_ZYNQMP firmware driver to be enabled.
This patch enables the case where only fixed-clock CLK setup is used.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Hou Zhiqiang
5b994e85a5 armv8: ls1043a: correct the PCIe INTx fixup
On LS1043A rev1.0 there are 4 interrupt pins for INTx, and on
rev1.1 there is only 1 for INTx, so the current fixup is inverse
of the fact.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:44 -08:00
Hou Zhiqiang
ec88ff80ff armv8: ls1043a: add SVR definitions for 23x23 package silicon
LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:40 -08:00
Rajesh Bhagat
9570df03ee armv8: ls2088ardb: Add TFABOOT support
TFABOOT support includes:
  - ls2088ardb_tfa_defconfig to be loaded by trusted firmware
  - environment address and size changes for TFABOOT
  - define BOOTCOMMAND for TFABOOT
  - remove EL3 specific erratas for TFABOOT

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:22 -08:00
Pankit Garg
143af3c6d5 armv8: ls1088ardb: Add TFABOOT support
TFABOOT support includes:
- ls1088ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- MC address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
- ifc chip select changes for TFABOOT

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:04 -08:00
Rajesh Bhagat
d23da2ae21 armv8: fsl-layerscape: fixes for TFABOOT framework
Fixes for TFABOOT framework
- update eMMC bootsrc to SD_MMC
- Increase buffer size for mcinitcmd from 256 to 512
- Fix mcinitcmd and bootcmd for Secure Boot

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:15:25 -08:00
Xiaoliang Yang
da4918acb8 watchdog: imx: add config to disable wdog reset
Add Kconfig option WATCHDOG_RESET_DISABLE to disable watchdog reset
in imx_watchdog driver, so that the watchdog will not be fed in
u-boot if CONFIG_WATCHDOG_RESET_DISABLE is enabled.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
2019-01-01 14:12:18 +01:00
Xiaoliang Yang
005c1cf888 watchdog: driver support for fsl-lsch2
Support watchdog driver for fsl-lsch2. It's disabled in default.
If you want to use it, please enable CONFIG_IMX_WATCHDOG.
Define CONFIG_WATCHDOG_TIMEOUT_MSECS to set watchdog timeout.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
2019-01-01 14:12:18 +01:00
Priyanka Jain
4909b89ec7 armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Priyanka Jain
d6fdec211f armv8:fsl-layerscape: Add support for Chassis 3.2
NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.

Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Priyanka Jain
6252faa0da armv8: lsch3: Add support of serdes3 module
Some lsch3 based SoCs like lx2160a contains three
serdes modules.
Add support for third serdes protocol in lsch3

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
ade32bb473 armv8: fsl-layerscape: add support of MC framework for TFA
Add support of MC framework for TFA
Make MC framework independent of boot source.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
2e17cb8a42 armv8: sec_firmware: return job ring status as true in TFABOOT
Returns job ring status as true in TFABOOT, as one job ring is always
reserved.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
339fb297d4 armv8: sec_firmware: change el2_to_aarch32 SMC ID
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17,
it is applicable to both TFA and non-TFA boot.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
York Sun
56db948b85 armv8: fsl-layerscape: Update parsing boot source
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
5a73ec6169 armv8: layerscape: skip OCRAM init for TFABOOT
OCRAM initialization is performed by TFA, Hence
skipped from u-boot.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
681d489e62 armv8: layerscape: add SMC calls for DDR size and bank info
Adds SMC calls for getting DDR size and bank info for TFABOOT.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
2141d250f5 armv8: fsl-layerscape: bootcmd identification for TFABOOT
Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
[YS: remove unnecessary braces]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:36 -08:00
Rajesh Bhagat
b6c97f4d94 armv8: layerscape: remove EL3 specific erratas for TFABOOT
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.

ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511,
SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663,
SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942,
SYS_FSL_ERRATUM_A010165

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
4c41738462 armv8: fsl-layerscape: identify boot source from PORSR register
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.

Further, it can be used to select the environment location.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix multiple checkpatch issues]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:26 -08:00
Rajesh Bhagat
535d76a121 armv8: layerscape: Add TFABOOT support
Adds TFABOOT support config option and add generic code to enable
execution from DDR.

Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
e350648046 armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3
Change tlb base address from OCRAM to DDR when exception level is
less than 3.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
York Sun
bb50569dc4 armv8: layerscape: Enable routing SError exception
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to
EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes
the exception to EL2. Otherwise this exception is not taken.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
York Sun
d171c70716 move data structure out of cpu.h
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-04 08:30:23 -08:00
Heinrich Schuchardt
81ea00838c efi_loader: PSCI reset and shutdown
When an operating system started via bootefi tries to reset or power off
this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system
the actual reset relies on PSCI. Depending on whether the PSCI firmware
resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC
or an SMC command has to be issued.

The current implementation always uses SMC. This results in crashes on
systems where the PSCI firmware is implemented in the hypervisor, e.g.
qemu-arm64_defconfig.

The logic to decide which call is needed based on the device tree is
already implemented in the PSCI firmware driver. During the EFI runtime
the device driver model is not available. But we can minimize code
duplication by merging the EFI runtime reset and poweroff code with
the PSCI firmware driver.

As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff
and reset_misc routines let's move them into the same code module.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02 21:59:37 +01:00
Chee Hong Ang
eb13dddd2c ARMv8: SError exception handling in PSCI exception vectors
Allow platform vendors to handle SError interrupt exceptions from
ARMv8 PSCI exception vectors by overriding this weak function
'plat_error_handler'.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:34 -05:00
Chee Hong Ang
c0f3296f83 ARMv8: Add EL3 exception handling for ARMv8's Kconfig
Kconfig option to allow all External Abort and SError exception
taken to EL3.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:34 -05:00
Siva Durga Prasad Paladugu
5860bc16b9 arm64: zynqmp: Add new command for TCM initialization
This patch adds new zynqmp command "zynqmp tcminit mode" to
initialize TCM. TCM needs to be initialized before accessing
to avoid ECC errors. This new command helps to perform
the same. It also makes tcm_init() as global and uses it for
doing the TCM initialization.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Siva Durga Prasad Paladugu
12ad2994a5 arm64: zynqmp: Move TCM initialization to a separate routine
This patch moves TCM initialization to a separate routine to
make it modular and can be reused if required. It also prints
warning message now as it writes to TCM.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Tom Rini
27f622d568 Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
 Switch to driver model for SATA on LS1021A and LS1043A.
 Add support for LS1012AFRWY rev C board.
 Enable SMMU for LS1043A.
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Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
Switch to driver model for SATA on LS1021A and LS1043A.
Add support for LS1012AFRWY rev C board.
Enable SMMU for LS1043A.
2018-09-29 11:47:32 -04:00
Laurentiu Tudor
dc29a4c177 armv8: ls1043a: add icid setup support
Reuse the existing ICID setup code done for LS1046A smmu enablement
and add the equivalent setup for LS1043A chips.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:58:15 -07:00
Yinbo Zhu
0fdf696721 armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support
This patch adds esdhc clock support for ls1088a and ls2088a.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:50:26 -07:00
Yinbo Zhu
c3ced8a6ed ppa/fm/qe: use block layer in ppa/fm/qe driver
At present the MMC subsystem maintains its own list of MMC devices.
This cannot work with driver model when CONFIG_BLK is enabled, use
blk_dread to replace previous mmc read interface, use
mmc_get_blk_desc to get the mmc device property.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
[York S: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:48:51 -07:00
Tom Rini
bbef20d479 Xilinx changes for v2018.11
- Handle BOARD_LATE_INIT via Kconfig
 
 SPL:
 - Enable GZIP for all partitions types(not only for kernel)
 
 ZynqMP:
 - Rearrange pmufw version handling
 - Support newer PMUFW with improved fpga load sequence
 
 Zynq:
 - Cleanup config file
 - Simplify zybo config by enabling option via Kconfig
 
 net:
 - Fix gems max-speed property reading
 - Enable support for fixed-link phys
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Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.11

- Handle BOARD_LATE_INIT via Kconfig

SPL:
- Enable GZIP for all partitions types(not only for kernel)

ZynqMP:
- Rearrange pmufw version handling
- Support newer PMUFW with improved fpga load sequence

Zynq:
- Cleanup config file
- Simplify zybo config by enabling option via Kconfig

net:
- Fix gems max-speed property reading
- Enable support for fixed-link phys
2018-09-27 08:29:10 -04:00
Siva Durga Prasad Paladugu
b94a8271cc arm64: zynqmp: Return pmufw version for zynqmp_pmufw_version()
Modify the zynqmp_pmufw_version() routine to return PMUFW version so
that it can be reused wherever required. Get PMUFW version from PMU
only once at bootup and later just return stored value.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Siva Durga Prasad Paladugu
fe68f2332d arm64: zynqmp: Move PM version related macros to .h
This patch moves the PM version related macros to .h file so that
they can be reused in other files.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Stephen Warren
9b5e6396bf efi_loader: simplify ifdefs
Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL
too. This simplifies the conditional.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:29 +02:00
York Sun
50f566d6ee armv8: fsl-layerscape: Update README.falcon for compression
Update README.falcon to use "none" for compression property for
ramdisk image to avoid being uncompressed upon loading.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-08-23 08:17:35 -07:00
Ran Wang
9add5a4b75 armv8: layerscape: Enable EHCI access for LS1012A
Program Central Security Unit (CSU) to grant access to USB 2.0
controller.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: rewrite commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:37:39 -07:00
Laurentiu Tudor
5651f438f8 armv8: ls1046a: setup SEC ICIDs and fix up device tree
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.

Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:46 -07:00
Laurentiu Tudor
b50ff5e1b6 armv8: ls1046a: setup fman ports ICIDs and device tree
Add support for ICID setting of fman ports and the required device
tree fixups.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:42 -07:00
Laurentiu Tudor
599a97d49c armv8: ls1046a: add icid setup for qman portals
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:36 -07:00
Laurentiu Tudor
3cb4fe65f9 armv8: ls1046a: initial icid setup support
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:33 -07:00
Andre Przywara
1416e2d225 armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.

On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.

Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03 19:53:54 -04:00
Andre Przywara
15b6184971 armv8: Reduce exception handling code
The arm64 exception handling code is quite big, mostly due to
architectural alignment requirements. Each exception entry spans 32
instructions, which sounds generous, but is too small to fit all of the
save/branch/restore code in there. So at the moment we use only four
instructions, branching into shared save and restore routines.
To not leave the space for those remaining 28 instructions wasted, let's
split the save and restore routines and stuff them into the gaps.
This saves about 250 bytes of code, which is helpful for those tight
SPLs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03 19:53:54 -04:00
Tom Rini
406fd7e207 Patch queue for efi - 2018-07-25
Highlights this time:
 
   - Many small fixes to improve spec compatibility (found by SCT)
   - Almost enough to run with sandbox target
   - GetTime() improvements
   - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-07-25

Highlights this time:

  - Many small fixes to improve spec compatibility (found by SCT)
  - Almost enough to run with sandbox target
  - GetTime() improvements
  - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
2018-07-30 16:02:29 -04:00
Michal Simek
58008cbab5 Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:48 -04:00
Tom Rini
0e8a8a3110 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-07-27 13:09:30 -04:00
Joe Hershberger
9cce566321 arm: Prevent redefinition error in fsl-layerscape
The include/phy.h will start including dm.h, which pulls in
linux/compat.h after the attempted redefinition in
arch/arm/include/asm/armv8/mmu.h, so move this include to allow
redefinition.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:21 -05:00
York Sun
038b965c2b armv8: ls1046ardb: Add falcon mode for for QSPI boot
A new defconfig is introduced to support SPL boot from QSPI NOR
flash. This is to support falcon mode for faster booting into
Linux.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 11:51:23 -07:00
York Sun
9960609275 armv8: layerscape: spl: Initialize QSPI AHB for QSPI boot
To get full access of QSPI space, initialize AHB interface.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Yuantian Tang
ed167eb1c7 armv8: fsl: remove sata support
Remove the old implementation in order to enable DM for sata.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
York Sun
61ab8aac60 armv8: layerscape: Enabled I-cache for SPL boot
Enable I-cache for SPL boot to boost performance. Earlier MMU was
enabled only for LS2080A and has since been dropped by commit
f539c8a4a7 ("armv8: ls2080a: Drop early MMU for SPL build").

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Alexander Graf
7e21fbca26 efi_loader: Rename sections to allow for implicit data
Some times gcc may generate data that is then used within code that may
be part of an efi runtime section. That data could be jump tables,
constants or strings.

In order to make sure we catch these, we need to ensure that gcc emits
them into a section that we can relocate together with all the other
efi runtime bits. This only works if the -ffunction-sections and
-fdata-sections flags are passed and the efi runtime functions are
in a section that starts with ".text".

Up to now we had all efi runtime bits in sections that did not
interfere with the normal section naming scheme, but this forces
us to do so. Hence we need to move the efi_loader text/data/rodata
sections before the global *(.text*) catch-all section.

With this patch in place, we should hopefully have an easier time
to extend the efi runtime functionality in the future.

Signed-off-by: Alexander Graf <agraf@suse.de>
[agraf: Fix x86_64 breakage]
2018-07-25 14:57:44 +02:00
Tom Rini
4ac5df4b41 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-07-03 23:09:34 -04:00
Andre Przywara
be0d217952 arm: timer: sunxi: add Allwinner timer erratum workaround
The Allwinner A64 SoCs suffers from an arch timer implementation erratum,
where sometimes the lower 11 bits of the counter value erroneously
become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and
backwards, with the latter one often showing weird behaviour.
Port the workaround proposed for Linux to U-Boot and activate it for all
A64 boards.
This fixes crashes when accessing MMC devices (SD cards), caused by a
recent change to actually use the counter value for timeout checks.

Fixes: 5ff8e54888 ("sunxi: improve throughput
in the sunxi_mmc driver")

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
2018-07-03 22:00:00 +05:30
Andre Przywara
38651588d3 arm: timer: factor out FSL arch timer erratum workaround
At the moment we have the workaround for the Freescale arch timer
erratum A-008585 merged into the generic timer_read_counter() routine.
Split those two up, so that we can add other errata workaround more
easily. Also add an explaining comment on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
2018-07-03 21:59:46 +05:30
Michal Simek
20b016a336 common: Fix cpu nr type which is always unsigned type
cpu_cmd() is reading cpu number via simple_strtoul() which is always
unsigned type.
Platform code implementations are not expecting that nr can be negative
and there is not checking in the code for that too.

This patch is using u32 type for cpu number to make sure that platform
code get proper value range.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-19 07:31:45 -04:00
Tom Rini
d94e89c765 Xilinx fixes for v2018.07-rc2
Zynq:
 - Fix missing watchdog header
 - DT fixes
 
 ZynqMP:
 - emmc configuration split
 - Enable SPD
 - Fix PMUFW_INIT_FILE logic
 - Coverity fixes in SoC code
 
 timer
 - Add timer_get_boot_us
 
 mmc:
 - Fix MMC HS200 tuning command
 
 serial:
 - Fix scrabled chars with OF_LIVE
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Merge tag 'xilinx-for-v2018.07-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx fixes for v2018.07-rc2

Zynq:
- Fix missing watchdog header
- DT fixes

ZynqMP:
- emmc configuration split
- Enable SPD
- Fix PMUFW_INIT_FILE logic
- Coverity fixes in SoC code

timer
- Add timer_get_boot_us

mmc:
- Fix MMC HS200 tuning command

serial:
- Fix scrabled chars with OF_LIVE
2018-06-15 09:38:06 -04:00
Michal Simek
e3c26b8d95 arm64: zynqmp: Check return value in zynqmp_mmio_rawwrite()
There should be return value check from zynqmp_mmio_read() in
zynqmp_mmio_rawwrite() to make sure that errors are propagated properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:05 +02:00
Alexander Graf
e4679489c3 efi_loader: Convert runtime reset from switch to if statements
We currently handle the UEFI runtime reset / power off case handling via
a switch statement. Compilers (gcc in my case) may opt to handle these via
jump tables which they may conveniently put into .rodata which is not part
of the runtime section, so it will be unreachable when executed.

Fix this by just converting the switch statement into an if/else statement.
It produces smaller code that is faster and also correct because we no
longer refer .rodata from efi runtime code.

Reported-by: Andreas Färber <aferber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-06-14 10:52:14 +02:00
Bhaskar Upadhaya
9629ccdde7 board: ls1012a: FRWY-LS1012A board support
FRWY-LS1012A belongs to LS1012A family with features 2 1G SGMII PFE
MAC, Micro SD, USB 3.0, DDR, QuadSPI, Audio, UART.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
[yorks: rebase and fix SPDX tag]
[yorks: fix board/freescale/ls1012afrdm/Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-06-11 12:34:45 -07:00
Bhaskar Upadhaya
7191d45348 board: Kconfig: Re-Arrangement of PPA firmware and header addresses
PPA firmware and header address may vary depending upon different
boards, configure ppa firmware and header address in board specific
Kconfig.

Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-06-08 16:43:19 -07:00
Rajan Vaja
6189f76ae8 soc: zynqmp: Update required API version to 1.0
Existing EEMI version is to as 1.0 (available from xilinx v2018.1
version). Update required API version to match with EEMI API version.

New PMUFW version is required for operations with programmable logic.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-31 13:50:39 +02:00
Michal Simek
8dd94a8fe5 arm64: zynqmp: Get rid of emulation platforms
ZynqMP emulation platforms are no longer tested and supported that's why
remove macros and code around.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-31 13:50:39 +02:00
Michal Simek
d0f855f221 arm64: timer: Create timer_get_bootus for bootstage support
Implement timer_get_boot_us() based on available functions to support
bootstage command.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-23 22:06:41 -04:00
Tom Rini
3b52847a45 Xilinx changes for v2018.07
microblaze:
 - Align defconfig
 
 zynq:
 - Rework fpga initialization and cpuinfo handling
 
 zynqmp:
 - Add ZynqMP R5 support
 - Wire and enable watchdog on zcu100-revC
 - Setup MMU map for DDR at run time
 - Show board info based on DT and cleanup IDENT_STRING
 
 zynqmp tools:
 - Add read partition support
 - Add initial support for Xilinx bif format for boot.bin generation
 
 mmc:
 - Fix get_timer usage on 64bit cpus
 - Add support for SD3.0 UHS mode
 
 nand-zynq:
 - Add support for 16bit buswidth
 - Use address cycles from onfi params
 
 scsi:
 - convert ceva sata to UCLASS_AHCI
 
 timer:
 - Add Cadence TTC for ZynqMP r5
 
 watchdog:
 - Minor cadence driver cleanup
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Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING

zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation

mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode

nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params

scsi:
- convert ceva sata to UCLASS_AHCI

timer:
- Add Cadence TTC for ZynqMP r5

watchdog:
- Minor cadence driver cleanup
2018-05-11 11:45:28 -04:00
Nitin Jain
0678941ae5 arm64: zynqmp: Setup MMU map for DDR at run time
This patch fills the MMU map for DDR at run time based on information read
from Device Tree or automatically detected from static configuration.

The patch is needed because for systems which has for example 1GB of memory
but MMU map is 2GB there could be spurious accesses which was seen in past
when mapping is not fitting with actual memory installed.

Signed-off-by: Nitin Jain <nitin.jain@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Hou Zhiqiang
8b40f22900 armv8/fsl-lsch2: make the workaround for PIN MUX erratum A010539 robust
Mask HRESET_B after cleared the the RCW_SRC, because in the workaround
we override the RCW_SRC and if HRESET_B is issued after the override
then SoC cannot find valid RCW as the RCW_SRC was overwritten and
result in hang. So we need to mask HRESET_B in case user asserts it,
and the PORESET_B should be asserted which leads to resampling of
cfg_rcw_src pins and loading of correct RCW_SRC.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Hou Zhiqiang
945fad57be armv8/fsl-lsch2: correct QMAN clock
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Sumit Garg
8044900a5b armv8: sec_firmware: Add support for multiple loadables
Enable support for multiple loadable images in SEC firmware FIT image.
Also add example "sec_firmware_ppa.its" file.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Ruchika Gupta
b6bb93de75 armv8: sec_firmware: Remove JR3 from device tree node in all cases
JR3 was getting removed from device tree only if random number
generation was successful. However, if SEC firmware is present,
JR3 should be removed from device tree node irrespective of the
random seed generation as SEC firmware reserves it for it's use.
Not removing it in case of random number generation failure causes
the kernel to crash.

Random number generation was being called twice. This is not
required. If SEC firmware is running, SIP call can be made to the SEC
firmware to get the random number. This call itself would return
failure if function is not supported. Duplicate calling of random
number generation function has been removed.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Sriram Dash
bda33d3c6c armv8: layerscape: Avoid code duplication for TZASC Instantiation
TZASC controller configurations are similar. Put them in a macro and
avoid code duplication.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Andre Przywara
7842b6a91e arm: move SYS_ARCH_TIMER to KConfig
SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch
timer) in U-Boot.
At the moment it is mandatory for ARMv8 and used by a few ARMv7 boards.
Add a proper Kconfig symbol to express this dependency properly,
allowing certain board configuration to later disable arch timer in case
there are any problems with it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[tuomas: rebase + fix conflicts and resync with moveconfig & use select]
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2018-04-28 18:30:43 -04:00
Masahiro Yamada
7325f6cfdc distro: use imply to enable DISTRO_DEFAULTS as SoC default
The default of DISTRO_DEFAULTS is messy.  Using the 'imply' keyword
is equivalent and cleaner.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-28 10:42:35 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Tom Rini
ebca902aeb Merge git://git.denx.de/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-15 08:43:50 -04:00
Heinrich Schuchardt
482fc90c0a efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC
EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the
EFI service ResetSystem. The missing definition is added. The value has to
handled in efi_reset_system().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-04 11:00:07 +02:00
Heinrich Schuchardt
22c793e6a2 efi_loader: exit status for efi_reset_system_init
efi_reset_system_init provides the architecture or board specific
initialization of the EFI subsystem. Errors should be caught and
signalled by a return code.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-04 11:00:06 +02:00
Sriram Dash
942ecc8bd8 drivers: i2c: mxc: Update SYS_I2C_MXC_I2C support in Kconfig
NXP layerscape platforms like ls1088a, ls2088a
uses MXC I2C Controller.
-Remove dependency of MX6 for the same.

Update related configs to use Kconfig file.
-Add SYS_I2C_MXC_I2C1,_I2C2,_I2C3,_I2C4 in Kconfig
-Add CONFIG_SYS_MXC_I2C1_SPEED,_I2C2_,_I2C3_,_I2C4_ in Kconfig
-Add CONFIG_SYS_MXC_I2C1_SLAVE,_I2C2_,_I2C3_,_I2C4_ in Kconfig

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2018-03-29 17:20:42 +02:00
Michal Simek
1cf6cac4d1 arm64: zynqmp: Enable newer pmufw versions
As of now newer pmufw is keeping old interfaces. That's why permit
u-boot to run on newer version. Recommended version will be setup later.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:43 +01:00
Calvin Johnson
c4dc68b02f armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-22 15:05:30 -05:00
Masahiro Yamada
b08c8c4870 libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -> include/linux/libfdt.h
  include/libfdt_env.h     -> include/linux/libfdt_env.h

and replaces include directives:
  #include <libfdt.h>      -> #include <linux/libfdt.h>
  #include <libfdt_env.h>  -> #include <linux/libfdt_env.h>

Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-05 10:16:28 -05:00
Vipul Kumar
5dc5a53c5e mmc: Added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ
This patch added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ
and enabled it in respective defconfig.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-01 16:44:10 +01:00
Sriram Dash
30cf7f818d armv8: Remove dependency of SERDES for LSCH2 and LSCH3
Remove dependency of SYS_HAS_SERDES for Layerscape Chasis 2 and
Layerscape Chasis 3.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-02-09 08:33:21 -08:00
Lukasz Majewski
d695d66278 spl: eMMC/SD: Provide one __weak spl_boot_mode() function
The goal of this patch is to clean up the code related to choosing SPL
MMC boot mode.

The spl_boot_mode() now is called only in spl_mmc_load_image() function,
which is only compiled in if CONFIG_SPL_MMC_SUPPORT is enabled.

To achieve the goal, all per mach/arch implementations eligible for
unification has been replaced with one __weak implementation.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Michal Simek <michal.simek@xilinx.com> (For ZynqMP)
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-02-07 22:06:18 -05:00
Tom Rini
ab21ecef7a Xilinx changes for v2018.03
- Several Kconfig fixes (also moving configs to defconfigs)
 - Some DTS updates
 - ZynqMP psu rework based on Zynq concept
 - Add low level initialization for zc770 and zcu102
 - Add support for Zynq zc770 x16 nand configuration
 - Add mini nand/emmc ZynqMP targets
 - Some arasan nand changes
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Merge tag 'xilinx-for-v2018.03' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.03

- Several Kconfig fixes (also moving configs to defconfigs)
- Some DTS updates
- ZynqMP psu rework based on Zynq concept
- Add low level initialization for zc770 and zcu102
- Add support for Zynq zc770 x16 nand configuration
- Add mini nand/emmc ZynqMP targets
- Some arasan nand changes
2018-01-31 07:10:55 -05:00
Ulf Magnusson
e7563c204e arm64: zynqmp: Fix misspelled choice default
There is no JTAG symbol in the "Boot mode" choice. JTAG_MODE was
probably intended.

No functional changes. Kconfig choices fall back on using the first
(visible) symbol in the choice as the default if the default symbol is
not visible.

Discovered in Kconfiglib (https://github.com/ulfalizer/Kconfiglib),
which prints the following warning:

	warning: the default selection JTAG (undefined) of <choice> (defined at arch/arm/cpu/armv8/zynqmp/Kconfig:107) is not contained in the choice

I've added a corresponding warning to the C tools too, which is
currently in linux-next: https://patchwork.kernel.org/patch/9983667/

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:29:52 +01:00
Michal Simek
2ad341ed7d arm64: zynqmp: Prepare psu_init rework
Move generic functions to common location psu_spl_init.c. Function
declarations are added to private header.
These changes are done in connection to the fact that still files from
HDF can be copied over and compilation should pass.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:29:18 +01:00
Siva Durga Prasad Paladugu
3b644a3c2f arm64: zynqmp: Provide a config to not map DDR region in MMU table
DDR less systems are possible for configuration like mini qspi
and making DDR region as normal memory may cause speculative
access which results u-boot hang if DDR is absent. So, this
patch fixes the issue by not making DDR memory region
entry into MMU table.

Future solution is to prepare MMU table per memory node in dts instead
of hard code DDR addresses.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:29:03 +01:00
Michal Simek
f32e79f159 arm64: zynqmp: Propagate error value from psu_init()
psu_init() returns int which wasn't declared and checked.
The patch is fixing function declarations and code to handle return
values properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:28:59 +01:00
Michal Simek
7109930a70 arm64: zynqmp: Remove whitespaces in psu_init() comment
Remove additional spaces before comment.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:28:58 +01:00
Anders Hedlund
501fbc6744 armv8: zynqmp: Map PCIe High as device memory
Set the 8GB PCIe High area as device memory.
Also extend the DDR High area to cover the full 32GB range.

Signed-off-by: Anders Hedlund <anders.j.hedlund@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:28:40 +01:00
Rajesh Bhagat
1fab98fb90 common: board_f: vid: Add VID specific API to adjust core voltage
Adds a VID specific API in init_sequence_f and spl code flow
namely init_func_vid which is required to adjust core voltage.

VID specific code is required in spl, hence moving flag CONFIG_VID
out of spl flags.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-23 11:20:46 -08:00
Rajesh Bhagat
a1f95ff7d7 armv8: lsch3: Add serdes and DDR voltage setup
Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-23 11:18:12 -08:00
Tom Rini
086ebcd40e Merge git://git.denx.de/u-boot-fsl-qoriq 2018-01-17 13:48:35 -05:00
Andre Przywara
4d4db83d18 armv8: secure firmware: fix incorrect unit address in node name
The DT spec demands a unit-address in a node name to match the "reg"
property in that node. Newer dtc versions will throw warnings if this is
not the case.
Remove the unit address from the config node name when U-Boot deals with
secure firmware FIT images.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-01-15 18:29:21 -07:00
Andre Przywara
971a54193c doc: fix incorrect usage of DT node unit address
The DT spec demands a unit-address in a node name to match the "reg"
property in that node. Newer dtc versions will throw warnings if this is
not the case.
Fix all occurences in various documentation files where this was not
observed, to not give bad examples to the reader.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-01-15 18:29:21 -07:00
Zhang Ying-22455
958b2ed526 armv8/ls1088a: configure PMU's PCTBENR to enable WDT
The SP805-WDT module on LS1088A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.

Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15 12:44:23 -08:00
Bhaskar Upadhaya
b0ce187b1f board: ls1012a: LS1012A-2G5RDB board support
LS1012A-2G5RDB belongs to LS1012A family with features 2 2.5G SGMII
PFE MAC, SATA, USB 2.0/3.0, WiFi DDR, eMMC, QuadSPI, UART.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15 11:56:33 -08:00
Bhaskar Upadhaya
bdc48ec61e armv8/kconfig: Align boards of same family at one place
Align boards belonging to LS1012A, LS2080A SoC at one place.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15 11:55:54 -08:00
Stephen Warren
8163faf952 ARMv8: add optional Linux kernel image header
Allow placing a Linux kernel image header at the start of the U-Boot
binary. This is useful since the image header reports the amount of memory
(BSS and similar) that U-Boot needs to use, but that isn't part of the
binary size. This can be used by the code that loads U-Boot into memory to
determine where to load U-Boot, based on other users of memory.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12 09:52:11 -07:00
Sumit Garg
dcb081ba95 armv8: fsl-layerscape: SPL size reduction
Compile-off mp.c and libfdt.c in case of SPL build. SPL size reduces
by approx 2k.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10 12:31:19 -08:00
Alison Wang
ab0ab54e49 armv8: Implement workaround for Cortex-A53 erratum 855873
855873: An eviction might overtake a cache clean operation
Workaround: The erratum can be avoided by upgrading cache clean by
address operations to cache clean and invalidate operations. For
Cortex-A53 r0p3 and later release, this can be achieved by setting
CPUACTLR.ENDCCASCI to 1.

This patch is to implement the workaround for this erratum.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10 12:29:57 -08:00
Ahmed Mansour
44262327aa drivers/misc: Share qbman init between archs
This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware

- Create new board/freescale/common/fsl_portals.c to house shared
  device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
  both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
  setup to disable interrupts on all QMan and BMan portals. It is
  needed because the interrupts are enabled by default for all portals
  including unused/uninitialised portals. When the kernel attempts to
  go to deep sleep the unused portals prevent it from doing so

Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10 12:28:47 -08:00
Yuantian Tang
1b76f3b8ab armv8: layerscape: sata: refine port register configuration
Sata registers PP2C and PP3C are used to control the configuration
of the PHY control OOB timing for the COMINIT/COMWAKE parameters
respectively. Calculate those parameters from port clock frequency.
Overwrite those registers with calculated values to get better OOB
timing.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10 12:28:14 -08:00
Ashish Kumar
fa60abc6e6 armv8: ls1088 : MC alignment should always be fixed to 512MB
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10 12:27:36 -08:00
Masahiro Yamada
7e3caa81e0 Move CONFIG_PANIC_HANG to Kconfig
Freescale (NXP) boards have lots of defconfig files per board.
I used "imply PANIC_HANG" for them.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-26 13:10:24 -05:00
York Sun
f440aba172 armv8: ls2085a: Update README file for NAND boot
Update README file to note LS2088A and LS1088A don't support booting
from NAND flash.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-12-18 08:25:07 -08:00
Wenbin song
20c7305101 armv8: layerscape: Discard the needless cpu nodes
Using "cpu_pos_mask()" function to detect the real online cpus,
and discard the needless cpu nodes on kernel dts.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-13 13:40:29 -08:00
Wenbin song
a8f33034f2 armv8: ls1043a/ls2080a: check SoC by device ID
Check LS1043A/LS2080a by device ID without using personality ID to
determine revision number. This check applies to all various
personalities of the same SoC family.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-13 13:40:29 -08:00
Tuomas Tynkkynen
9fd95ef0d3 ata: Migrate CONFIG_SCSI_AHCI to Kconfig
And use 'imply' liberally.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-12-12 18:13:19 -05:00
Udit Agarwal
30c41d2191 armv8: LS1088A_QSPI: SECURE_BOOT: Images validation
Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC
phase using esbc_validate command.

Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment

Add header address for PPA to be validated during ESBC phase for
LS1088A platform based on LAyerscape Chasis 3.

Moves sec_init prior to ppa_init as for validation of PPA sec must
be initialised before the PPA is initialised.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-06 14:55:17 -08:00