Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2025-02-18 06:58:54 +00:00
Code Issues Projects Releases Packages Wiki Activity

armv8: Implement workaround for Cortex-A53 erratum 855873

Browse source 
855873: An eviction might overtake a cache clean operation
Workaround: The erratum can be avoided by upgrading cache clean by
address operations to cache clean and invalidate operations. For
Cortex-A53 r0p3 and later release, this can be achieved by setting
CPUACTLR.ENDCCASCI to 1.

This patch is to implement the workaround for this erratum.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Alison Wang 2017-12-28 13:00:55 +08:00 • committed by York Sun
parent 541d57663f
commit ab0ab54e49
3 changed files with 29 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
arch/arm/Kconfig
View file

@ -122,6 +122,9 @@ config ARM_ERRATA_852421
config ARM_ERRATA_852423
bool
config ARM_ERRATA_855873
bool
config CPU_ARM720T
bool
select SYS_CACHE_SHIFT_5

3
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View file

@ -1,6 +1,7 @@
config ARCH_LS1012A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873
select FSL_LSCH2
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
@ -16,6 +17,7 @@ config ARCH_LS1012A
config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873
select FSL_LSCH2
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
@ -68,6 +70,7 @@ config ARCH_LS1046A
config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873
select FSL_LSCH3
select SYS_FSL_DDR
select SYS_FSL_DDR_LE

24
arch/arm/cpu/armv8/start.S
View file

@ -196,7 +196,10 @@ reset_sctrl:
WEAK(apply_core_errata)
mov x29, lr /* Save LR */
/* For now, we support Cortex-A57 specific errata only */
/* For now, we support Cortex-A53, Cortex-A57 specific errata */
/* Check if we are running on a Cortex-A53 core */
branch_if_a53_core x0, apply_a53_core_errata
/* Check if we are running on a Cortex-A57 core */
branch_if_a57_core x0, apply_a57_core_errata
@ -204,6 +207,25 @@ WEAK(apply_core_errata)
mov lr, x29 /* Restore LR */
ret
apply_a53_core_errata:
#ifdef CONFIG_ARM_ERRATA_855873
mrs x0, midr_el1
tst x0, #(0xf << 20)
b.ne 0b
mrs x0, midr_el1
and x0, x0, #0xf
cmp x0, #3
b.lt 0b
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Enable data cache clean as data cache clean/invalidate */
orr x0, x0, #1 << 44
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
b 0b
apply_a57_core_errata:
#ifdef CONFIG_ARM_ERRATA_828024