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armv8: layerscape: sata: refine port register configuration
Sata registers PP2C and PP3C are used to control the configuration of the PHY control OOB timing for the COMINIT/COMWAKE parameters respectively. Calculate those parameters from port clock frequency. Overwrite those registers with calculated values to get better OOB timing. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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2 changed files with 8 additions and 0 deletions
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@ -341,6 +341,8 @@ int sata_init(void)
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#ifdef CONFIG_SYS_SATA2
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ccsr_ahci = (void *)CONFIG_SYS_SATA2;
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
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out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
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#endif
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@ -348,6 +350,8 @@ int sata_init(void)
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#ifdef CONFIG_SYS_SATA1
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ccsr_ahci = (void *)CONFIG_SYS_SATA1;
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
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out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
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@ -368,6 +372,8 @@ int sata_init(void)
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/* Disable SATA ECC */
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out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
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out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
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@ -88,6 +88,8 @@ struct cpu_type {
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/* ahci port register default value */
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#define AHCI_PORT_PHY_1_CFG 0xa003fffe
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#define AHCI_PORT_PHY2_CFG 0x28184d1f
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#define AHCI_PORT_PHY3_CFG 0x0e081509
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#define AHCI_PORT_TRANS_CFG 0x08000029
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#define AHCI_PORT_AXICC_CFG 0x3fffffff
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