timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As the function 'sprintf' does not check buffer boundaries but outputs
to the buffer 'enet' of fixed size (16), this patch removes the function
'sprintf', and uses 'strcpy' instead. It will assign the character
arrays 'enet' and 'phy' the corresponding character strings.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
hab_status command returns a memory dump of the hab event log. But the
raw data is not human-readable. Parsing such data into readable event
will help to minimize debbuging time.
Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.
Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
enable_spi_clock does the same thing with enable_cspi_clock, so
remove enable_cspi_clock.
Remove enable_cspi_clock prototype in header file
convert cm_fx6/spl.c to use enable_spi_clk
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The A33 adds a pinmux function for UART0 in the PB pin group.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The original code was configuring the external pins after enabling
the R_PIO clock, which meant the configuration never made it to
the pin controller the first time in SPL.
Why this was working before is uncertain. Maybe the state was left
from a previous boot sequence, or RSB just happened to be the default
configuration. However with some A33 chips, SPL failed to configure
the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev
board.
Reordering the calls fixed this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function
index defines") renamed all GPIO index defines, but missed the PORT F
UART0 setup functions.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads & clock for the controller.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This reverts commit f76eba38b3.
This patch did not have a full and proper copyright/S-o-b chain.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Conflicts:
include/configs/sun6i.h
include/configs/sun8i.h
The DIGPROG register map:
23 ------- 16 | 15 ------ 8 | 7 --- 0 |
Major upper | Major Lower | Minor |
We also need to account for Major Lower.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This is the first patch to remove the
CONFIG_SYS_EXTRA_OPTIONS.
This patch implements CPU type selection from Kconfig.
Further Kconfig stuff is added later.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.
Remove the configs that behave this way from the archs.
A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:
SPIFLASH
DISPLAY_BOARDINFO
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF controller should not be the master of the reset
signal and an external entity might be in control of things.
The default configuration of Linux on TI evms involve not powering off
the voltage rails (due to various reasons including reliability concerns)
and must not allow DDR reset to be controlled by EMIF. On platforms
where external entity might control the reset signal, this configuration
will be a "dont care".
Fixes: 536d874708 ("ARM: DRA7: Update DDR IO registers")
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently on sun6i after a "reset" the prompt returns and the user can
even type stuff until the watchdog triggers and does the actual reset.
This is somewhat unexpected behavior for the "reset" command, this
commit adds an endless loop to wait for the watchdog to trigger so that
we do not return to the prompt.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.
Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet. In other cases
update the call to be as functional as before and check an already
programmed value in.
Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On AM57xx evm I2C5 is used to detect the LCD board by reading the
EEPROM present on the bus.
Enable i2c5 clocks to help that.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
In addition to the regular mux configuration, certain pins of DRA7
require to have "manual mode" also programmed, when predefined
delay characteristics cannot be used for the interface.
struct iodelay_cfg_entry is introduced for populating
manual mode IO timings.
For configuring manual mode, along with the normal pad
configuration do the following steps:
- Select MODESELECT field of each assocaited PAD.
CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux)
- Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL.
And pass the offset of the CFG_XXX register in iodelay_cfg_entry.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
On DRA7, in addition to the regular muxing of pins, an additional
hardware module called IODelay which is also expected to be
configured. This "IODelay" module has it's own register space that is
independent of the control module.
It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay recalibration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do muxing as part of IOdelay recalibration.
IODELAY recalibration sequence:
- Complete AVS voltage change on VDD_CORE_L
- Unlock IODLAY config registers.
- Perform IO delay calibration with predefined values.
- Isolate all the IOs
- Update the delay mechanism for each IO with new calibrated values.
- Configure PAD configuration registers
- De-isolate all the IOs.
- Relock IODELAY config registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
We plan to enable device tree in SPL by default. Before doing this,
explicitly disable it for all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is used before jumping to U-Boot, but in that case we don't
always want to disable caches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
This fixes ethernet no longer working on boards which use a gpio to enable
the phy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Before this commit the code for determining the disconnect threshold was
checking for sun4i or sun6i assuming that those where the exception and
that newer SoCs use a disconnect threshold of 2 like sun7i does.
But it turns out that newer SoCs actually use a disconnect threshold of 3
and sun5i and sun7i are the exceptions, so check for those instead.
Here are the settings from the various Allwinner SDK sources:
sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
Note this commit makes no functional changes for sun4i - sun7i, and
changes the disconnect threshold for sun8i to match what Allwinner uses.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This updates r8a7790 QoS to revision 0.973.
This commit can changed from KConfig to fit contents of the QoS.
Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
sun8i can share the PSCI backend with sun6i. Only difference
is sun8i does not have CPU power clamp controls.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This adds PSCI support for sun6i. So far it only supports
the PWR_ON method.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The PSCI code only works for sun7i. Rename it with _sun7i suffix,
and build only if building for sun7i.
This paves the way for adding PSCI support for other platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The PSCI CPU_ON code accesses quite a few registers. Document
their names to make it easier to cross reference.
Also explain "lock cpu" and "unlock cpu" as enabling/disabling
debug access.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit adds support to the sunxi SPL to load u-boot from the internal
NAND. Note this only adds support to access the boot partitions to load
u-boot, full NAND support to load the kernel, etc. from the nand data
partition will come later.
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add initial sun9i (A80) support, only uart + mmc are supported for now.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The latest versions of the fel tool support loading normal u-boot builds
directly, and this is now the preferred way to use the fel boot method.
This commit removes support for the old deprecated standalone fel builds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Unlike the A31 and the A23 the A33 actually has a SID inside the SoC again,
but sid[3] is 0 (at least on some SoCs), so it is better to use the axp221
sid.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION
setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of
only in dram_sun4i.c and hardcoding odt_en elsewhere.
Note this commit makes no functional changes for existing boards,
its purpose is to allow changing the odt_en value on future A33 boards.
For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs
currently do) this patch turns on odt for both the DQ and the DQS lines,
whereas previously it was possibly (but not desirable) to turn odt on only
for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
When porting the allwinner dram init code to u-boot we missed some code
setting an extra bit when doing auto dram config.
This commits add this bit, fixing dram init not working on the ga10h
10" a33 tablet which I'm bringing up atm.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for UART2 (2-pin version but note that RTS/CTS pins are available
pn that port for possible future use), can be selected in config
by using CONFIG_CONS_INDEX=3
Signed-off-by: Laurent Itti <laurentitti@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
This has been tested with IMX6 Automative and Industrial parts.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.
Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which
doesn't take into account DDR3 memory limitations.
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Upstream Linux is broken with default configs when PSCI, thus non-secure
mode is enabled. So the user should explicitly enable this mode, e.g.
when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to
use). We can revert this workaround once Linux got fixed.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These registers can be used to prevent non-secure world from accessing a
megabyte aligned region of RAM, use them to protect the u-boot secure monitor
code.
At first I tried to do this from s_init(), however this inexplicably causes
u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine.
So instead I have added a new weak arch function protect_secure_section()
called from relocate_secure_section() and reserved the region there. This is
better overall since it defers the reservation until after the sec vs. non-sec
decision (which can be influenced by an envvar) has been made when booting the
os.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
[Jan: tiny style adjustment]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra boards will have to initialize power management for the PSCI
support this way.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.
Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons
This will be used in a subsequent patch for Jetson-TK1.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Use a per-CPU variable for saving the target PC during CPU_ON
operations. This allows us to run this service independently on targets
that have more than 2 cores and also core-local power control.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This algorithm will be useful on Tegra as well, plus we will need it for
making _psci_target_pc per-CPU.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.
As with psci_disable_smp, also the enabling is designed to be overloaded
in cased SMP is not controlled via ACTLR.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely
cache disabling and flushing, clrex and the disabling of SMP for the
dying CPU. These steps are apparently generic for ARMv7 and will be
reused for Tegra124 support.
As the way of disabled SMP is not architectural, though commonly done
via ACLTR, the related function can be overloaded.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Will be required for obtaining the ID of the current CPU in shared PSCI
functions. The default implementation requires a dense ID space and only
supports a single cluster. Therefore, the functions can be overloaded in
cases where these assumptions do not hold.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.
CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: York Sun <yorksun@freescale.com>
CC: Steve Rae <srae@broadcom.com>
CC: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
Because all the SOCFPGA boards define CONFIG_SPL_FRAMEWORK
(see include/configs/socfpga_common.h), u-boot.img is automatically
added to the target image list by the top Makefile.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The compiler option "-Iboard/$(VENDOR)/$(BOARD)" just exists here
for iocsr_config.c to be able to include iocsr_config.h.
Use "..." instead of <...> to include a header in the same directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Move arch/arm/cpu/armv7armada-xp/* -> arch/arm/mach-mvebu/*
Since this platform will be extended to support other Marvell SoC's as
well, lets rename it directly to mvebu.
This will be used by the upcoming Armada 38x suport (A38x).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Once we add support for the ohci controller the phy-init and phy-power-on
functions may be called twice (once by the ehci code and once by the ohci
code) protect them against this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The 2/3 usb-phys on the sunxi SoCs are really a single separate functional
block, and are modelled as such in devicetree. So once we've moved all the
sunxi usb code to the driver-model then phy_probe will be called once
for the entire block from the driver-model enumeration code.
Move to this now as this also avoids problems with phy_probe being called
multiple times once we introduce ohci support. This also allows us to get rid
of the sunxi_usb_phy_enabled_count variable as phy_probe now is guaranteed
to be called only once.
Since we're effectively rewriting the probe / remove functions, move them
to the end of the file while we are at it, as that is the most logical place
for them.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The usbc.? files now only contain usb-phy related code, rename them to make
this clear.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Rename the sunxi_usbc_foo functions to sunxi_usb_phy_bar to make it clear
that these are usb-phy functions. Also change the verbs & nouns in the suffix
to match the verbs & nouns used in the Linux kernels generic phy framework.
This patch purely renames things, it contains no functional changes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is the only function left in sunxi/usbc.c which is not phy related,
so remove it.
This is a preparation patch for turning the usbc.c code into a proper
usb phy driver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sunxi "usbc" code is mostly about phy setup, but currently also sets up
the host controller clocks, which is something which really belongs in the
host controller drivers, so move it there.
This is a preparation patch for moving the sunxi ehci code to the driver
model and for adding ohci support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
All sunxi boards now use the driver-model, so remove the non driver-model
code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Modify the sunxi-emac eth driver to support driver model.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Stefan Roese <sr@denx.de>
Add support for the axp152 and axp209 PMICs to the pmic register access
helpers. This is a preparation patch for moving the axp gpio code to a
separate gpio driver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move the register helpers used to access the registers via p2wi resp.
rsb bus on the otherwise identical axp221 and axp223 pmics to a separate
file, so that they can be used by the upcoming standalone axp gpio driver
too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The driver-model gpio functions may return another value then -1 as error,
make the sunxi usbc properly handle this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Enable full support for the A33 SoC including display, otg-usb, etc.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for the new second DRAM PLL found on the A33 SoC.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is a preparation patch for adding A33 support, which will have a
mach name of sun8i-a33.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sun6i and newer (derived) SoCs such as the sun8i-a23, sun8i-a33 and sun9i
have a various things in common, like having separate ahb reset control
registers, the SID living inside the pmic, custom pmic busses, new style
watchdog, etc.
This commit introduces a new hidden SUNXI_GEN_SUN6I Kconfig bool which can be
used to check for these features avoiding the need for an ever growing list
of "#if defined CONFIG_MACH_SUN?I" conditionals as we add support for more
"new style" sunxi SoCs.
Note that this commit changes the behavior of the gmac and hdmi code for
sun8i and the upcoming sun9i devices. This does not matter as sun8i does
not have gmac nor hdmi, and sun9i has new hardware-blocks for these so
the old code will not work there.
Also this is intentional as if a sun8i / sun9i variant which does use the
old hwblocks shows up then the GEN_SUN6I code paths will be the right ones
to use.
For completeness this also adds a SUNXI_GEN_SUN4I bool for A10/A13/A20.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We do not use irqs in u-boot so remove the unused irq field, and all the
#ifdef-ery around the irq initialization.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
There is no reason not to and this make the #ifdef-ery easier to read.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is already invoked a few cycles later in monitor mode by
_secure_monitor (_sunxi_cpu_entry calls _do_nonsec_entry which triggers
_secure_monitor via smc #0). Drop it here, it serves no purpose.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The comment line in arch/arm/cpu/armv7/zynq/config.mk says that
the option "-mfpu=neon" is necessary for compiling lowlevel_init.S.
We do not have to give it to all the source files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fix wrong timer calculation in get_timer_masked incase of
overflow.
This fixes the issue of getting wrong time from get_timer()
calls.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Disable all level shifters before enabling
the PS-to-PL level shifters as it would
be good to disable all level shifters before
enabling the PS-to-PL in order to ensure that
it is in proper state
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We are about to change the location for ps7_init files, breaking the
current work-flows. It is good time to drop the legacy ps7_init.c/h
support.
Going forward, please use ps7_init_gpl.c/h all the time.
If you are still using old Xilinx tools that are only able to
generate ps7_init.c/h, rename them into ps7_init_gpl.c/h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The PicoZed is a System-on-Module board which is marketed as part of
the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000
processor.
This patch adds support that covers all the variants of the PicoZed
including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This
patch set however only covers support for the System-on-Module and does
not cover any extra components that are available on carrier boards
(except those that are fanned out of the module itself).
More information on this board, its variants and available carrier
boards is available at: http://zedboard.org/product/picozed
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Implemented fb_set_reboot_flag() for OMAP5 to set
an environment variable 'dofastboot' when reboot-bootloader called.
This environment variable will be checked in boot command and fastboot
will be called if the variable is set.
If the bootcmd env variable of OMAP5 common is overwritten with board-specific
command, then these changes will not apply.
This was originally intended for DRA7 platform, but now applies to all OMAP5.
Ref:
http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=19da2e436e9806259cf1f4988b9e046ab256bf2c
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Make it check for !CONFIG_ENV_IS_NOWHERE as we can't saveenv()
in that case]
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch populates serial number environment variable from
die_id_0 and die_id_1 register values for DRA7xx boards.
The function is added in omap common code so that this can be re-used.
Serial# environment variable will be useful to show correct
information in "fastboot devices" commands.
Ref:
http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=a6bcaaf67f6e4bcd97808f53d0ceb4b0c04d583c
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit.
In slow-exit mode the DLL is off but in some quiescent state that makes it easy
to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK).
In fast-exist mode the DLL is maintained such that it is ready again in about
3tCK.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f().
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
For SoCFGPA, use the common ARMv7 lowlevel_init. Thus, we can delete the
SoCFPGA lowlevel_init.S file.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add the calls in the spl_board_init to enable SDRAM, timer, and UART.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
These functions will be needed for use by the SPL for enabling the
console and sdram initialization.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Don't store it in a u32.
Don't dereference the bus address as if it were a virtual address
(fixes 284231e49a ("ahci: Support splitting of read transactions
into multiple chunks")).
Fixes crash on boot in MPC8641HPCN_36BIT target.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: York Sun <yorksun@freescale.com>
Move this to Kconfig and clean up board config files that use it. Also
rename it to CONFIG_ETH_DESIGNWARE to fit with the naming that exists
in drivers/net/Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Version 1:
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As mentioned in the previous commit, adding default values in each
Kconfig causes problems because it does not co-exist with the
"depends on" syntax. (Please note this is not a bug of Kconfig.)
We should not do so unless we have a special reason. Actually,
for CONFIG_DM*, we have no good reason to do so.
Generally, CONFIG_DM is not a user-configurable option. Once we
convert a driver into Driver Model, the board only works with Driver
Model, i.e. CONFIG_DM must be always enabled for that board.
So, using "select DM" is more suitable rather than allowing users to
modify it. Another good thing is, Kconfig warns unmet dependencies
for "select" syntax, so we easily notice bugs.
Actually, CONFIG_DM and other related options have been added
without consistency: some into arch/*/Kconfig, some into
board/*/Kconfig, and some into configs/*_defconfig.
This commit prefers "select" and cleans up the following issues.
[1] Never use "CONFIG_DM=n" in defconfig files
It is really rare to add "CONFIG_FOO=n" to disable CONFIG options.
It is more common to use "# CONFIG_FOO is not set". But here, we
do not even have to do it.
Less than half of OMAP3 boards have been converted to Driver Model.
Adding the default values to arch/arm/cpu/armv7/omap3/Kconfig is
weird. Instead, add "select DM" only to appropriate boards, which
eventually eliminates "CONFIG_DM=n", etc.
[2] Delete redundant CONFIGs
Sandbox sets CONFIG_DM in arch/sandbox/Kconfig and defines it again
in configs/sandbox_defconfig.
Likewise, OMAP3 sets CONFIG_DM arch/arm/cpu/armv7/omap3/Kconfig and
defines it also in omap3_beagle_defconfig and devkit8000_defconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Convert Exynos boards over to use driver model for USB. This does not remove
any unnecessary code so far.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between
the two dwc3 controllers present in dra7xx/am43xx and enabled these
clocks in enable_basic_clocks() in hw_data.c. However these clocks
continued to be enabled in board files/driver files for dwc3 host
mode functionality causing compilation break with few configs.
Fixed it here by making all the clocks enabled in enable_basic_clocks()
and removing it from board files/driver files here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This enables ARMv7 barrier operations support when
march=armv7-a is enabled.
Using CP15 barriers causes U-Boot bootm command crash when
transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU.
Using ARMv7 barrier operations instead of the deprecated CP15 barriers
helps to avoid these issues.
Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com>
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
When u-boot boots the board may be powering vbus, we turn off vbus in
sunxi_usbc_request_resources, if we are too quick with reading vusb-detect
after this we may see a residual charge and assume we've an external vusb
connected even though we do not. So when we see an external vusb wait a bit
and try again.
Without this when dealing with a pmic controller vbus and doing "reset" on
the u-boot console the musb host will only init once every other boot, because
the other boot it thinks an external vbus is present, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
On boards which use the pmic to enable/disable vbus on the otg port, the
vbus value is not reset to 0 on reset, as reset only resets the SoC and not
the pmic, so explicitly set vbus to 0 on init (request_resources) by moving
the gpio_direction_output call into request_resources.
For consistency also move the gpio_direction_input call for vbus-detect into
request_resources.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Each hardware feature exposed through the GPIO pin mux is usually using the same
function index (for a given port), so there is no need to define one value per
pin: one value per hardware feature per port is sufficient, avoids duplication
and makes everything easier to understand.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
VBUS detection could be needed not only by the musb code (to prevent host mode),
but also by e.g. gadget drivers to start only when a cable is connected.
In addition, this allows more flexibility in vbus detection, as it could easily
be extended to other USBC indexes. Eventually, this would help making musb
support independent from a hardcoded USB controller index (0).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
VBUS detection and enable is now be used with virtual AXP GPIOs, so all the USB
code has to use GPIO in every case and let sunxi_gpio do the heavy lifting.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Enabled clocks for dwc3 controller and USB PHY present in AM43xx.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Enabled clocks for dwc3 controller and USB PHY present in DRA7.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced
a different method to return from save_boot_params(). The SPL support
for AXP has been pulled and changing to this new method is now
required for SPL to work correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Add support for Inverse Path USB armory board, an open source
flash-drive sized computer based on Freescale i.MX53 SoC.
http://inversepath.com/usbarmory
Signed-off-by: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
Move the MX5 based boards to arch/arm/cpu/armv7/mx5, following the
commit: 89ebc82137
Signed-off-by: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
Back in fc46bae a "clean up" was introduced that intended to reconcile
some of the AM335x codepaths based on how AM43xx operates.
Unfortunately this introduced a regression on the DDR2 platforms. This
was un-noticed on DDR3 (everything except for Beaglebone White) as we
had already populated sdram_config correctly in sequence. This change
brings us back to the older behavior and is fine on all platforms.
Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM
Reported-by: Matt Ranostay <mranostay@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.
This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.
This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
exynos video driver.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Commit 2e82e92526 'Exynos: Clock: Cleanup
soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec
keyboard working again on Samsung Chromebook (snow).
Changes in V2: reorder lines as requested by Joonyoung Shim.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Joonyoung Shim <jy0922.shim@samsung.com>
Reviewed-by: Simon Glass <sjg@chroimum.org>
Tested-by: Simon Glass <sjg@chroimum.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
make the CPU clock selectable via Kconfig
this removes the sunxi specific CONFIG_CLK_FULL_SPEED defined in each
soc header and replaces it's use in board/sunxi/board.c with
CONFIG_SYS_CLK_FREQ from Kconfig which allows us to configure board
specific frequency on boot
Signed-off-by: Iain Paton <ipaton0@gmail.com>
[hdegoede@redhat.com s/CONFIG_SYS_CLK_FREQ/CONFIG_TIMER_CLK_FREQ/ for the
arch-timer clk speed on sun7i to fix mis-compile on sun7i]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
clock_set_pll1 would pick the next highest available cpu clock speed if
a value not in the pre defined table was selected. this potentially
results in overclocking the soc.
reverse the selection method so that we select the next lowest speed
and add the missing 912Mhz setting that's requested by sun7i which also
uses the sun4i clock code.
Signed-off-by: Iain Paton <ipaton0@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The usb0 / otg phy on sunxi boards has a bug where it wrongly detects a
high speed squelch on usb reset deassert when a lo speed device is plugged in.
The android kernel has a work around for this in the form of temporary
disabling the phy's squelch detection on reset deassert, this commit adds
the same workaround to the u-boot sunxi musb code, thereby fixing various usb
lo speed devices not working.
Tested with a (before non working) usb keyboard and a usb 2.4 GHz wireless
keyboard/mouse combo receiver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
BCM2835 (used on Raspberry Pi) and BCM2836 (used on Raspberry Pi 2)
are similar enough. One of the biggest differences is the ARM
processor. It is reasonable to collect the source files into a
single place, arch/arm/mach-bcm283x/.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
This option has a bool type, not hex.
Fix it and enable it if CONFIG_DM is on because Driver Model always
requires malloc memory. Devices are scanned twice, before/after
relocation. CONFIG_SYS_MALLOC_F should be enabled to use malloc
memory before relocation. As it is board-independent, handle it
globally.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
The default value of CONFIG_SYS_MALLOC_F_LEN is defined by ./Kconfig
as 0x400. Each defconfig or Kconfig need not repeat the same value.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
My main motivations for this commit are:
[1] Follow the arch/arm/Makefile style of Linux Kernel
[2] Maintain compiler options systematically
Currently, we give -march=* and -mtune=* options inconsistently:
Only some of the CPUs pass -march=* and -mtune=* options.
By collecting such options into the single place arch/arm/Makefile
we can tell which options are missing at a glance.
[3] Prepare for deprecating arch/*/cpu/*/config.mk
Note:
This commit just moves the compiler options so as not to change
the behavior at all. It does not care about the correctness of
the given options. Fox example, "-march=armv5te" might be better
than "-march=armv4" for ARM946EJS, but it is beyond the scope this
commit. Also, filling the missing -march=* and -tune=* is left
to follow-up patches.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: "David Müller" <d.mueller@elsoft.ch>
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Torsten Koschorrek <koschorrek@synertronixx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported).
It also adds a Kconfig skeleton to later add more SECO board (supporting
SoC and board variants).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Freescale boards are currently all defined in arch/arm/Kconfig, which
makes them hard to detect.
Moreover the MX6 SoC variant (Q, D, DL, S, SL) selection is currently
done via the SYS_EXTRA_OPTIONS option which marked as deprecated.
Move to a more standard way to select sub-architecture and board by
creating a Kconfig under arch/arm/cpu/armv7/mx6 and a new ARCH_MX6
option.
Existing MX6 board definitions should be moved in this new Kconfig in
choice menu, and new boards should be directly declared in this menu.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.
While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.
Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.
While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
621766: Under a specific set of conditions, executing a sequence of
NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
454179: Stale prediction may inhibit target address misprediction on
next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Disable the warm reset and enable the cold reset for a more reliable
restart ('reset'). This is taken from the Linux kernel, see imx_src_init()
in arch/arm/mach-imx/src.c.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
The way the PSCI DT update happens currently means we pull in
<asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in
<asm/io.h> for some non-PSCI related things that header needs to deal
with.
To fix this, we rework the hook slightly. A good portion of
arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI
is needed on ARMv8 we can re-use this by and large. So rename the
current hook to psci_update_dt(), move the prototype to <asm/psci.h> and
add an #ifdef that will make re-use later easier.
Reported-by: York Sun <yorksun@freescale.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: York Sun <yorksun@freescale.com>
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw <hamming|bch8>
where 'hamming' is still the default.
Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
This patch extends OMAP3 support for AM/DM37xx and
introduces the AM3703-based Quipos Cairo board.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently in some cases SDRAM init requires global_data to be available
and soon this will not be available prior to board_init_f(). Adjust the
code paths in these cases to be correct. In some cases we had the SPL
stack be in DDR as we might have large stacks (due to Falcon Mode +
Environment). In these cases switch to CONFIG_SPL_STACK_R. In other
cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these
cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also
in SRAM) so drop those lines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested on Beagleboard, Beagleboard xM
Tested-by: Matt Porter <mporter@konsulko.com>
Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This function has grown into something of a monster. Some boards are setting
up a console and DRAM here in SPL. This requires global_data which should be
set up in one place (crt0.S).
There is no need for SPL to use s_init() for anything since board_init_f()
is called immediately afterwards.
Signed-off-by: Simon Glass <sjg@chromium.org>
If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined,
smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr(
_smp_pen), before code is relocated to secure ram.
So need relocation to secure ram before enable secondary cores.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).
This also provides a big cleanup of the L2 cache init code avoiding
some duplication. The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
time) and left resident in iRAM for the kernel to use when bringing
up additional CPUs. It used configure_l2_ctlr() and
configure_l2_actlr() when it detected it was on an A15. This was
needed (despite the L2 cache registers being shared among all A15s)
because we might have been the first man in after the whole A15
cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
time. Strangely this called configure_l2_ctlr() but not
configure_l2_actlr() which was almost certainly wrong. Given that
we'll call both (see next bullet) later in the boot process it
didn't matter for normal boot, but I guess this is how L2 cache
settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
This should happen at boot time (normally in the SPL except for USB
boot where it happens in main U-Boot).
Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time. For resume time we'd get it
anyway when the 2nd A15 core came up.
Let's make this a whole lot simpler. Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.
Intended net effects of this change (other than cleanup):
* Timings go from before:
data: 0 cycle setup, 3 cycles (0x2) latency
tag: 0 cycle setup, 3 cycles (0x2) latency
after:
data: 1 cycle setup, 4 cycles (0x3) latency
tag: 1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.
One note is that we're still relying on luck to keep low_power_start()
working. The compiler is being nice and not storing anything on the
stack.
Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL. The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
(after it has turned the L2 cache off). This is why the functions
are in a header file instead of lowlevel_init.c.
* Have the kernel save the L2 cache settings of the boot CPU and apply
them to all other CPUs. We get a little lucky here because the old
code was using "|=" to modify the registers and all of the bits that
it's setting are also present in the new settings (!). That means
that when the 2nd CPU in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores do jump to 0x0 but consider following instructions as a Thumb
instructions which in turn makes them loop inside the iROM code instead of
jumping to power_down_core.
This issue is fixed by replacing the "mov pc" instruction with a "bx"
instruction which switches state along with the jump to make the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of "bx" ARM instruction.
"bx" instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switching.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping to wrong address and create undesired results.
Logic of the workaround:
Step-1: iROM code checks value at address 0x2020028.
Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
else, it continues executing normally.
Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
0x2020028 and jump address (pointer to function low_power_start)
in (0x202000+CPUid*4).
Step-4: When secondary cores recieve event signal they jump to this address
and continue execution.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
addresses 0x02020028 & 0x02020004.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and jumps
to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function secondary_cores_configure,
it puts pointer to function power_down_core into 0x02020004
and provides DSB and SEV for all cores so that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Porter is an entry level development board based on R-Car M2 SoC (R8A7791)
This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, SD, USB Host
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
