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Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This was inspired by a patch from Catalin Marinas [1] and also from recent discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring suggested that bootloaders should initialize the cache. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html [2] https://lkml.org/lkml/2015/2/20/199 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> |
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am33xx | ||
bcm281xx | ||
bcmcygnus | ||
bcmnsp | ||
exynos | ||
iproc-common | ||
kona-common | ||
ls102xa | ||
mx5 | ||
mx6 | ||
omap-common | ||
omap3 | ||
omap4 | ||
omap5 | ||
rmobile | ||
s5p-common | ||
s5pc1xx | ||
stv0991 | ||
sunxi | ||
u8500 | ||
vf610 | ||
arch_timer.c | ||
cache_v7.c | ||
config.mk | ||
cp15.c | ||
cpu.c | ||
Kconfig | ||
lowlevel_init.S | ||
Makefile | ||
nonsec_virt.S | ||
psci.S | ||
start.S | ||
syslib.c | ||
virt-dt.c | ||
virt-v7.c |