Commit graph

1194 commits

Author SHA1 Message Date
Jesse Gilles
08f0533a14 ARM: sam9x5: fix ethernet pins in MII mode
Fix pin setting in MII mode

Signed-off-by: Jesse Gilles <jgilles@multitech.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-03-12 13:02:20 +01:00
Bo Shen
fc14fbace4 ARM: at91sam9x5: Using CPU string directly
As the CPU name is not configurable, using CPU string directly

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-03-12 13:02:13 +01:00
Akshay Saraswat
3a0b1dae5b Exynos5: TMU: Add hardware tripping
This adds hardware tripping at 110 degrees celsius which must enable
forced system shutdown in case TMU fails to power off.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 17:07:31 +09:00
Tom Rini
76b40ab41e Merge u-boot/master into u-boot-ti/master
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850).  Resolve these
conflicts manually and comment the #else/#endif lines for clarity.

Conflicts:
	arch/arm/include/asm/arch-davinci/gpio.h
	drivers/gpio/da8xx_gpio.c

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-11 12:16:13 -04:00
Lokesh Vutla
de62688bb6 arm: dra7xx: Add silicon id support for DRA752 soc
Adding CPU detection support for the DRA752 ES1.0 soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:39:57 -04:00
Lokesh Vutla
7831419d7b arm: dra7xx: Add DDR related data for DRA752 ES1.0
DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
8b12f1779e arm: dra7xx: Add control module changes
Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
ea8eff1fe0 arm: dra7xx: clock: Add the dplls data
A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
d4e4129c31 arm: dra7xx: clock: Add the prcm changes
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
d4d986ee27 ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
	 The 1 in wkup domain is not enabled because smart i/os
	 of wkup domain work with default compensation code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
9100edecf8 ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for
OMAP543X SOCs here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
47abc3df70 ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum
Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.

While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x

Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
afc2f9dcf1 ARM: OMAP5: clock: Add the prcm register changes required for ES2.0
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.

So adding the nessecary register changes for the same.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
eed7c0f727 ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
ef1697e99f ARM: OMAP5: Clean up iosettings code
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.

This avoids unnessecary code addition for future socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
c43c8339fe ARM: OMAP4+: Make control module register structure generic
A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
e05a4f1f54 ARM: OMAP4+: Cleanup emif specific files
Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.

These change reduces code addition for future Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
3fcdd4a5f8 ARM: OMAP4+: Clean up the pmic code
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
ee9447bfe3 ARM: OMAP4+: Cleanup the clocks layer
Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.

This helps in addition of a new Soc with minimal
changes.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:09 -04:00
SRICHARAN R
01b753ff7b ARM: OMAP4+: Change the PRCM structure prototype common for all Socs
The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new silicon
revision which has register space changes.

Avoiding this by making the prototye generic and populating the register
addresses seperately for all Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-03-11 11:06:09 -04:00
Lokesh Vutla
9ca8bfea80 ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:09 -04:00
Enric Balletbo i Serra
b51a5e3a0a OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled.
In order to use SPL boot from OneNAND we should initialize the gpmc.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-03-11 11:06:08 -04:00
Enric Balletbo i Serra
66c7f39923 SPL: ONENAND: Fix some ONENAND related defines.
Some ONENAND related defines use the term ONE_NAND instead of
ONENAND, as the technology name is ONENAND this patch replaces
all these defines.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-03-08 16:41:14 -05:00
Nikita Kiryanov
e3913f56a2 omap_hsmmc: add driver check for write protection
Add check for write protection in omap mmc driver.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
e874d5b001 omap_hsmmc: implement driver check for card detection
Implement driver check for card detection.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:13 -05:00
Tom Rini
1c382ead7a am33xx: Update DDR3 EMIF configuration sequence
Based on
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
we need to re-work our sequence in config_sdram slightly to match what
the TRM describes as the correct sequence.  In our current (incorrect)
sequence some edge cases may fail to initalize correctly.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-08 16:41:12 -05:00
Rajeshwari Shinde
a006076b15 EXYNOS5: Add function to enable XXTI clock source
This patch adds funtion to enable XXTI clock source
required by MAX98095 codec.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-08 22:34:18 +09:00
Stephen Warren
8f3937761b ARM: mx6: use common CPU errata config options
Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.S, since it's just duplicated code now.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2013-03-07 18:20:37 +01:00
Fadil Berisha
3e9dc93051 mxs: timrot: Rename local macros
Local macros apply to both iMX23 and iMX28. This patch renames local
macros with attribute MX28 to MXS.

Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:50:55 +01:00
Fadil Berisha
6ecd05d2f5 mxs: timrot: Add support to i.MX23
This patch add timer support to i.MX23 and complete bit fields and values
on regs-timrot.h.
Testet on imx23-olinuxino board.

Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-03-07 17:22:58 +01:00
Otavio Salvador
89075d3f4f mx23: Document the tRAS lockout setting in memory initialization
Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to
enable the 'Fast Auto Pre-Charge' found in the memory chip. The
setting is applied after memory initialization and it is worth
document it.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-03-07 17:22:57 +01:00
Otavio Salvador
a74dbf2734 mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT
The power switch option is compatible with i.MX23 and i.MX28 so the
configration option needs to reflect it. We choose
'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
2013-03-07 17:22:57 +01:00
Marek Vasut
3430e0bd2a mxs: mmc: spi: dma: Better wrap the MXS differences
This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, different clock domain for SSP block and fixes a few minor
bugs.

First of all, the DMA channel mapping is now fixed in dma.h by defining
the actual channel map for both MX23 and MX28. Thus, MX23 now does no
longer use MX28 channel map which was wrong. Also, there is a fix for
MX28 DMA channel map, where the last four channels were incorrect.

Next, because correct DMA channel map is in place, the mxs_dma_init_channel()
call now bases the channel ID starting from SSP port #0. This removes the
need for DMA channel offset being added and cleans up the code. For the
same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus
no need to adjust dma channel number in the driver either.

Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus()
which handles the fact that MX23 has shared SSP clock for both ports, while
MX28 has per-port SSP clock.

Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the
same functionality from MMC and SPI driver into common code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:22:56 +01:00
Marek Vasut
5c2f444c9b mxs: Reset the EMI block on mx23
The real reason for memory instability was the fact that the EMI block
was gated and not reset throughout the boards' operation. This patch
resets the EMI block properly while also reverts the memory voltage bump.
The memory stability issues were caused by the EMI not being reset properly
and thus there is no longer need to run the memory at higher voltage than
it ought to run at.

This partly reverts 8303ed128a .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:22:56 +01:00
Stefano Babic
9cd9b34dc7 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-02-23 10:13:40 +01:00
Albert ARIBAUD
a5627914da Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-02-21 21:30:47 +01:00
Albert ARIBAUD
03268374db Merge 'u-boot-microblaze/mainline/arm' into 'u-boot-arm/master'
This pulls the three following ZYNQ commits into ARM master:

7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board
59c651f4: arm: zynq: Add SLCR support with system reset
00ed3458: arm: zynq: Add lowlevel initialization to C
2013-02-21 16:43:19 +01:00
Holger Hans Peter Freyther
c8876f1c72 mac: Fix the condition check for setting the MAC from the EEPROM
The issue got introduced in a cleanup by Manjunath Hadli in commit
826e99136e. The eth_getenv_enetaddr_by_index
method will validate the MAC addr and if none is set in the environment
0 will be returned. Set the MAC from the eeprom if no valid address
is found in environment.

Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
2013-02-20 08:52:41 -05:00
Rajeshwari Shinde
51ff1eda6f EXYNOS5: Add function to setup set ps hold
This patch adds a function to set ps_hold data driving value high.
This enables the machine to stay powered on even after the initial
power-on condition goes away(e.g. power button).

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-02-20 16:48:17 +09:00
Ilya Yanok
da07c21b77 am33xx: support for booting via usbeth
This patch adds BOOT_DEVICE define for USB booting and fixes
spl_board_init function to call arch_misc_init (this is the place there
musb is initialized).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2013-02-18 13:48:04 -05:00
Otavio Salvador
291b3dcd49 build: imx: Fix 'u-boot.imx' build without full OBJTREE reference
When calling 'make u-boot.imx' the build were failing as it were
expecting the full path for the file; this regression has been
included by commit 71a988a (imximage.cfg: run files through C
preprocessor).

The direct references for u-boot.imx were replaced by $(obj) as
config.mk handles the proper setting of it making it set to $(OBJTREE)
when required.

The build has been test using:

 - ./MAKEALL -s mx5 -s mx6
 - make u-boot.imx
 - make O=/tmp/build

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-02-12 18:39:08 +01:00
Tom Rini
951c6baaf4 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-02-12 10:18:31 -05:00
Fabio Estevam
76c91e668a mx6: Disable Power Down Bit of watchdog
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.

Comparing the watchdog behaviour on a revB versus revC board:

- On a mx6qsabresd revB:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...

- On a mx6qsabresd revC:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR

So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.

Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-02-12 13:54:34 +01:00
Tom Warren
e23bb6a438 Tegra114: Add common CPU (shared) files
These files are used by both SPL and main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
ec1885cee1 Tegra114: Add CPU (armv7) files
These files are for code that runs on the CPU (A15) on T114 boards.
At this time, there is no A15-specific code here.
As T114-specific run-time code is added, it'll go here.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
4040ec10df Tegra114: Add AVP (arm720t) files
This provides SPL support for T114 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Allen Martin
7d54f022bb tegra30: add SBC1 to periph id mapping table
SBC1 is SPI controller 1 on tegra30

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Stephen Warren
4727a13bde tegra: rename FUNCMUX_UART2_UARTB
FUNCMUX_ defines should be named after the pin groups they affect, not
after the module they're muxing onto those pin groups.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Tom Warren
f29f086a09 Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c

Some T30 tables needed whitespace fixes due to checkpatch complaints.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Tom Warren
d83152d8e4 Tegra: T20: Remove unused 'SLOW' SoC ID and PLLX table entry
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:23 -07:00
Michal Simek
00ed345898 arm: zynq: Add lowlevel initialization to C
Do lowlevel initialization directly in C. Zynq do not
require to do it in asm.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-07 09:18:42 +01:00
Michal Simek
59c651f4e2 arm: zynq: Add SLCR support with system reset
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-07 09:18:42 +01:00
Simon Glass
e9adeca3fc ppc: arm: Move sdhc_clk into arch_global_data
This is used by both powerpc and arm, but I think it still qualifies as
architecture-specific.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Albert ARIBAUD
e5f5c4a977 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-02-02 19:29:59 +01:00
Simon Glass
b4d51db86b ixp: Move timestamp to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
5f70714c2f arm: Move timer_reset_value to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
582601da2f arm: Move lastinc to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
66ee692347 arm: Move tbl to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
8ff43b03e9 arm: Move tbu to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
b339051c0d arm: Move timer_rate_hz into arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Simon Glass
f47e6ecd5d at91: Move at91 global data into arch_global_data
Move these fields into arch_global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Fabio Estevam
f093088214 mxs: Use __weak annotation to simplify code
Using the __weak annotation can make the code cleaner.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-01-28 06:54:19 +01:00
Marek Vasut
8303ed128a mxs: Boost the memory power supply
The memory power supply on MX23 didn't pump out enough juice into
the DRAM chip, thus caused occasional memory corruption. Fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-01-28 06:40:38 +01:00
Troy Kisky
71a988aa63 imximage.cfg: run files through C preprocessor
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.

The mkimage command which uses this preprocessor output
was moved to arch/arm/imx-common/Makefile

.gitignore was updated to ignore .cfgtmp files.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-22 10:20:13 +01:00
Otavio Salvador
0023997709 mxs: Add MX23 quirks into the clock code
The MX23 has different handling of the SSP clock and GPMI NAND clock sources,
add necessary quirks into the clock code to properly handle these.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00
Otavio Salvador
30af6c0bca mxs: Fix the memory init for MX23
The memory init is slightly different on MX23, thus split the memory
init for mx23 and mx28 into different functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00
Marek Vasut
7788bf067d mxs: Add function to ungate the power block on MX23
The power block on MX23 must first be ungated before it can be operated.
Add function to MXS power init that ungates it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00
Otavio Salvador
e6d93c26c7 mx23: config: Enable building of u-boot.sb binary
For i.MX23 we need to pass imx23 as elftosb param.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
1ddf386e23 mx23: SPL: Initialize DDR at 133MHz
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
f942f7d962 mx23: SPL: Add boot mode support
This adds the boot mode support for i.MX23 processors.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
f69077e420 mx23: Add support on print_cpuinfo()
Add information to identify i.MX23 chips and its known revisions.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Otavio Salvador
bf48fcb61b mxs: clock: Use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Marek Vasut
14e26bcfa7 mxs: ssp: Pull out the SSP bus to regs conversion
Create function which converts SSP bus number to SSP register pointer.
This functionality is reimplemented multiple times in the code, thus
make one common implementation. Moreover, make it a switch(), since the
SSP ports are not mapped in such nice linear fashion on MX23, therefore
having it a switch will simplify things there.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:19 +01:00
Allen Martin
d08b9e9c7e tegra: remove IRDA pinmux synonym
IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this
synonym and replace with UARTB to disambiguate.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
619bd99e5c Tegra30: clocks: Fix clock tables for I2C and other periphs
Add 16-bit divider support (I2C) to periph table, annotate and
correct some entries, and fix clk_id lookup function.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
6d6c0baebe Tegra30: Add generic Tegra30 build support
This patch adds basic Tegra30 (T30) build support - no specific
board is targeted.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
b2871037d2 Tegra30: Add common CPU (shared) files
These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 13:40:07 -07:00
Tom Warren
5576aab517 Tegra30: Add CPU (armv7) files
These files are for code that runs on the CPU (A9) on T30 boards.
At this time, there are no T30-specific ARMV7 files. As T30-specific
run-time code is added, it'll go here.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidai.com>
2013-01-16 13:40:07 -07:00
Tom Warren
1b245fee91 Tegra30: Add AVP (arm720t) files
This provides SPL support for T30 boards - AVP early init, plus
CPU (A9) init/jump to main U-Boot.

Some changes were made to Tegra20 cpu.c to move common routines
into tegra-common/cpu.c and reduce code duplication.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-01-16 13:40:07 -07:00
Łukasz Dałek
df3ad6c81d pxa: Save lr register in relocate_code function
When u-boot is compiled for PXA25x processor, pxa/start.S is calling
cpu_init_crit by BL instruction. BL is overwriting lr register so
relocate_code is going into infinite loop. This patch preservs lr
register in r12 before calling cpu_init_crit and after function returns
restores it.

Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-01-14 16:22:00 -07:00
Albert ARIBAUD
a17617d655 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-01-14 17:00:02 +01:00
Albert ARIBAUD
1199c377cf Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-01-14 15:21:00 +01:00
Troy Kisky
abbab70363 mx31/mx35/mx51/mx53/mx6: add watchdog
Use a common watchdog driver for all these cpus.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-01-13 11:39:57 +01:00
Jaehoon Chung
5374d386f8 Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clk
Mobile storage is used the CLK_DIV_FSYS3 value.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-11 16:56:31 +09:00
Jaehoon Chung
c39e969e8e Exynos: clock: support get_mmc_clk for exynos
To get exactly clock value for mmc, support the get_mmc_clk() like
set_mmc_clk().

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-11 16:56:31 +09:00
Ajay Kumar
1673f199d9 EXYNOS5: Change parent clock of FIMD to MPLL
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-10 10:19:47 +09:00
Albert ARIBAUD
612404c28a Merge 'u-boot-atmel/master' into 'u-boot-arm/master' 2013-01-09 20:01:48 +01:00
Fabio Estevam
2b16e51c2f mx6: Add workaround for ARM errata
Add workaround for the following ARM errata: 743622 and 751472.

The motivation for this change is the following kernel commit 62e4d357a
(ARM: 7609/1: disable errata work-arounds which access
secure registers), which removes the errata from multiplatform kernel.

Since imx has been converted to multiplatform in the kernel, we need to apply
such workarounds into the bootloader.

Workaround code has been taken from arch/arm/mm/proc-v7.S from 3.7.1 kernel.

Explanation of each erratum is provided at "Chip Errata for the i.MX 6Dual/6Quad"
document available at: cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-09 19:22:06 +01:00
Albert ARIBAUD
ea33fb1a32 Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master' 2013-01-09 16:57:03 +01:00
Albert ARIBAUD
9d86f0c30b kirkwood: make MPP arrays static const
This saves stack and code memory for local copy, and
consumes initialized data memory. For 22 of the 29
kirkwood-based boards, this results in a global saving
of about 30 bytes. For 7 of them, it results in an
increase of 6 to 14 bytes.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-09 04:12:10 +05:30
Albert ARIBAUD
61bdb91335 arm: remove useless code in start.S files
Remove code such as unneeded includes or labels.
These removals have no functional effect.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-08 22:14:54 +01:00
Albert ARIBAUD
e05e5de7fa arm: move C runtime setup code in crt0.S
Move all the C runtime setup code from every start.S
in arch/arm into arch/arm/lib/crt0.S. This covers
the code sequence from setting up the initial stack
to calling into board_init_r().

Also, rewrite the C runtime setup and make functions
board_init_*() and relocate_code() behave according to
normal C semantics (no jumping across the C stack any
more, etc).

Some SPL targets had to be touched because they use
start.S explicitly or for some reason; the relevant
maintainers and custodians are cc:ed.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-08 22:14:50 +01:00
Albert ARIBAUD
79f3877794 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This required manual merging drivers/mtd/nand/Makefile
and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
2013-01-08 13:15:45 +01:00
Rajeshwari Shinde
d055911887 EXYNOS5: FDT : Decode peripheral id
Api is added to decode peripheral id based on the interrupt number
of the peripheral.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:32 +09:00
Piotr Wilczek
7a84e1fa22 arm:exynos4:pinmux: Modify the gpio function for mmc
This patch add pinmux settings for Exynos4 for mmc0 and mmc2

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:47:45 +09:00
Chander Kashyap
a527757316 EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
Adds functions to extract clock frequency of Exynos4x12 IPs.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 21:12:43 +09:00
Albert ARIBAUD
96764df1b4 Merge samsung, imx, tegra into u-boot-arm/master
This commit merges branches from samsung, imx and tegra
meant to fix merge issues between u-boot/master and
u-boot-arm/master, as well as a few manual merge fixes.
2012-12-22 11:59:14 +01:00
Allen Martin
a098cf41fd Merge remote-tracking branch 'u-boot/master' into u-boot-arm-merged
Conflicts:
	README
	arch/arm/cpu/armv7/exynos/clock.c
	board/samsung/universal_c210/universal.c
	drivers/misc/Makefile
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/seaboard.h
2012-12-19 13:02:36 -08:00
Piotr Wilczek
89bd58a1e9 exynos:pinmux: Add pinmux support for i2c
This patch add pinmux for I2C for Exynos4

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
2012-12-11 13:17:31 -07:00
Piotr Wilczek
83d745dd88 exynos:clock: Add i2c clock
This patch adds i2c clock for Exynos4

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
2012-12-11 13:17:31 -07:00
Marek Vasut
fa5e2845a8 mxs: i2c: Implement algorithm to set up arbitrary i2c speed
This algorithm computes the values of TIMING{0,1,2} registers for the
MX28 I2C block. This algorithm was derived by using a scope, but the
result seems correct.

The resulting values programmed into the registers do not correlate
with the contents in datasheet. When using the values from the datasheet,
the I2C clock were completely wrong.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
2012-12-11 13:17:30 -07:00
Davide Bonfanti
21f11c7b49 davinci: fixed cpu reset
The reset procedure works on watchdog timer while before it was modifying
TIMER_1 registers.
Tested on DM365.

Signed-off-by: Davide Bonfanti <davide.bonfanti@bticino.it>
2012-12-10 08:56:38 -07:00
Lokesh Vutla
86021143a3 omap: emif: configure emif only when required
DMM_LISA_MAP registers program whether memory is mapped
on particular EMIF or not. Irrespective of these registers
EMIF is getting configured. Correcting the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-12-10 08:55:25 -07:00
Robert P. J. Day
c7f1cf5f29 OMAP: Tweak omap-common/Makefile since reset.S -> reset.c
Git commit d417d1db5f replaced the
omap-common file reset.S with reset.c, but the Makefile was not
adjusted for that.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-10 08:55:25 -07:00
Robert P. J. Day
f281f299df omap4: Add comments on some "#endif"s for readability.
No functional changes, simply for readability.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-10 08:55:25 -07:00
Robert P. J. Day
e3fe62574d omap3: Add a few comments to "#endif"s for readability.
No functional changes, just more comments for readability when a
preprocessor check spans more than a few lines, and for consistency.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-10 08:55:25 -07:00
Peter Barada
8c4445d266 Pass sdrc timing values through board_sdrc_timings structure
Instead of passing individual registers by value to board_get_mem_timings,
pass a board_mem_timings structure pointer for the board files to fill in.
Pass same structure pointer to write_sdrc_timings.  This saves about
90 bytes of space in SPL.

Signed-off-by: Peter Barada <peter.barada@logicpd.com>
2012-12-10 08:54:02 -07:00
Mansoor Ahamed
04c3757829 am33xx: add ELM support
AM33XX has Error Location Module (ELM) that can be used in conjuction
with GPMC controller to implement BCH codes fully in hardware.
This code is mostly taken from arago tree.

Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:02 -07:00
Ilya Yanok
8eb16b7f73 am33xx: NAND support
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:01 -07:00
Ilya Yanok
1befaffbfb OMAP: include sys_proto.h from boot-common
Include asm/arch/sys_proto.h for gpmc_init prototype.
Without this we get a warning while building for AM335x.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:01 -07:00
Andreas Bießmann
4af9e675fa omap3/mem.c: remove unused defines
These GPMC_CS defines are a leftover from prior gpmc_init(). Commit 187af954
removed the need for these definitions but missed to remove them.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
2012-12-10 08:54:01 -07:00
Minkyu Kang
2c601c7208 Merge branch 'master' of git://git.denx.de/u-boot into resolve
Conflicts:
	README
	board/samsung/universal_c210/universal.c
	drivers/misc/Makefile
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/seaboard.h
2012-12-10 14:13:27 +09:00
Richard Genoud
bcfc8976e5 at91sam9x5: enable USB support for 9x5ek board.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-12-09 22:38:27 +01:00
Stefano Babic
05a860c228 Merge branch 'master' of git://git.denx.de/u-boot into master
Conflicts:
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/woodburn_common.h
	board/woodburn/woodburn.c

These boards still use the old old PMIC framework, so they
do not merge properly after the power framework was merged into
mainline.

Fix all conflicts and update woodburn to use Power Framework.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-12-08 12:02:45 +01:00
Otavio Salvador
393ff47ba3 mxs: SPL: Generalize memory initialization
Use a generic 'dram_vals[]' array that has the full initialization
sequence and rename the initialization method so it doesn't has a
frequency on its name.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-12-07 14:50:02 +01:00
Marek Vasut
a918a53c36 mxs: Staticize SPL functions
The MXS SPL didn't mark local functions "static". Fix it. This also makes the
SPL smaller by roughly 300 bytes.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-04 09:29:11 +01:00
Marek Vasut
1230e7bc2d mxs: Properly setup VDDD in power supply setup code
The memory setup code adjusted the VDDD voltage. Remove this adjustment
and configure the VDDD voltage correctly in the power supply setup code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-04 09:27:21 +01:00
Marek Vasut
77cb33bd25 mxs: Implement common function to setup VDDx
Implement common function to setup the VDDIO, VDDD and VDDA voltage.
Right now, there are two almost identical functions to setup VDDIO
and VDDD, which is prone to breakage. Pull out the differences into
constant structure and pass them as an argument to the common function.

Moreover, the function has almost identical loops for setting higher
and lower VDDx voltage. Merge these two loops.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-04 09:26:54 +01:00
Albert ARIBAUD
b8a7c46796 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2012-11-25 13:01:58 +01:00
Ilya Yanok
08fc71711a OMAP3: am35x: add musb functions
AM35XX specific functions for integrated USB PHY/MUSB IP.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Ilya Yanok
7df5cf35de am33xx: init OTG hardware and new musb gadget driver
AM33xx has support for dual port MUSB OTG controller. This patch
adds initialization for the controller using new MUSB gadget
driver and ether gadget.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Simon Glass
0dde7f5379 arm: Add control over cachability of memory regions
Add support for adjusting the L1 cache behavior by updating the MMU
configuration. The mmu_set_region_dcache_behaviour() function allows
drivers to make these changes after the MMU is set up.

It is implemented only for ARMv7 at present.

This is needed for LCD support, where we want to make the LCD frame buffer
write-through (or off) rather than write-back.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:38 -07:00
Wei Ni
87540de3af tegra: Add SOC support for display/lcd
Add support for the LCD peripheral at the Tegra2 SOC level. A separate
LCD driver will use this functionality to configure the display.

Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Mayuresh Kulkarni:
- changes to remove bitfields and clean up for submission

Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass:
- simplify code, move clock control into here, clean-up
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:37 -07:00
Simon Glass
e1ae0d1f71 tegra: Add support for PWM
The pulse width/frequency modulation peripheral supports generating
a repeating pulse. It is useful for controlling LCD brightness.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:36 -07:00
Simon Glass
b344496110 tegra: Add display support to funcmux
Add support for a default pin mapping for display1.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:35 -07:00
Simon Glass
95be58c988 tegra: Use const for pinmux_config_pingroup/table()
These two functions don't actually modify their arguments so add a const
keyword.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:35 -07:00
Benoît Thébaudeau
39e8576164 mx5: Mark lowlevel_init board-specific code
The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-11-19 08:56:27 +01:00
Fabio Estevam
cc446726de mx6: clock: Only show CSPI clock if CSPI is enabled
If a board does not enable CSPI, there is no need to show the CSPI clock
frequency as part of the 'clock' command.

Reported-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
2012-11-19 08:49:00 +01:00
Fabio Estevam
081237c1f7 mx5: Print CSPI clock in 'clock' command
Print CSPI clock in 'clock' command.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2012-11-19 08:49:00 +01:00
Hatim RV
b56b304252 EXYNOS: Add clock for SPI
Add api to calculate and set the clock for SPI channels

Signed-off-by: James Miller <jamesmiller@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Rajeshwari Shinde
fbb5743308 EXYNOS5: Add pinmux support for SPI
This patch adds pinmux support for SPI channels

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Rajeshwari Shinde
2e206caaa6 EXYNOS: Add clock for I2S
This patch adds clock support for I2S

Signed-off-by: R. Chandrasekar <rcsekar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Rajeshwari Shinde
6b0884d73a EXYNOS: Add pinmux for I2S
This patch adds pinmux support for I2S1

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Ashok Kumar Reddy
4debcc2c22 ARM: arm1176: Define arch_cpu_init() for s3c64xx
arch_cpu_init() is removed from cpu level to SOC level for arm1176
in commit 4ea6d6b,the same is done for s3c64xx

Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:19 +09:00
Marek Vasut
2b5fdd07c5 dm: wdt: Move s5p watchdog timer to drivers/watchdog/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:19 +09:00
Minkyu Kang
bb6527bc73 EXYNOS: Clock: Add common function for pll rate calculation
Moved the common code to calculate pll clock rate to new function
exynos_get_pll_clk().

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
2012-11-15 21:08:19 +09:00
Piotr Wilczek
a3eab2ac41 arm:exynos4:pinmux: Modify the gpio function for mmc
This patch add pinmux settings for Exynos4 for mmc0 and mmc2

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:18 +09:00
Benoît Thébaudeau
ccfa398547 arm1136: Fix enable_caches()
enable_caches() did not enable icache if CONFIG_SYS_ICACHE_OFF was not defined
but CONFIG_SYS_DCACHE_OFF was.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2012-11-10 12:28:22 +01:00
Troy Kisky
20332a066a mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
Previously, the same value was returned for both mx6dl and mx6solo.
Check number of processors to differeniate.
Also, a freescale patch says that sololite has its cpu/rev
stored at 0x280 instead of 0x260.
I don't have a sololite to verify.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-11-10 08:15:40 +01:00
Stefano Babic
3e4d27b06d Merge git://git.denx.de/u-boot 2012-11-10 08:05:54 +01:00
Tom Rini
6acc7c3cbc Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-11-05 07:42:00 -07:00
Kim Phillips
eef1cf2d5c include/linux/byteorder: import latest endian definitions from linux
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives.  Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h.  They come with 'const' added for some swab functions, so
fix those up, too:

include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]

Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).

We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:

macb.c:54:0: warning: "barrier" redefined [enabled by default]

In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)).  This fixes
arch/powerpc/lib/bootm.c:

bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token

powerpc sparse builds yield:

include/common.h:356:22: error: marked inline, but without a definition

the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'

also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]

and:

Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here

and:

In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
2012-11-04 11:00:34 -07:00
Vikram Narayanan
46d626d392 socfpga/spl: Remove malloc.h
Remove unused header

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
2012-11-04 16:23:23 +01:00
Vikram Narayanan
7ae534cef9 socfpga/spl: Remove timer_init from spl_board_init
Timer is initialized already in board_init_r function in
(common/spl/spl.c) No need to initialize it again

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
2012-11-04 16:19:58 +01:00
Albert ARIBAUD
a42c87f9d8 Merge remote-tracking branch 'u-boot-ti/master' 2012-11-03 10:05:22 +01:00
Tom Rini
57f588be60 omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFF
When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings
currently.  Re-order functions so that we don't have that anymore.

Signed-off-by: Tom Rini <trini@ti.com>
2012-10-30 22:23:28 -07:00
Allen Martin
d598e0fe73 arm720t: add back common.h include
Add back common.h header that was removed in previous patch so that
CONFIG_TEGRA can be evaluated correctly.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-29 14:04:26 -07:00
Allen Martin
ee2e185f62 tegra20: initialize variable to avoid compiler warning
Initialize this variable to avoid a compiler warning about possible
use of uninitialized variable with gcc 4.4.6.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-29 09:07:06 -07:00
Allen Martin
b2f9893826 tegra: move to common SPL framework
Change tegra SPL to use common SPL framework.  Any tegra specific
initialization is now done in spl_board_init() instead of
board_init_f()/board_init_r().  Only one SPL boot target is supported
on tegra, which is boot to RAM image.  jump_to_image_no_args() must be
overridden on tegra so the host CPU can be initialized.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-29 09:07:06 -07:00
Stephen Warren
2b7818d49f ARM: enhance u-boot.lds to detect over-sized SPL
Add an ASSERT() to u-boot.lds to detect an SPL that doesn't fit within
SPL_TEXT_BASE..SPL_MAX_SIZE.

Different .lds files implement this check in two possible ways:
1) An ASSERT() like this
2) Defining a MEMORY region of size SPL_MAX_SIZE, and re-directing all
   linker output into that region. Since u-boot.lds is used for both
   SPL and main U-Boot, this would entail only sometimes defining a
   MEMORY region, and only sometimes performing that redirection, and
   hence option (1) was deemed much simpler, and hence implemented.

Note that this causes build failures at least for NVIDIA Tegra Seaboard
and Ventana. However, these are legitimate; the SPL doesn't fit within
the required space, and this does cause runtime issues.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-29 09:07:05 -07:00