Commit graph

656 commits

Author SHA1 Message Date
York Sun
08a37fd13b powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014
Remove these SoCs from Kconfig because they don't have individual
configuration. Clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:20 -05:00
York Sun
90b80386ff crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig
Use Kconfig option to set little- or big-endian access to secure
boot and trust architecture.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:19 -05:00
York Sun
2c2e2c9e14 crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:17 -05:00
York Sun
53c953841b powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate 8572]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04 19:40:14 -05:00
York Sun
26e79b6547 powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig
Use Kconfig option for SYS_NUM_TLBCAMS and clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:13 -05:00
Shengzhou Liu
473f1fc280 fsl/ddr: Enable erratum-a009942 workaround for B/T-series
Enable ERRATUM_A009942 workaround for B-series and T-series platforms.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-15 11:56:17 -08:00
Shengzhou Liu
02fb276157 fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum
- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-05 08:31:45 -08:00
York Sun
54db3c20bd powerpc: mpc86xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig option
Use Kconfig instead of defining this macro in header file.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-04 08:59:11 -08:00
York Sun
8303acbce8 powerpc: mpc85xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig option
Move the macro to Kconfig SYS_FSL_NUM_LAWS.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-02 12:38:42 -08:00
York Sun
830fc1bfe7 powerpc: mpc85xx: Convert CONFIG_SYS_CCSRBAR_DEFAULT to Kconfig option
Move default value definitions to to Kconfig SYS_CCSRBAR_DEFAULT.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-02 08:52:34 -08:00
York Sun
e8a390f018 powerpc: Drop default CONFIG_MAX_CPUS
This configuration has been moved into Kconfig for mpc85xx, and
dropped for mpc86xx. Remove the default value in config.h.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:17 -08:00
York Sun
6c691a1c7e powerpc: mpc86xx: Remove macro CONFIG_MAX_CPUS
This macro CONFIG_MAX_CPUS is not used for MPC86xx SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:16 -08:00
York Sun
4f5554c6e5 powerpc: MPC8641: Remove macro CONFIG_MPC8641
Replace CONFIG_MPC8641 with ARCH_MPC8641 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:16 -08:00
York Sun
1425a87b14 powerpc: MPC8610: Remove macro CONFIG_MPC8610
Replace CONFIG_MPC8610 with ARCH_MPC8610 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:16 -08:00
York Sun
3f82b56d41 powerpc: mpc85xx: Move CONFIG_MAX_CPUS to Kconfig
Use Kconfig to set MAX_CPUS for mpc85xx.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:16 -08:00
York Sun
cdb72c5212 powerpc: T4080: Drop configuration for T4080
There is no T4080 target. Drop related macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:16 -08:00
York Sun
26bc57da0a powerpc: T4240: Remove macro CONFIG_PPC_T4240
Use CONFIG_ARCH_T4240 from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
652a7bbd87 powerpc: T4160: Remove macro CONFIG_PPC_T4160
Use CONFIG_ARCH_T4160 instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
673c01c708 powerpc: T4240QDS: Remove macro CONFIG_T4240QDS
Use CONFIG_TARGET_T4240QDS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
9c21d06c67 powerpc: T4160QDS: Separate from T4240QDS in Kconfig
Use TARGET_T4160QDS to simplify Kconfig options.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
0f3d80e993 powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081
Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
78e5699523 powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDB
CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for
all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI.
CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:14 -08:00
York Sun
5449c98a2d powerpc: T1042: Remove macro CONFIG_PPC_T1042
Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
5d73701073 powerpc: T1040: Remove macro CONFIG_PPC_T1040
Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
e5d5f5a8be powerpc: T1024: Remove macro CONFIG_PPC_T1024
Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
5ff3f41d04 powerpc: T1023: Remove macro CONFIG_PPC_T1023
Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
10343403af powerpc: QEMU_E500: Remove macro CONFIG_QEMU_E500
Replace CONFIG_QEMU_E500 with ARCH_QEMU_E500 in Kconfig and
clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
b41f192b67 powerpc: B4420: Remove macro CONFIG_PPC_B4420
Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up
existing macros.
2016-11-23 23:42:12 -08:00
York Sun
d46a4a1378 powerpc: B4860QDS: Remove macro CONFIG_B4860QDS
Use CONFIG_TARGET_B4860QDS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
3006ebc37e powerpc: B4860: Remove macro CONFIG_PPC_B4860
Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
9539036012 powerpc: P5040: Remove macro CONFIG_P5040
Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:11 -08:00
York Sun
cefe11cdb2 powerpc: P5020: Remove macro CONFIG_PPC_P5020
Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:11 -08:00
York Sun
e71372cb63 powerpc: P4080: Remove macro CONFIG_PPC_P4080
Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:11 -08:00
York Sun
5e5fdd2d00 powerpc: P3041: Remove macro CONFIG_PPC_P3041
Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:10 -08:00
York Sun
ce040c83f1 powerpc: P2041: Remove macro CONFIG_PPC_P2041
Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:10 -08:00
York Sun
789460c914 powerpc: P2010: Drop configuration for P2010
P2010 is a single-core version of P2020. There is no P2010 target
configured. Drop related macros. P2010 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:10 -08:00
York Sun
4593637b13 powerpc: P2020: Remove macro CONFIG_P2020
Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:10 -08:00
York Sun
4167a67d5d powerpc: P1025: Remove macro CONFIG_P1025
Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:10 -08:00
York Sun
52b6f13d2c powerpc: P1024: Remove CONFIG_P1024
Replace CONFIG_P1024 with ARCH_P1024 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:10 -08:00
York Sun
a990799d52 powerpc: P1021: Remove macro CONFIG_P1021
Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:09 -08:00
York Sun
484fff6478 powerpc: P1020: Remove macro CONFIG_P1020
Replace CONFIG_P1020 with ARCH_P1020 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:09 -08:00
York Sun
41c7b7b132 powerpc: P1017: Drop configuration for P1017
P1017 is a single-core version of P1023. There is no P1017 target
configured. Drop related macros. P1017 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
46d9fc0bb7 powerpc: P1014: Drop configuration for P1014
P1014 is a variant of P1010. There is no P1014 target configured.
Drop related macros. P1014 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
2f8b81268a powerpc: P1013: Drop configuration for P1013
P1013 is a single-core version of P1022. There is no P1022 target
configured. Drop related macros. P1022 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
83b9bea116 powerpc: P1012: Drop configuration for P1012
P1012 is a single-core version of P1021. There is no P1012 target
configured. Drop related macros. P1012 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
1cdd96f325 powerpc: P1011: Remove macro CONFIG_P1011
Replace CONFIG_P1011 with ARCH_P1011 in Kconfig. P1011RDB seems to be in
scrapyard though.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
9bb1d6bcd2 powerpc: P1023: Remove macro CONFIG_P1023
Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
feb9e25bc7 powerpc: P1022: Remove macro CONFIG_P1022
Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
7d5f9f84f1 powerpc: P1010: Remove macro CONFIG_P1010
Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
c8f48474bc powerpc: MPC8572: Remove macro CONFIG_MPC8572
Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:06 -08:00
York Sun
23b36a7d48 powerpc: MPC8569: Remove macro CONFIG_MPC8569
Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:06 -08:00
York Sun
d07c384310 powerpc: MPC8568: Remove macro CONFIG_MPC8568
Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:06 -08:00
York Sun
99d0a3123e powerpc: MPC8560: Remove macro CONFIG_MPC8560
Replace CONFIG_MPC8560 with ARCH_MPC8560 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:05 -08:00
York Sun
3c3d8ab58d powerpc: MPC8555: Remove macro CONFIG_MPC8555
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:05 -08:00
York Sun
3aff30825e powerpc: mpc8541: Remove macro CONFIG_MPC8541
Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:05 -08:00
York Sun
7f825218dc powerpc: mpc8540: Remove macro CONFIG_MPC8540
Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:04 -08:00
York Sun
24ad75ae55 powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option
Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:04 -08:00
York Sun
ebccf25518 powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIE
Use CONFIG_TARGET_C29XPCIE instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:04 -08:00
York Sun
4fd64746b0 powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option
Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:04 -08:00
York Sun
a202b9f802 powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macro
Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS
macro.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:04 -08:00
York Sun
115d60c0cf powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options
Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132
Kconfig options.

Also drop #ifdef in BSC9131RDB.h since it is redundant.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:03 -08:00
York Sun
25cb74b30a powerpc: MPC8544: Move CONFIG_MPC8544 to Kconfig option
Replace CONFIG_MPC8544 with ARCH_MPC8544 in Kconfig.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:03 -08:00
York Sun
281ed4c74b powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option
Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:03 -08:00
Sriram Dash
f413d1cae8 mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261
Apply the erratum A006261 for the following Socs:
P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1

Do not apply erratum A006261 for the following Socs:
T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081

Erratum A006261 is applicable for the following Socs:
P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1),
P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0),
P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1).

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-28 09:08:16 -07:00
Sriram Dash
15a6d496e7 mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010
CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy
offset are set to enable the initial setting of Usb Phy for P1010.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-28 09:08:16 -07:00
Tom Rini
cbe7706ab8 Merge git://git.denx.de/u-boot-fsl-qoriq
trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-26 17:10:56 -04:00
Masahiro Yamada
4491327d59 Remove arch/${ARCH}/include/asm/errno.h
Unlike Linux, nothing about errno.h is arch-specific in U-Boot.
As you see, all of arch/${ARCH}/include/asm/errno.h is just a
wrapper of <asm-generic/errno.h>.  Actually, U-Boot does not
export headers to user-space, so we just have to care about the
consistency in the U-Boot tree.

Now all of include directives for <asm/errno.h> are gone.
Deprecate <asm/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-09-23 17:56:18 -04:00
Simon Glass
d3662dff78 Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to Kconfig
Move this option to Kconfig and tidy up existing uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:08 -04:00
Simon Glass
d3e7e2b2ce Convert CONFIG_SPL_HASH_SUPPORT to Kconfig
Move this option to Kconfig and tidy up existing uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:07 -04:00
Simon Glass
dbdaeee43c Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig
Move this option to Kconfig and tidy up existing uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:07 -04:00
Simon Glass
d3c1f46737 Move existing use of CONFIG_SPL_RSA to Kconfig
A few boards define this in a header file which is incorrect. It means that
Kconfig options that rely on this cannot be used. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:03:45 -04:00
Simon Glass
3433a693a9 Move existing use of CONFIG_SPL_DM to Kconfig
A few boards define this in a header file which is incorrect. It means that
Kconfig options that rely on this cannot be used. Move it.

Note that quite a few boards defined this options but do not appear to
actually use SPL:

	BSC9132QDS_NOR_DDRCLK100_SECURE
	BSC9132QDS_NOR_DDRCLK133_SECURE
	BSC9132QDS_SDCARD_DDRCLK100_SECURE
	BSC9132QDS_SDCARD_DDRCLK133_SECURE
	BSC9132QDS_SPIFLASH_DDRCLK100_SECURE
	BSC9132QDS_SPIFLASH_DDRCLK133_SECURE
	C29XPCIE_NOR_SECBOOT
	P1010RDB-PA_36BIT_NAND_SECBOOT
	P1010RDB-PA_36BIT_SPIFLASH_SECBOOT
	P1010RDB-PA_NAND_SECBOOT
	P1010RDB-PA_NOR_SECBOOT
	P1010RDB-PB_36BIT_NOR_SECBOOT
	P1010RDB-PB_36BIT_SPIFLASH_SECBOOT
	P1010RDB-PB_NAND_SECBOOT
	P1010RDB-PB_NOR_SECBOOT
	P3041DS_SECURE_BOOT
	P4080DS_SECURE_BOOT
	P5020DS_NAND_SECURE_BOOT
	P5040DS_SECURE_BOOT
	T1023RDB_SECURE_BOOT
	T1024QDS_DDR4_SECURE_BOOT
	T1024QDS_SECURE_BOOT
	T1024RDB_SECURE_BOOT
	T1040RDB_SECURE_BOOT
	T1042D4RDB_SECURE_BOOT
	T1042RDB_SECURE_BOOT
	T2080QDS_SECURE_BOOT
	T2080RDB_SECURE_BOOT
	T4160QDS_SECURE_BOOT
	T4240QDS_SECURE_BOOT
	ls1021aqds_nor_SECURE_BOOT
	ls1021atwr_nor_SECURE_BOOT
	ls1043ardb_SECURE_BOOT

For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since
they apparently don't have an SPL, this should not matter.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:03:41 -04:00
Simon Glass
b63f8a4336 arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILD
The secure boot header files incorrectly define SPL options only if
CONFIG_SPL_BUILD is defined. This means that the options are only enabled
in an SPL build, and not with a normal 'make xxx_defconfig'. This means
that moveconfig.py cannot work, since it sees the options as disabled even
when they may be manually enabled in an SPL build.

Fix this by changing the order.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:03:37 -04:00
Hou Zhiqiang
71fe22256c fsl: serdes: ensure accessing the initialized maps of serdes protocol
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:06:49 -07:00
York Sun
f3dbf1f0c9 powerpc/mpc85xx: Update erratum workaround for A006379
Update erratum workaround for A006379 to set register CPCHDBCR0
with value 0x001e0000, replacing the old value 0x003c0000.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Dave Liu <dave.liu@nxp.com>
2016-08-02 09:43:13 -07:00
Sumit Garg
69d4b48c84 SECURE_BOOT: Enable SD as a source for bootscript
Add support for reading bootscript and bootscript header from SD. Also
renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and
NOR flash.

Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-26 09:01:43 -07:00
Sumit Garg
aa36c84edf powerpc/mpc85xx: T104x: Add nand secure boot target
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.

For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.

Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.

The changes are similar to
commit 467a40dfe3
    powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 11:09:34 -07:00
Sumit Garg
8f01397ba7 powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL
As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
the next level U-boot image. Add a new function spl_validate_uboot to
perform the validation.

Enable hardware crypto operations in SPL using SEC block.
In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
access to CPC configured as SRAM, configure PAMU.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 11:09:23 -07:00
Robert P. J. Day
62a3b7dd08 Various, unrelated tree-wide typo fixes.
Fix a number of typos, including:

     * "compatble" -> "compatible"
     * "eanbeld" -> "enabled"
     * "envrionment" -> "environment"
     * "FTD" -> "FDT" (for "flattened device tree")
     * "ommitted" -> "omitted"
     * "overriden" -> "overridden"
     * "partiton" -> "partition"
     * "propogate" -> "propagate"
     * "resourse" -> "resource"
     * "rest in piece" -> "rest in peace"
     * "suport" -> "support"
     * "varible" -> "variable"

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2016-07-16 09:43:12 -04:00
Hamish Martin
4b689f02ff dm: gpio: MPC85XX GPIO platform data support
Define a platform data structure for the MPC85XX GPIO driver to allow
use of the driver without device tree. Users should define the GPIO
blocks for their platform like this:
  struct mpc85xx_gpio_plat gpio_blocks[] = {
         {
                 .addr = 0x130000,
                 .ngpios = 32,
         },
         {
                 .addr = 0x131000,
                 .ngpios = 32,
         },
  };

  U_BOOT_DEVICES(my_platform_gpios) = {
         { "gpio_mpc85xx", &gpio_blocks[0] },
         { "gpio_mpc85xx", &gpio_blocks[1] },
  };

This is intended to build upon the recent submission of the base
MPC85XX driver from Mario Six. We need to use that new driver
without dts support and this patch gives us that flexibility.
This has been tested on a Freescale T2080 CPU, although only the first
GPIO block.

Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
Tested-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-11 14:06:44 -06:00
mario.six@gdsys.cc
07d31f8f98 dm: gpio: Add driver for MPC85XX GPIO controller
This patch adds a driver for the built-in GPIO controller of the MPC85XX
SoC (probably supporting other PowerQUICC III SoCs as well).

Each GPIO bank is identified by its own entry in the device tree, i.e.

gpio-controller@fc00 {
      #gpio-cells = <2>;
      compatible = "fsl,pq3-gpio";
      reg = <0xfc00 0x100>
}

By default, each bank is assumed to have 32 GPIOs, but the ngpios
setting is honored, so the number of GPIOs for each bank in configurable
to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of
the P1022 SoC).

The usual functions of GPIO drivers (setting input/output mode and output
value setting) are supported.

The driver has been tested on MPC85XX, but it is likely that other
PowerQUICC III devices will work as well.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 22:13:24 -07:00
Simon Glass
14c67ebaef powerpc: Drop unused code related to generic board
Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-27 15:39:54 -04:00
Tom Rini
fc15b9beed Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-05-24 13:42:03 -04:00
Alex Porosanu
404bf4547e arch/arm, arch/powerpc: add # of SEC engines on the SOC
Some SOCs, specifically the ones in the C29x familiy can have
multiple security engines. This patch adds a system configuration
define which indicates the maximum number of SEC engines that
can be found on a SoC.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18 08:51:46 -07:00
mario.six@gdsys.cc
dbc82ce31b dm: fsl_i2c: Enable DM for FSL I2C
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2016-05-17 08:28:55 +02:00
mario.six@gdsys.cc
ec2c81c5d4 dm: fsl_i2c: Rename I2C register structure
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2016-05-17 08:28:52 +02:00
Simon Glass
73223f0e1b Kconfig: Move CONFIG_FIT and related options to Kconfig
There are already two FIT options in Kconfig but the CONFIG options are
still in the header files. We need to do a proper move to fix this.

Move these options to Kconfig and tidy up board configuration:

   CONFIG_FIT
   CONFIG_OF_BOARD_SETUP
   CONFIG_OF_SYSTEM_SETUP
   CONFIG_FIT_SIGNATURE
   CONFIG_FIT_BEST_MATCH
   CONFIG_FIT_VERBOSE
   CONFIG_OF_STDOUT_VIA_ALIAS
   CONFIG_RSA

Unfortunately the first one is a little complicated. We need to make sure
this option is not enabled in SPL by this change. Also this option is
enabled automatically in the host builds by defining CONFIG_FIT in the
image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
be used in files that are built on the host but must also build for U-Boot
and SPL.

Note: Masahiro's moveconfig.py script is amazing.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add microblaze change, various configs/ re-applies]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:07 -04:00
Simon Glass
9e971632cd freescale: Remove CONFIG_DM from header files
Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP
relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA.
Remove the hacks which enable CONFIG_DM in header files and update the
defconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 14:21:27 -04:00
Aneesh Bansal
f698e9f39a powerpc/SECURE_BOOT: Add PAMU driver
PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.

The patch reverts commit 7cad2e38d6.

The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:40:55 -08:00
Tom Rini
cd85bec36d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-01-27 15:05:36 -05:00
Aneesh Bansal
d0a6d7ce55 secure_boot: enable chain of trust for PowerPC platforms
Chain of Trust is enabled for PowerPC platforms for Secure Boot.
CONFIG_BOARD_LATE_INIT is defined.
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
   bootdelay = 0 (To disable Boot Prompt)
   bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:56 -08:00
Aneesh Bansal
0a6b2714ad secure_boot: create function to determine boot mode
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:42 -08:00
Aneesh Bansal
bdc22074c5 secure_boot: split the secure boot functionality in two parts
There are two phases in Secure Boot
1. ISBC: In BootROM, validate the BootLoader (U-Boot).
2. ESBC: In U-Boot, continuing the Chain of Trust by
         validating and booting LINUX.

For ESBC phase, there is no difference in SoC's based on ARM or
PowerPC cores.

But the exit conditions after ISBC phase i.e. entry conditions for
U-Boot are different for ARM and PowerPC.
PowerPC:

If Secure Boot is executed, a separate U-Boot target is required
which must be compiled with a diffrent Text Base as compared to
Non-Secure Boot. There are some LAW and TLB settings which are
required specifically for Secure Boot scenario.

ARM:
ARM based SoC's have a fixed memory map and exit conditions from
BootROM are same irrespective of boot mode (Secure or Non-Secure).

Thus the current Secure Boot functionlity has been split into
two parts:
CONFIG_CHAIN_OF_TRUST
This will have the following functionality as part of U-Boot:
1. Enable commands like esbc_validate, esbc_halt
2. Change the environment settings based on bootmode, determined
   at run time:
     - If bootmode is non-secure, no change
     - If bootmode is secure, set the following:
         - bootdelay = 0 (Don't give boot prompt)
         - bootcmd = Validate and execute the bootscript.

CONFIG_SECURE_BOOT
This is defined only for creating a different compile time target
for secure boot.

Traditionally, both these functionalities were defined under
CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement
for a separate Secure Boot target for ARM based SoC's.
CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be
determine at run time.

Another Security Requirement for running CHAIN_OF_TRUST is that
U-Boot environemnt must not be picked from flash/external memory.
This cannot be done based on bootmode at run time in current U-Boot
architecture. Once this dependency is resolved, no separate
SECURE_BOOT target will be required for ARM based SoC's.

Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is
defining CONFIG_ENV_IS_NOWHERE

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:32 -08:00
Aneesh Bansal
74eecd820f secure_boot: include/configs: move definition of CONFIG_CMD_BLOB
CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was
earlier defined in all config files. The definition has been
moved to a common file which is included by all configs.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:26 -08:00
Ricardo Ribalda Delgado
5b218ae106 mailaddr: Update mail address
The old mail address will stop working soon.
Update it all the files

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:32:05 +01:00
Shengzhou Liu
a994b3deb0 driver/ddr/fsl: Add workaround for A009663
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.

When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Tom Rini
5b8031ccb4 Add more SPDX-License-Identifier tags
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19 08:31:21 -05:00
Shengzhou Liu
a46b1852de fsl/ddr: updated ddr errata-A008378 for arm and power SoCs
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
Shengzhou Liu
a07bdad749 fsl/errata: move fsl_errata.h to common directory
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
to make it public for both ARM and POWER SoCs.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix soc.h path in fsl_errata.h]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
Thomas Chou
f27445cbdc ns16550: unify serial_ppc
Unify serial_ppc, and use the generic binding.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add TODO comment]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-21 21:50:04 -05:00