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powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option
Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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parent
a202b9f802
commit
4fd64746b0
9 changed files with 15 additions and 16 deletions
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@ -33,6 +33,7 @@ config TARGET_BSC9132QDS
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config TARGET_C29XPCIE
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bool "Support C29XPCIE"
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select ARCH_C29X
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select SUPPORT_SPL
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select SUPPORT_TPL
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select PHYS_64BIT
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@ -185,6 +186,9 @@ config ARCH_BSC9131
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config ARCH_BSC9132
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bool
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config ARCH_C29X
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bool
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config ARCH_MPC8544
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bool
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@ -65,7 +65,7 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
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obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
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# SoC specific SERDES support
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obj-$(CONFIG_PPC_C29X) += c29x_serdes.o
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obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
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obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
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obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
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obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
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@ -959,7 +959,7 @@ int cpu_init_r(void)
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#if defined(CONFIG_PPC_C29X)
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#if defined(CONFIG_ARCH_C29X)
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if ((SVR_SOC_VER(svr) == SVR_C292) ||
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(SVR_SOC_VER(svr) == SVR_C293))
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sec_init_idx(1);
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@ -914,7 +914,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#elif defined(CONFIG_PPC_C29X)
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#elif defined(CONFIG_ARCH_C29X)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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@ -955,7 +955,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_SYS_FSL_DDRC_GEN3
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#endif
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#if !defined(CONFIG_PPC_C29X)
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#if !defined(CONFIG_ARCH_C29X)
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#endif
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@ -2123,7 +2123,7 @@ typedef struct ccsr_gur {
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#ifdef CONFIG_MPC8536
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#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
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#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
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#elif defined(CONFIG_PPC_C29X)
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#elif defined(CONFIG_ARCH_C29X)
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#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
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#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
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& MPC85xx_PORDEVSR2_DDR_SPD_0) \
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@ -2175,7 +2175,7 @@ typedef struct ccsr_gur {
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#elif defined(CONFIG_ARCH_BSC9132)
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#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
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#elif defined(CONFIG_PPC_C29X)
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#elif defined(CONFIG_ARCH_C29X)
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#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
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#else
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@ -2193,7 +2193,7 @@ typedef struct ccsr_gur {
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#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
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u32 pordbgmsr; /* POR debug mode status */
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u32 pordevsr2; /* POR I/O device status 2 */
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#if defined(CONFIG_PPC_C29X)
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#if defined(CONFIG_ARCH_C29X)
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#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
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#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
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#endif
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@ -2344,7 +2344,7 @@ typedef struct ccsr_gur {
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#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
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#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
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#endif
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#if defined(CONFIG_PPC_C29X)
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#if defined(CONFIG_ARCH_C29X)
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#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
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#define MPC85xx_PMUXCR_SPI 0x00000000
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#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
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@ -2964,7 +2964,7 @@ struct ccsr_pman {
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#endif
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#define CONFIG_SYS_MDIO1_OFFSET 0x24000
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#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
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#if defined(CONFIG_PPC_C29X)
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#if defined(CONFIG_ARCH_C29X)
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#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
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#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
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#else
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@ -21,7 +21,7 @@
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uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
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0,
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#if defined(CONFIG_PPC_C29X)
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#if defined(CONFIG_ARCH_C29X)
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CONFIG_SYS_FSL_SEC_IDX_OFFSET,
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2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
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#endif
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@ -11,10 +11,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_C29XPCIE
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#define CONFIG_PPC_C29X
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RAMBOOT_SPIFLASH
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#define CONFIG_SYS_TEXT_BASE 0x11000000
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@ -303,7 +303,7 @@ struct sg_entry {
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*/
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int blob_dek(const u8 *src, u8 *dst, u8 len);
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#if defined(CONFIG_PPC_C29X)
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#if defined(CONFIG_ARCH_C29X)
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int sec_init_idx(uint8_t);
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#endif
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int sec_init(void);
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@ -3682,7 +3682,6 @@ CONFIG_PPC4xx_EMAC
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CONFIG_PPC64BRIDGE
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CONFIG_PPC_B4420
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CONFIG_PPC_B4860
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CONFIG_PPC_C29X
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CONFIG_PPC_CLUSTER_START
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CONFIG_PPC_P2041
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CONFIG_PPC_P3041
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