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https://github.com/AsahiLinux/u-boot
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powerpc: mpc85xx: Convert CONFIG_SYS_CCSRBAR_DEFAULT to Kconfig option
Move default value definitions to to Kconfig SYS_CCSRBAR_DEFAULT. Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun
parent
22a1b99a1d
commit
830fc1bfe7
3 changed files with 52 additions and 43 deletions
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@ -471,6 +471,56 @@ config MAX_CPUS
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config SYS_CCSRBAR_DEFAULT
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hex "Default CCSRBAR address"
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default 0xff700000 if ARCH_BSC9131 || \
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ARCH_BSC9132 || \
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ARCH_C29X || \
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ARCH_MPC8536 || \
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ARCH_MPC8540 || \
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ARCH_MPC8541 || \
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ARCH_MPC8544 || \
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ARCH_MPC8548 || \
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ARCH_MPC8555 || \
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ARCH_MPC8560 || \
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ARCH_MPC8568 || \
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ARCH_MPC8569 || \
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ARCH_MPC8572 || \
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ARCH_P1010 || \
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ARCH_P1011 || \
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ARCH_P1020 || \
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ARCH_P1021 || \
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ARCH_P1022 || \
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ARCH_P1024 || \
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ARCH_P1025 || \
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ARCH_P2020
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default 0xff600000 if ARCH_P1023
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default 0xfe000000 if ARCH_B4420 || \
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ARCH_B4860 || \
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ARCH_P2041 || \
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ARCH_P3041 || \
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ARCH_P4080 || \
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ARCH_P5020 || \
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ARCH_P5040 || \
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ARCH_T1013 || \
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ARCH_T1014 || \
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ARCH_T1020 || \
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ARCH_T1022 || \
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ARCH_T1023 || \
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ARCH_T1024 || \
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ARCH_T1040 || \
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ARCH_T1042 || \
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ARCH_T2080 || \
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ARCH_T2081 || \
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ARCH_T4160 || \
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ARCH_T4240
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default 0xe0000000 if ARCH_QEMU_E500
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help
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Default value of CCSRBAR comes from power-on-reset. It
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is fixed on each SoC. Some SoCs can have different value
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if changed by pre-boot regime. The value here must match
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the current value in SoC. If not sure, do not change.
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source "board/freescale/b4860qds/Kconfig"
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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@ -9,10 +9,6 @@
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/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
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#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
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#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
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#endif
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/*
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* This macro should be removed when we no longer care about backwards
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* compatibility with older operating systems.
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@ -39,27 +35,23 @@
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A004508
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_MPC8540)
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_ARCH_MPC8541)
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_ARCH_MPC8544)
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_MPC8548)
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@ -67,7 +59,6 @@
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
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#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
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#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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@ -84,12 +75,10 @@
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_ARCH_MPC8560)
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_ARCH_MPC8568)
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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@ -98,7 +87,6 @@
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#define QE_MURAM_SIZE 0x10000UL
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#define MAX_QE_RISC 2
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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@ -111,7 +99,6 @@
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#define QE_MURAM_SIZE 0x20000UL
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#define MAX_QE_RISC 4
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#define QE_NUM_OF_SNUM 46
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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@ -124,7 +111,6 @@
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_DDR_115
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#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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#define CONFIG_SYS_FSL_ERRATUM_A004508
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@ -140,7 +126,6 @@
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
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@ -165,7 +150,6 @@
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A004508
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@ -177,7 +161,6 @@
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A004508
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@ -192,7 +175,6 @@
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define QE_MURAM_SIZE 0x6000UL
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@ -208,7 +190,6 @@
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_FSL_SATA_ERRATUM_A001
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@ -227,7 +208,6 @@
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#define CONFIG_SYS_BMAN_NUM_PORTALS 3
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#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_FSL_ERRATUM_A004508
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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@ -241,7 +221,6 @@
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A004508
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@ -255,7 +234,6 @@
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define QE_MURAM_SIZE 0x6000UL
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@ -268,7 +246,6 @@
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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@ -295,7 +272,6 @@
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 32
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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@ -332,7 +308,6 @@
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 32
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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@ -374,7 +349,6 @@
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
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#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
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@ -423,7 +397,6 @@
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 32
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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@ -460,7 +433,6 @@
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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@ -486,7 +458,6 @@
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#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
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#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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@ -507,7 +478,6 @@
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#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
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#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
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@ -575,7 +545,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A007186
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#define CONFIG_SYS_FSL_ERRATUM_A006593
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#define CONFIG_SYS_FSL_ERRATUM_A007798
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#define CONFIG_SYS_FSL_PCI_VER_3_X
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@ -618,7 +587,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A006384
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#define CONFIG_SYS_FSL_ERRATUM_A007212
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#define CONFIG_SYS_FSL_ERRATUM_A004477
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#ifdef CONFIG_ARCH_B4860
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@ -681,7 +649,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
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#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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#define QE_MURAM_SIZE 0x6000UL
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@ -725,7 +692,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
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#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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#define QE_MURAM_SIZE 0x6000UL
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@ -778,7 +744,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_A007212
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#define CONFIG_SYS_FSL_ISBC_VER 2
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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@ -799,22 +764,16 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
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#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
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#elif defined(CONFIG_ARCH_QEMU_E500)
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
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#else
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#error Processor type not defined for this platform
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#endif
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#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
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#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
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#endif
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#ifdef CONFIG_E6500
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#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
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#else
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@ -90,8 +90,8 @@ In the 2nd case bootloader has already re-located CCSRBAR to 0xffe00000
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This will finally use the CONFIG_SYS_RAMBOOT.
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3. File name-> arch/powerpc/include/asm/config_mpc85xx.h
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In the section of the particular SOC, for example P1020,
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3. Change CONFIG_SYS_CCSRBAR_DEFAULT in menuconfig accordingly.
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In the section of the particular SOC, for example P1020, pseudo code
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#if defined(CONFIG_GO)
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000
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