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https://github.com/AsahiLinux/u-boot
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powerpc: mpc85xx: Move CONFIG_MAX_CPUS to Kconfig
Use Kconfig to set MAX_CPUS for mpc85xx. Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun
parent
cdb72c5212
commit
3f82b56d41
2 changed files with 36 additions and 43 deletions
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@ -429,6 +429,42 @@ config ARCH_T4160
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config ARCH_T4240
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bool
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config MAX_CPUS
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int "Maximum number of CPUs permitted for MPC85xx"
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default 12 if ARCH_T4240
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default 8 if ARCH_P4080 || \
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ARCH_T4160
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default 4 if ARCH_B4860 || \
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ARCH_P2041 || \
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ARCH_P3041 || \
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ARCH_P5040 || \
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ARCH_T1040 || \
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ARCH_T1042 || \
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ARCH_T2080 || \
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ARCH_T2081
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default 2 if ARCH_B4420 || \
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ARCH_BSC9132 || \
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ARCH_MPC8572 || \
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ARCH_P1020 || \
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ARCH_P1021 || \
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ARCH_P1022 || \
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ARCH_P1023 || \
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ARCH_P1024 || \
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ARCH_P1025 || \
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ARCH_P2020 || \
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ARCH_P5020 || \
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ARCH_T1020 || \
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ARCH_T1022 || \
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ARCH_T1023 || \
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ARCH_T1024
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default 1
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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source "board/freescale/b4860qds/Kconfig"
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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@ -36,7 +36,6 @@
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#endif
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#if defined(CONFIG_ARCH_MPC8536)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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@ -45,20 +44,17 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_MPC8540)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_ARCH_MPC8541)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_ARCH_MPC8544)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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@ -67,7 +63,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_MPC8548)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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@ -86,20 +81,17 @@
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
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#elif defined(CONFIG_ARCH_MPC8555)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_ARCH_MPC8560)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_ARCH_MPC8568)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_DDRC_GEN2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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@ -114,7 +106,6 @@
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_ARCH_MPC8569)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define QE_MURAM_SIZE 0x20000UL
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@ -130,7 +121,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_MPC8572)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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@ -141,7 +131,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_P1010)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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@ -170,7 +159,6 @@
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/* P1011 is single core version of P1020 */
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#elif defined(CONFIG_ARCH_P1011)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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@ -184,7 +172,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_P1020)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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@ -200,7 +187,6 @@
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#endif
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#elif defined(CONFIG_ARCH_P1021)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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@ -217,7 +203,6 @@
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#elif defined(CONFIG_ARCH_P1022)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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@ -232,7 +217,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A004477
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#elif defined(CONFIG_ARCH_P1023)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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@ -251,7 +235,6 @@
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/* P1024 is lower end variant of P1020 */
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#elif defined(CONFIG_ARCH_P1024)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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@ -266,7 +249,6 @@
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/* P1025 is lower end variant of P1021 */
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#elif defined(CONFIG_ARCH_P1025)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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@ -283,7 +265,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_ARCH_P2020)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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@ -303,7 +284,6 @@
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#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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@ -341,7 +321,6 @@
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#elif defined(CONFIG_ARCH_P3041)
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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@ -381,7 +360,6 @@
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#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_MAX_CPUS 8
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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@ -433,7 +411,6 @@
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#define CONFIG_SYS_PPC64 /* 64-bit core */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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@ -469,7 +446,6 @@
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#define CONFIG_SYS_PPC64
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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@ -500,7 +476,6 @@
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#define CONFIG_SYS_FSL_ERRATUM_A005812
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#elif defined(CONFIG_ARCH_BSC9131)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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@ -519,7 +494,6 @@
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#define CONFIG_ESDHC_HC_BLK_ADDR
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#elif defined(CONFIG_ARCH_BSC9132)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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@ -553,7 +527,6 @@
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#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
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#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
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#ifdef CONFIG_ARCH_T4240
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#define CONFIG_MAX_CPUS 12
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
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#define CONFIG_SYS_NUM_FM1_DTSEC 8
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#define CONFIG_SYS_NUM_FM1_10GEC 2
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@ -568,7 +541,6 @@
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#define CONFIG_SYS_NUM_FM2_10GEC 1
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#define CONFIG_NUM_DDR_CONTROLLERS 2
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#if defined(CONFIG_ARCH_T4160)
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#define CONFIG_MAX_CPUS 8
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
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#endif
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#endif
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@ -651,7 +623,6 @@
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#ifdef CONFIG_ARCH_B4860
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#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_MAX_DSP_CPUS 12
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#define CONFIG_NUM_DSP_CPUS 6
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#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
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@ -665,7 +636,6 @@
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_SRIO_LIODN
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#else
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_MAX_DSP_CPUS 2
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#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
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#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
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@ -685,11 +655,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
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#ifdef CONFIG_SYS_FSL_DDR4
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#define CONFIG_SYS_FSL_DDRC_GEN4
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#endif
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#if defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
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#define CONFIG_MAX_CPUS 4
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#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
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#define CONFIG_MAX_CPUS 2
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#endif
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
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#define CONFIG_SYS_FSL_NUM_LAWS 16
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@ -737,11 +702,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#ifdef CONFIG_SYS_FSL_DDR4
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#define CONFIG_SYS_FSL_DDRC_GEN4
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#endif
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#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
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#define CONFIG_MAX_CPUS 2
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#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_MAX_CPUS 1
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#endif
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#define CONFIG_SYS_FSL_NUM_CC_PLL 2
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
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#define CONFIG_SYS_FSL_NUM_LAWS 16
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@ -783,7 +743,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_QMAN_V3
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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@ -831,7 +790,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#elif defined(CONFIG_ARCH_C29X)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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@ -847,7 +805,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
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#elif defined(CONFIG_ARCH_QEMU_E500)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
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#else
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