The soc info without initialization value should be put into
data section. The driver could be used before relocation,
with it in BSS section could cause issue, since BSS section
is not initializated and it might overwrite other areas that
used by others, such as dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The soc info without initialization value should be put into
data section. The driver could be used before relocation,
with it in BSS section could cause issue, since BSS section
is not initializated and it might overwrite other areas that
used by others, such as dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The soc info without initialization value should be put into
data section. The driver could be used before relocation,
with it in BSS section could cause issue, since BSS section
is not initializated and it might overwrite other areas that
used by others, such as dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue
Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
the DRAM Controller in i.MX8MP will support a feature called "Inline ECC".
This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and
DDR3L). When this feature is enabled by software, the DRAM Controller
reserves 12.5% of DRAM capacity for ECC information, and presents only
the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to
the rest of the SoC.
The DRAM memory can be divided into 8 regions so that if a use case only
requires ECC protection on a subset of memory, then only that subset of
memory need support inline ECC. If this occurs, then there is no
performance penalty accessing the non-ECC-protected memory (no need to
access ECC for this portion of the memory map). This is all configured
with the DRAM Controller.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The 'selfref_en' should be bit'0', so correct the setting to
enable the auto self-refresh.
Reviewed-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In commit commit d2c05f50e1 ("mmc: omap_hsmmc: Set 3.3V for IO voltage")
was changed 3.0V IO voltage to 3.3V but it was not done on all places in
omap_hsmmc driver. That commit broke eMMC support on Nokia N900.
This patch fixes that problematic commit and changes 3.0V to 3.3V on all
remaining places in omap_hsmmc driver.
Fixes: d2c05f50e1 ("mmc: omap_hsmmc: Set 3.3V for IO voltage")
Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Faiz Abbas <faiz_abbas@ti.com>
We only request ring pairs via K3 DMA driver, switch to use the new
k3_ringacc_request_rings_pair() to simplify the code.
As a good side effect, all boot stages now use exposed RING mode which
avoid maintaining proxy mode for 32 bit R5 core.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
In K3 UDMA architecture, RX rings are associated with RX flows rather
than RX channels, therefore move the ring pointers to udma_rflow struct
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Encapsulate channel configuration in a separate struct so as to ease
resetting of these fields with memset() and also to increase readability
of the code.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
In preparation of adding more K3 SoCs, separate soc specific
initialization add a SoC specific initialization hook.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add new API k3_ringacc_request_rings_pair() to request pair of rings at
once, as in the most case Rings are used with DMA channels which required
to request pair of rings - one to feed DMA with descriptors (TX/RX FDQ) and
one to receive completions (RX/TX CQ). This will allow to simplify Ringacc
API users.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Move the free, occ, windex and rinfex under a struct.
We can use memset to zero them and it will allow a cleaner way to extend
the variables for duplex rings.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Update driver to use static PSIL endpoint Data instead of DT. This will
allow DT bindings to be in sync with kernel's DT.
Note that this patch breaks networking and OSPI boot as driver changes
are not backward compatible with existing DT. Subsequent commit will
update the DT to make it compatible with updated driver.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Much of PSIL endpoint configuration for a given SoC can be known at
compile time, therefore pass them for platform specific data instead of
DT.
Add per SoC's specific PSIL endpoint data. This is to bring driver in
sync with upstream DT.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Fixed delay 200us is not working in certain platforms. Change to
poll for reset completion status to have more reliable reset process.
Controller will set the rst_comp bit in intr_status register after
controller has completed its reset and initialization process.
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Radu Bacrau <radu.bacrau@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Always put the controller in reset, then take it out of reset.
This is to make sure controller always in reset state in both SPL and
proper Uboot.
This is preparation for the next patch to poll for reset completion
(rst_comp) bit after reset.
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Radu Bacrau <radu.bacrau@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This UART controller is integrated with a FIFO. Enable it.
You can put the next character into the FIFO while the transmitter
is sending out the current character. This works slightly faster.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Ensure the transmitter is empty when chaining the baudrate or any
hardware settings. If a character is remaining in the transmitter,
the console will be garbled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
After all, I am not a big fan of using a structure to represent the
hardware register map.
You do not need to know the entire register map.
Add only necessary register macros.
Use FIELD_PREP() instead of maintaining a pair of shift and mask.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since commit 1517126fda ("ARM: uniphier: select DM_ETH"), DM-based
drivers/net/smc911x.c is compiled, but it is never probed because the
parent node lacks the DM-based driver.
I need a skeleton driver to populate child devices (but the next commit
will move more hardware settings to the this driver).
I put this to drivers/bus/uniphier-system-bus.c because this is the
same path as the driver in Linux kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
patman support for Python3 on Ubuntu 14.04
new checkpatch check to avoid #ifdefs
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Merge tag 'dm-pull-10jul20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
of-platdata: better phandle and compatible-string support
patman support for Python3 on Ubuntu 14.04
new checkpatch check to avoid #ifdefs
On build with 32 bit, there is a warning for int-to-pointer-cast.
Fix the int to pointer cast by using uintptr_t.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Some atypical users of xhci might need to manually reset their xHCI
controller before starting the HCD setup. Check if a reset controller
device is available to the PCI bus and trigger a reset.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
[mb: squash fix to only build xhci_reset_hw() if CONFIG_DM_BUS]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Raspberry Pi 4's co-processor controls some of the board's HW
initialization process, but it's up to Linux to trigger it when
relevant. Introduce a reset controller capable of interfacing with
RPi4's co-processor that models these firmware initialization routines as
reset lines.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
This patch adds basic driver PCI Express controller found on Broadcom
set-top-box SoCs, e.g. BCM2711.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 3GB region is used.
The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
USB Host Controller.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Drop the nondm code from kirkwood_spi.c since there
is no board or any other code using for it.
Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
In the current implementation, when dtoc parses a dtb to generate a struct
platdata it converts the information related to linked nodes as pointers
to struct platdata of destination nodes. By doing this, it makes
difficult to get pointer to udevices created based on these
information.
This patch extends dtoc to use struct driver_info when populating
information about linked nodes, which makes it easier to later get
the devices created. In this context, reimplement functions like
clk_get_by_index_platdata() which made use of the previous approach.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently when creating an U_BOOT_DEVICE entry a struct driver_info
is declared, which contains the data needed to instantiate the device.
However, the actual device is created at runtime and there is no proper
way to get the device based on its struct driver_info.
This patch extends struct driver_info adding a pointer to udevice which
is populated during the bind process, allowing to generate a set of
functions to get the device based on its struct driver_info.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In order to prepare for a new support of phandle when OF_PLATDATA is used
drop the const for struct driver_info as this struct will need to be
updated on runtime.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently when using OF_PLATDATA the binding between devices and drivers
is done trying to match the compatible string in the node with a driver
name. However, usually a single driver supports multiple compatible strings
which causes that only devices which its compatible string matches a
driver name get bound.
To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro,
which generates no code at all, but allows an easy way to declare driver
name aliases. Thanks to this, dtoc could be improve to look for the driver
name based on its alias when it populates the U_BOOT_DEVICE entry.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When using OF_PLATDATA, the bind process between devices and drivers
is performed trying to match compatible string with driver names.
However driver names are not strictly defined, and also there are different
names used when declaring a driver with U_BOOT_DRIVER, the name of the
symbol used in the linker list and the used in the struct driver_info.
In order to make things a bit more clear, rename the drivers names. This
will also help for further OF_PLATDATA improvements, such as checking
for valid driver names.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour:
Signed-off-by: Simon Glass <sjg@chromium.org>
Compiling drivers/mtd/spi/sandbox.c fails when compiled with
CONFIG_LOG=n:
In file included from include/common.h:20,
from drivers/mtd/spi/sandbox.c:13:
drivers/mtd/spi/sandbox.c:295:15: error: format ‘%s’ expects argument of
type ‘char *’, but argument 7 has type ‘int’ [-Werror=format=]
295 | log_content(" cmd: transition to %s state\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’
37 | #define pr_fmt(fmt) fmt
| ^~~
include/log.h:128:30: note: in expansion of macro ‘log_nop’
128 | #define log_content(_fmt...) log_nop(LOG_CATEGORY, \
| ^~~~~~~
drivers/mtd/spi/sandbox.c:295:3: note: in expansion of macro
‘log_content’
295 | log_content(" cmd: transition to %s state\n",
| ^~~~~~~~~~~
drivers/mtd/spi/sandbox.c:295:37: note: format string is defined here
295 | log_content(" cmd: transition to %s state\n",
| ~^
| |
| char *
| %d
Supply function sandbox_sf_state_name() independent of CONFIG_LOG.
Fixes: c3aed5db59 ("sandbox: spi: Add more logging")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable QE bit for ISSI flash chips.
QE enablement logic is similar to what Macronix
has, so reuse the existing code itself.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The spi bitbanging driver did not implement all spi modes properly. Add
code to support all spi modes, honoring soft_spi_set_mode() and
defaulting to spi mode 0. Previously, CPHA was implemented inversely
(defaulting to CPHA=1) and CPOL=1 was hardcoded.
Signed-off-by: Johannes Holland <johannes.holland@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
- Add two- and three-argument versions of CONFIG_IS_ENABLED in
linux/kconfig.h
- Adds a new feature which supports copying modified parts of
the frame buffer to the uncached hardware buffer
- Enable the copy framebuffer on various x86 targets
Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
In current code there is no cache flush after initializing the scratchpad
buffer array with the scratchpad buffer pointers. This leads to a failure
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
controller + VL805 USB hub) - the very first TRB transfer on the command
ring fails and there is a timeout while waiting for the command completion
event. After adding the missing cache flush everything seems to be working
as expected.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
i2c changes for v2020.10
- Add support for I2C controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
- Add I2C controller support for Cortina Access CAxxxx SoCs
- new rtc methods, rtc command, and tests
- imx_lpi2c: Improve the codes to use private data
- stm32f7_i2c.c: Add new compatible "st,stm32mp15-i2c"
- stm32f7_i2c.c: Add Fast Mode Plus support
- pwm: Add PWM driver for SiFive SoC
Since the mdio code got upstreamed it is not possible
to activate network ports on CP110 Master and Slave.
The problem is in mvpp2_base_probe which is called for each
CP110 and it initializes the buffer area for descs and rx_buffers.
This should only happen once though and the bd space is actually
set to 0 after the first run of the function.
This leads to an error when the second CP110 tries the initialization
again and disables all network ports on this CP110.
This patch adds a static variable to check if the buffer area is
initialized only once globally.
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Measurements on actual hardware shown that the read ODT is early by 3
clocks. Adjust the calculation to avoid this.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample
delay fields are 5 bits wide. Use the correct bitmask of 0x1f when
extracting the value.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Update the video driver to support this feature and enable it on
minnowmax to speed up the display.
With this change, the time taken to print the environment to the display
without CONFIG_CONSOLE_SCROLL_LINES is reduced from over 13 seconds to
300ms, at 1280x1024.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Update the video driver to support this feature and enable it on link.
Also remove the multi-line scrolling since normal scrolling is fast enough
now.
With this change, the time taken to print the environment to the display
without CONFIG_CONSOLE_SCROLL_LINES is reduced from about 930ms to 29ms.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update the video driver to support this feature and enable it on samus.
Also remove the multi-line scrolling since normal scrolling is fast enough
now.
With this change, the time taken to print the environment to the display
without CONFIG_CONSOLE_SCROLL_LINES is reduced from about 430ms to 12ms.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For PCI video devices that are not mentioned in the devicetree, U-Boot
does not bind a driver before relocation, since PCI is not fully probed
at that point. Furthermore it is possible for the video device to be on
a secondary bus which is not even scanned.
This is fine if the framebuffer is allocated in fixed memory, as it
normally is on x86. But when using this as a copy framebuffer, we also
need U-Boot to allocate its own cached framebuffer for working in. Since
the video driver is never bound before relocation, the framebuffer size
is never set and U-Boot does no allocation.
Add a new CONFIG option to reserve 16MB of memory for this eventuality.
This allows vesa devices to use the copy framebuffer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present video_bottom is set to the bottom of each framebuffer when it
is allocated. This is not correct, since it should hold the bottom of the
entire area available for framebuffers.
Fix this by adding a private address in the uclass which keeps track of
the next available spot for a framebuffer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
When using a copy framebuffer we need to tell the video subsystem its
address. U-Boot's normally allocated framebuffer is used as the working
buffer, but nothing is displayed until it is copied to the copy
framebuffer.
For this to work the video driver must request that a framebuffer be
allocated separately from the hardware framebuffer, so add a check for
that.
Also add a log category so that logging appears correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Enable this feature on sandbox by updating the SDL driver to have two
framebuffers.
Update the video tests to check that the copy framebuffer is kept in sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Adjust the bitmap code to sync to the copy framebuffer when done.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Update the implementation to keep a track of what it changes in the frame
buffer and then tell the copy buffer about it. Use the special
vidconsole_memmove() helper so that memmove() operations are also
reflected in the copy buffer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Update the implementation to keep a track of what it changes in the frame
buffer and then tell the copy buffer about it. Use the special
vidconsole_memmove() helper so that memmove() operations are also
reflected in the copy buffer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Update the implementation to keep a track of what it changes in the frame
buffer and then tell the copy buffer about it. Use the special
vidconsole_memmove() helper so that memmove() operations are also
reflected in the copy buffer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a convenience function to call video_sync_copy() for a vidconsole.
Also add a memmove() helper, which does the memmove() as well as the sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Update video_clear() to also sync to the copy framebuffer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This framebuffer is separately mapped. Update the video post-probe
function to set this up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Some architectures use a cached framebuffer and flush the cache as needed
so that changes are visible. This is supported by U-Boot.
However x86 uses an uncached framebuffer with a 'write-combining' feature
to speed up writes. Reads are permitted but they are extremely expensive.
Unfortunately, reading from the frame buffer is quite common, e.g. to
scroll it. This makes scrolling very slow.
Add a new feature which supports copying modified parts of the frame
buffer to the uncached hardware buffer. This speeds up scrolling by at
least 10x on x86 so the extra complexity cost seems worth it.
As a starting point, add the Kconfig, update the video structures to keep
track of the buffer and add a function to do the copy.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present when the console is rotated 180 degrees it starts almost a
whole character to the left of the right edge (typically 7 pixels with
an 8-pixel-wide font). On a display which aligns with the font width,
this just wastes space. On a display that does not this can result in
x_frac going negative for the final character (the one on the left
side) and the overflow -EAGAIN check at the start of the function
failing.
Change the function to start at the rightmost pixel to fix these
problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The functions in this file do similar things but not always in the same
way. To make the code easier to read and compare, use a separate 'linenum'
variable in every function. This is then multiplied by the line length to
get the offset within the frame buffer to modify. Also use an 'x' variable
to hold the pixel position within that line. This is multipled by the
pixel size and added to the offset.
Also move the pbytes declaration up a little with the other long lines.
A side effect of splitting out these variables is that they are promoted
to int, i.e. a signed type, from the unsigned short used in the
vidconsole_priv struct. This would be necessary should any of the
variables go negative. At present this can actually happen in
console_putc_xy_2(), if the display width is not a multiple of the
character size (see next patch).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a devicetree property to select a rotated console. This uses the same
encoding as vidconsole itself: 0=normal; 1=90 degrees clockwise, 2=upside
down, 3=90 degrees anticlockwise.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
At present these functions fail silently even when debugging, which is not
very helpful. Add a way to print a message to the serial output when an
error is detected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC
This driver is simple port of Linux pwm sifive driver from Linux v5.6
commit: 9e37a53eb051 ("pwm: sifive: Add a driver for SiFive SoC PWM")
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Read SYSCFG bindings to set Fast Mode Plus bits if Fast Mode Plus
speed is selected.
Handle the stm32mp15 specific compatible to handle FastMode+
registers handling which is different on the stm32mp15 compared
to the stm32f7 or stm32h7.
Indeed, on the stm32mp15, the FastMode+ set and clear registers
are separated while on the other platforms (F7 or H7) the control
is done in a unique register.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add a new compatible "st,stm32mp15-i2c" introduced in Linux kernel v5.8
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
It's more natural that any write that happens to touch the reset
register should cause a reset, rather than just a write that starts at
that offset.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The current set method is broken; a simple test case is to first set
the date to something in April, then change the date to 31st May:
=> date 040412122020.34
Date: 2020-04-04 (Saturday) Time: 12:12:34
=> date 053112122020.34
Date: 2020-05-01 (Friday) Time: 12:12:34
or via the amending of the existing rtc_set_get test case similarly:
$ ./u-boot -T -v
=> ut dm rtc_set_get
Test: dm_test_rtc_set_get: rtc.c
expected: 31/08/2004 18:18:00
actual: 01/08/2004 18:18:00
The problem is that after each register write,
sandbox_i2c_rtc_complete_write() gets called and sets the internal
time from the current set of registers. However, when we get to
writing 31 to mday, the registers are in an inconsistent state (mon is
still 4), so the mktime machinery ends up translating April 31st to
May 1st. Upon the next register write, the registers are populated by
sandbox_i2c_rtc_prepare_read(), so the 31 we just wrote to mday gets
overwritten by a 1.
Fix it by writing all registers at once, and for consistency, update
the get method to retrieve them all with one "i2c transfer".
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
This simply consists of renaming the existing pcf2127_read_reg()
helper to follow the naming of the other
methods (i.e. pcf2127_rtc_<method name>) and changing the type of its
"len" parameter.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Similar to how the dm_rtc_{read,write} functions fall back to using
the {read,write}8 methods, do the opposite in the rtc_{read,write}8
functions.
This way, each driver only needs to provide either ->read8 or ->read
to make both rtc_read8() and dm_rtc_read() work - without this, a
driver that provides ->read() would most likely just duplicate the
logic here for implementing a ->read8() method in term of its ->read()
method. The same remarks of course apply to the write case.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Similar to dm_rtc_read(), introduce a helper that allows the caller to
write multiple consecutive 8-bit registers with one call. If the
driver provides the ->write method, use that, otherwise loop using
->write8.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Some users may want to read multiple consecutive 8-bit
registers. Instead of each caller having to implement the loop,
provide a dm_rtc_read() helper. Also, allow a driver to provide a
->read method, which can be more efficient than reading one register
at a time.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Current driver calls the devfdt_get_addr to get the base address
of lpi2c controller in each sub-functions. Since the devfdt_get_addr
accesses the DTB and translate the address, it introduces much
overhead.
Improve the codes to use private variable which has recorded the
base address from probe.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The offset at which the image to be loaded from NAND is located is
retrieved from the itb header. The presence of bad blocks in the area
of the NAND where the itb image is located could invalidate the offset
which must therefore be adjusted taking into account the state of the
sectors concerned.
cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
tpm_tis_spi.c directly includes tpm_tis.h and tpm-v2.h which both
define the same enums (see e.g. TPM_ACCESS_VALID). Add an #ifndef to
prevent redeclaration errors.
Signed-off-by: Johannes Holland <johannes.holland@infineon.com>
This solves a compatibility issue with Linux device trees
that contain TPMv2.x hardware. So it's easier to import DTS
from upstream kernel when migrating board init from C code
to DTS.
The issue is that fallback binding is different between Linux
and u-Boot.
Linux: "tcg,tpm_tis-spi"
U-Boot: "tis,tpm2-spi"
As there are currently no in-tree users of the U-Boot binding,
it makes sense to use Linux fallback binding.
Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Even though the sata_sil driver was converted over to the driver model,
it still assumed that the PCI controller is using the legacy interface.
Allow the "devno" member to be a struct udevice pointer and use
DM_PCI_COMPAT to covert the rest of the interface.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
When compiled as a DM_ETH driver, the scm911x driver was reading the MAC
address from the optional EEPROM storage, but failed to copy this to the
platdata struct. Since it was also missing a definition of the
read_rom_hwaddr() function, the generic Ethernet code was dismissing
this MAC address, falling back to a random address or denying to start
at all.
Add an implementation of .read_rom_hwaddr, and refactor the function
reading the ROM address to be called by all interested parties.
This fixes MAC address issues when using the driver in DM_ETH "mode".
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
dm_gpio_lookup_name() searches for a gpio through
the bank name. But we have also gpio labels, and it
makes sense to search for a gpio also in the labels
we have defined, if no gpio is found through the
bank name definition.
This is useful for example if you have a wp pin on
different gpios on different board versions.
If dm_gpio_lookup_name() searches also for the gpio labels,
you can give the gpio an unique label name and search
for this label, and do not need to differ between
board revisions.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Don't enable by default]
Signed-off-by: Tom Rini <trini@konsulko.com>
This patchs adds glue logic to enable designware mac present on
Action Semi based S700 SoC, Configures SoC specific bits.
Undocumented bit that programs the PHY interface select register
comes from vendor source.
It has been tested on Cubieboard7-lite based on S700 SoC.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
RTL8201F PHY module found on Actions Semi Cubieboard7 seems to have
specific Rx/Tx interface timings requirement for proper PHY operations.
These timing values are not documented anywhere and picked from vendor
code.
This commits lets proper packets to be transmitted over the network.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This patch adds support for Realtek PHY RTL8201F 10/100Mbs
(with variants: RTL8201FN and RTL8201FL) PHYceiver. It is
present on Actions Semi Cubieboard7 board.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This commit adds clocks needed for ethernet operations for
Actions OWL family of SoCs (S700 and S900).
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Renamed dm "drivers" subcommand to "compat" (as it listed
compatibility strings) and prevent it from segfaulting when
drivers have no of_match populated.
Added a new "drivers" subcommand to dump a list of all known DM
drivers and for each, their uclass id, uclass driver and names of
attached devices.
Added a new "static" subcommand to dump a list of DM drivers with
statically defined platform data.
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add size and addr parameter to test "All" to override the default
value (4kB and STM32_DDR_BASE) used in tests with these optional
parameters: [size] or [addr].
When other optional parameters are present before [addr],
they are replaced by default value:
- [loop] = "1"
- [pattern] = "-" (new: force default pattern)
Example to use:
DDR>test 0 1 0x20000
DDR>test 0 1 0x1000000 0xD0000000
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The test 4 = "AddressBus [size] [addr]" without parameter
detects alias for any address bit only when:
- size = real size of DDR
- addr = start of DDR = 0xC0000000
These value must be the default value when parameters are absent.
This patch sets bufsize to STM32_DDR_SIZE and get_bufsize() selects
the correct value for bufsize when this parameter is absent =
full size of the DDDR
On EV1 board :
DDR> test 4
running at 0xC0000000 length 0x40000000
On DK2 board
DDR> test 4
running at 0xC0000000 length 0x20000000
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add a parameter addr in test FrequencySelectivePattern to select
the base address used to execute the tests.
Default value (when the parameter is absent) is STM32_DDR_BASE,
selected in get_addr() function.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add protection on minimum value for result of get_bufsize
and check the alignment of buffer size: only multiple min_size
is allowed; only 4 bytes alignment was checked previously
(value & 0x3).
For example the "Random" test raises an issue when size is not 8 bytes
aligned because address for buffer = address + size / 2 is not word
aligned.
This patch avoid test error for unsupported size value.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
There maybe an overshoot:
- when disabling, then re-enabling vrefbuf too quickly
- or upon platform reset as external capacitor maybe slow
discharging (VREFBUF is HiZ at reset by default).
VREFBUF is used by ADC/DAC on some boards. An overshoot on the reference
voltage make the conversions inaccurate for a short period of time. So:
- Don't put the VREFBUF in HiZ when disabling, to force an active
discharge.
- Enforce a 1ms OFF/ON delay, also upon reset
Penalty is a 1ms delay is applied (even for a cold boot), when enabling
VREFBUF.
Fixes: 93cf0ae775 ("power: regulator: Add support for stm32-vrefbuf")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Add information on pin configuration used for pinmux command:
- bias configuration for output (disable, pull up, pull down)
- otype for input (open drain or push pull)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add information on pin configuration used for pinmux command.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add support of ops get_dir_flags() to read dir flags from
STMFX registers.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add the helper functions stmfx_read_reg() and stmfx_write_reg() to avoid
duplicated code for access to stmfx's register with mask.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Rename the two function used to change the pin configuration
from stmfx_pinctrl_.. stmfx_conf_... to clarify the function usage.
No functional change.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Move the functions stmfx_pinctrl_set_pupd and stmfx_pinctrl_set_type;
they can be used by the new ops get_dir_flags and set_dir_flags introduced
by next patch.
No functional change.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add ops get_dir_flags() to read dir flags from GPIO registers.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add a weak functions to save the vddcore voltage value provided
in the OPP node when the clock tree is initialized.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
The PLL1 node (st,pll1) is optional in device tree, the max supported
frequency define in OPP node is used when the node is absent.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Update the compatible associated with the STM32 MPU glue
in the DWC ethernet driver.
The supported compatible is the specific "st,stm32mp1-dwmac"
as indicated in Linux binding
Documentation/devicetree/bindings/net/stm32-dwmac.txt
and not the "snps,dwmac-4.20a" only used to the select IP
version.
This glue is implemented in Linux kernel in:
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
For information in stm32mp151.dtsi, the 2 compatibles are
supported:
ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
...
};
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This patch restores CONFIG_VIDCONSOLE_AS_LCD as boolean
and introduce a separate sting as CONFIG_VIDCONSOLE_AS_NAME
to search this string in stdout used as videoconsole.
This patch avoid issue with board defconfig or code expecting
CONFIG_VIDCONSOLE_AS_LCD as boolean.
Fixes: 22b897a123 ("video: extend stdout video console work-around for 'vga'")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
- Resync Kconfiglib with the v14.1.0 release.
- Re-sync our <linux/compiler*h> files with v5.7-rc5 from upstream.
- Fully resync checkpatch.pl with v5.7 release.
To safely to all of the above, we have a few bugfixes about functions
that need a 'static inline' but weren't. We also stop setting
CROSS_COMPILE in arch/*/config.mk. Finally, with the above changes
boards can now opt-in to optimizing inlining and we do this for the
socfpga stratix10 platform for space savings.
save the GPIOD_ flags also in the gpio descriptor.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Fixes: 788ea83412 ("gpio: add function _dm_gpio_set_dir_flags")
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Walter Lozano <walter.lozano@collabora.com>
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
All cpu cores within FU540-C000 having split I/D caches.
Set the L1 cache feature bit using the i-cache-size or d-cache-size
as one of the property from device tree indicating that L1 cache is
present on the cpu core.
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz: L1 cache, MMU
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
The conditional check to read "mmu-type" from the device tree
is not rightly handled due to which the cpu feature doesn't include
CPU_FEAT_MMU even if it's corresponding entry is present in the device
tree.
The initialization of cpu features is now taken care in cpu-uclass
driver, so no need to zero out cpu_freq in riscv_cpu driver and can be
removed.
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
The cmd "cpu detail" fetches uninitialized cpu feature information
and thus displays wrong / inconsitent details as below.
For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it.
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
The L1 cache or MMU entry seen above is also displayed inconsistently.
So initialize cpu information to zero into cpu-uclass itself so that
similar issues can be avoided for other CPU drivers.
We now see correct features as:
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Instead of always using the "clock-frequency" property to determine cpu
frequency, try using a clock in "clocks" if it exists. This patch also
fixes a bug where there could be spurious higher frequencies if sizeof(u32)
!= sizeof(ulong).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
dev_read_addr_ptr had different semantics depending on whether OF_LIVE was
enabled. This patch converts both implementations to return NULL on error,
and converts all call sites which check for FDT_ADDR_T_NONE to check for
NULL instead. This patch also removes the call to map_physmem, since we
have dev_remap_addr* for those semantics.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This type of bus is used in Linux to designate buses which have power
domains and/or clocks which need to be enabled before their child devices
can be used. Because power domains are automatically enabled before probing
in U-Boot, we just need to enable any clocks present.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Due to the large number of clocks, I decided to use the CCF. The overall
structure is modeled after the imx code. Clocks parameters are stored in
several arrays, and are then instantiated at run-time. There are some
translation macros (FOOIFY()) which allow for more dense packing.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
This is a small driver to do a software bypass of a clock if hardware
bypass is not working. I have tried to write this in a generic fashion, so
that it could be potentially broken out of the kendryte code at some future
date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
so that the CPU keeps on working.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean
predicate instead of the index. Other clk_get_by_* functions got the clock
correctly, but passed a predicate instead of the index to clk_get_by_tail.
This could lead to confusing error messages.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
clk_composite_ops was shared between all devices in the composite clock
driver. If one clock had a feature (such as supporting set_parent) which
another clock did not, it could call a null pointer dereference.
This patch does three things
1. It adds null-pointer checks to all composite clock functions.
2. It makes clk_composite_ops const and sets its functions at compile-time.
3. It adds some basic sanity checks to num_parents.
The combined effect of these changes is that any of mux, rate, or gate can
be NULL, and composite clocks will still function normally. Previously, at
least mux had to exist, since clk_composite_get_parent was used to
determine the parent for clk_register.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
CCF clocks should always use the struct clock passed to their methods for
extracting the driver-specific clock information struct. Previously, many
functions would use the clk->dev->priv if the device was bound. This could
cause problems with composite clocks. The individual clocks in a composite
clock did not have the ->dev field filled in. This was fine, because the
device-specific clock information would be used. However, since there was
no ->dev, there was no way to get the parent clock. This caused the
recalc_rate method of the CCF divider clock to fail. One option would be to
use the clk->priv field to get the composite clock and from there get the
appropriate parent device. However, this would tie the implementation to
the composite clock. In general, different devices should not rely on the
contents of ->priv from another device.
The simple solution to this problem is to just always use the supplied
struct clock. The composite clock now fills in the ->dev pointer of its
child clocks. This allows child clocks to make calls like clk_get_parent()
without issue.
imx avoided the above problem by using a custom get_rate function with
composite clocks.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
- Makefile: add rule to build an endian-swapped U-Boot image
used by MIPS Malta EL variants
- CI: add Qemu tests for MIPS Malta
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Merge tag 'mips-pull-2020-06-29' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips into next
- net: pcnet: cleanup and add DM support
- Makefile: add rule to build an endian-swapped U-Boot image
used by MIPS Malta EL variants
- CI: add Qemu tests for MIPS Malta
Add missing space before a comment delimiter.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Add Kconfig entries for the pcnet driver and convert MIPS malta
to use those.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
With all the changes in place, add support for DM into the
pcnet driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Pull the common parts of functions out so they can be reused by both
DM and non-DM code paths. The recv() function had to be reworked to
fit into this scheme and this means it now only receives one packet
at a time instead of spinning in an endless loop.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Instead of using the non-DM-only name and enetaddr in struct eth_device,
add pointers into the private data which can either point to that non-DM
name or a DM one later on.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Instead of using the non-DM-only iobase in struct eth_device, add
one into the private data to make DM and non-DM operation possible.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Get rid of the global point to private data, and rather pass it
thought dev->priv. Also remove the unnecessary check for lp being
non-NULL, since it is always NULL at this point.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Instead of using eth_device priv for this PCI devbusfn, free it
so it could be used for driver private data, and wrap devbusfn
into those driver private data.
Note that using the name dev for the variable is a trick left for
later, when DM support is in place, so dm_pci_virt_to_mem() can be
used with minimal ifdeffery.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Remove those as they are not needed anymore.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Move the function at the end of the driver, so we could drop
various forward declarations later. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The private data allocation does not have to be done every time the
NIC is initialized at run time, move the allocation to initialize
function, which means it will be done only once when the driver
starts.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
This combination of functions can be replaced with calloc(),
make it so.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The current code is horribly complex. Both the RX and TX buffer
descriptors are 16 bytes in size, the init block is 32 bytes in
size, so simplify the code such that the entire private data of
the driver are allocated cache aligned and the RX and TX buffer
descriptors are part of the private data.
This removes multiple malloc calls and cache flushes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Use this macro to fully fill the PCI device ID table. This is mandatory
for the DM PCI support, which checks all the fields.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
All of one PCNET users has this option set, make this default
and drop this config option.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Use struct pcnet_priv all over the place instead.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
This change allows more fine tuning of driver model based SPI support in
SPL and TPL. It is now possible to explicitly enable/disable the DM_SPI
support in SPL and TPL via Kconfig option.
Before this change it was necessary to use:
/* SPI Flash Configs */
#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#undef CONFIG_SPI_FLASH_MTD
#endif
in the ./include/configs/<board>.h, which is error prone and shall be
avoided when we strive to switch to Kconfig.
The goal of this patch:
Provide distinction for DM_SPI support in both U-Boot proper and SPL (TPL).
Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must
still support non DM driver.
Another use case is the conversion of non DM/DTS SPI driver to support
DM/DTS. When such driver needs to work in both SPL and U-Boot proper, the
distinction is needed in Kconfig (also if SPL version of the driver
supports OF_PLATDATA).
In the end of the day one would have to support following use cases (in
single driver file - e.g. mxs_spi.c):
- U-Boot proper driver supporting DT/DTS
- U-Boot proper driver without DT/DTS support (deprecated)
- SPL driver without DT/DTS support
- SPL (and TPL) driver with DT/DTS (when the SoC has enough resources to
run full blown DT/DTS)
- SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have constrained
environment with no fitImage and OF_LIBFDT support).
Some boards do require SPI support (with DM) in SPL (TPL) and some only
have DM_SPI{_FLASH} defined to allow compiling SPL.
This patch converts #ifdef CONFIG_DM_SPI* to #if CONFIG_IS_ENABLED(DM_SPI)
and provides corresponding defines in Kconfig.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[trini: Fixup a few platforms]
Signed-off-by: Tom Rini <trini@konsulko.com>
3480 is not valid XRES, use 3840 as default.
Fixes: 05c65a82c3 ("video: rockchip: Support 4K resolution for rk3399, HDMI")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
- fix banner string overwriting the logo on small displays
- fix splash warning when building for ARM64
- fix STM32 DSI driver to probe only on supported hardware
- fix memory corruption with DSI panel drivers
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Merge tag 'fixes-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- fix logo on mx6ul_14x14_evk with DM_VIDEO enabled
- fix banner string overwriting the logo on small displays
- fix splash warning when building for ARM64
- fix STM32 DSI driver to probe only on supported hardware
- fix memory corruption with DSI panel drivers
The EDP_LCDC_SEL bit has to be set correctly to select vop0 or
vop1, but so far we have set it in both conditions, which is not
correct.
Can someone verify this is the correct way round? vop1 -> set,
vop0 -> clear?
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fill characteristics of DSI data link to platform data instead of
mipi device to avoid memory corruption.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Fill characteristics of DSI data link to platform data instead of
mipi device to avoid memory corruption.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Copy the DSI data link characteristics from panel
platform data to mipi DSI device.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Check the hardware version of DSI. Versions 1.30 & 1.31 are only
supported.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
Fix the bug that multiple lines wraps to overwrite logo bmp
display.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
Update video bmp code so that we can display 8 bits logo on
24 or 32 bpp framebuffer.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
The commit 84a6a27ae3 ("rockchip: rk3188: init CPU freq in clock
driver") changed ARM clock from 600MHz to 1600MHz. It made boot
unstable due to the fact that PMIC at the start generates insufficient
voltage for operation. See also: commit f4f57c58b5 ("rockchip:
rk3188: Setup the armclk in spl").
Fixes commit 84a6a27ae3 ("rockchip: rk3188: init CPU freq in clock
driver").
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update this value with the address of a video device so that it shows with
the 'bd' command.
It would be better to obtain the address from the uclass by looking in
struct video_uc_platdata for each device. We can move over to that once
DM_VIDEO migration is complete.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default
ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform
Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board
mmc:
- minor GD pointer removal
net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver
spi:
- Cleanup global macros for xilinx spi drivers
firmware:
- Add support for pmufw reloading
fpga:
- Improve error status reporting
common:
- Remove 4kB addition space for FDT allocation
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Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2020.10
Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default
ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform
Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board
mmc:
- minor GD pointer removal
net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver
spi:
- Cleanup global macros for xilinx spi drivers
firmware:
- Add support for pmufw reloading
fpga:
- Improve error status reporting
common:
- Remove 4kB addition space for FDT allocation
The index used to iterate over the possible PHYs in axiemac_phy_init was an
unsigned int and decremented. Therefor it was always >= 0 and never exited
the loop.
Signed-off-by: Patrick van Gelder <patrick.vangelder@nl.bosch.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fpga returns error value when fails, error status should be
printed in hex format.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove below config options and convert them to macros. They have never
been configured to different values than default one. And also it makes
sense to reduce the config_whitelist.
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_XILINX_SPI_IDLE_VAL
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Disable PCS autonegotiation if fixed-link node is present in device tree.
This way systems with multiple GEM instances with a combination of
SGMII-fixed and SGMII-PHY will work.
Reported-by: Goran Marinkovic <goran.marinkovic@psi.ch>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In case of aes decryption destination address range must be flushed
before transferring decrypted data to destination.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
AES engine cannot be used if has not been enabled at boot time
with an encrypted boot image.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch checks fpga config completion when a bitstream is loaded
into PL.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Correct the PL bitstream loading sequence for zynqaes command by
clearing the loaded PL bitstream before loading the new encrypted
bitstream using the zynq aes command. This was done by setting
the PROG_B same as in case of fpgaload commands.
This patch fixes the issue of loading the encrypted PL bitstream
onto the PL in which a bitstream has already been loaded
successfully.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no need to panic all the time when pmufw config object loading
failed. The patch improves function logic to report permission deny case
and also panic only for SPL case.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
alt_ref_clk is applicable only for PS extended version.
For PS base version there is no separate alt_ref_clk.
It is tied with ref_clk, so remove it from driver.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
SDHCI HISPD bits need to be configured based on desired mmc
timings mode and some HISPD quirks.
So, handle the HISPD bit based on the mmc computed selected
mode(timing parameter) rather than fixed mmc card clock
frequency.
Linux handle the HISPD similar like this in below commit but no
SDHCI_QUIRK_BROKEN_HISPD_MODE,
commit <501639bf2173> ("mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling")
This eventually fixed the mmc write issue observed in
rk3399 sdhci controller.
Bug log for refernece,
=> gpt write mmc 0 $partitions
Writing GPT: mmc write failed
** Can't write to device 0 **
** Can't write to device 0 **
error!
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Peng Fan <peng.fan@nxp.com>
Peng Fan: added back "ctrl &= ~SDHCI_CTRL_HISPD;" per Jaehoon's suggestion
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> # roc-rk3399-pc
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
According to eMMC specification v5.1 section 6.4.3, we should issue
CMD1 repeatedly in the idle state until the eMMC is ready even if
mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC
devices seems to enter the inactive mode after mmc_complete_op_cond()
issued CMD0 when the eMMC device is busy.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
In current code, we add 1ms dealy after each tuning command for standard
tuning method. Adding this 1ms dealy is because USDHC default check the
CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning
IC logic do not wait for the tuning data sending out by the card, trigger
the buffer read ready interrupt immediately, and step to next cycle. So
when next time the new tuning command send out by USDHC, card may still
not send out the tuning data of the upper command，then some eMMC cards
may stuck, can't response to any command, block the whole tuning procedure.
If do not check the CMD CRC for tuning, then do not has this issue. USDHC
will wait for the tuning data of each tuning command and check them. If the
tuning data pass the check, it also means the CMD line also okay for tuning.
So this patch disable the CMD CRC check for tuning, save some time for the
whole tuning procedure.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
This patch try to avoids eviction of dirty lines during DMA
transfer. The code right now execute the following step:
- allocate the buffer
- start a dma operation using the non-coherent dma buffer
- invalidate cache lines associated with the buffer
- read the buffer
This can lead to reading back not valid information, because the cache
controller could evict dirty cache lines belonging to the buffer *after*
the DMA operation has started to fill the DRAM.
In order to avoid this, a new invalidation is required *before* starting
the DMA operation. The patch just adds an invalidation before submitting
the DMA command.
Example below shows the nvme disk scan result without the following
patch
=> nvme scan
nvme_get_info_from_identify: nn = 544502629, vwc = 100,
sn = dev_0T, mn = `�\�, fr = t_part, mdts = 105
So, invalidating the cache before submitting the admin command,
fix the cpu read.
Cc: André Przywara <andre.przywara@arm.com>
Reported-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since the i.MX8 GPIO banks are indexed from 0 not 1 on other i.MX
platforms, so we have to adjust the index accordingly.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
As we move towards driver model, it is required to let the FEC driver
know how to properly deal with an Ethernet PHY subnode in the device tree.
For example:
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
reg = <0>;
qca,clk-out-frequency = <125000000>;
};
};
};
Currently the PHY node pointer is incorrectly associated with the
Ethernel controller instead of the PHY node itself.
This causes the PHY properties, such as "qca,clk-out-frequency" in
the example above to not get parsed.
Fix this problem by populating the phy_of_node node.
Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
The clock ouput frequency is calculated incorrectly for AR8035 due to
wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
This same issue has been already fixed in the kernel by:
commit b1f4c209d84057b6d40b939b6e4404854271d797
Author: Oleksij Rempel <o.rempel@pengutronix.de>
Date: Wed Apr 1 11:57:32 2020 +0200
net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
for the values that comprise the fields, not zero-bits-set.
This patch fixes the clock frequency configuration for ATH8030 and
ATH8035 Atheros PHYs by removing the erroneous "~".
To reproduce this bug, configure the PHY with the device tree binding
"qca,clk-out-frequency" and remove the machine specific PHY fixups.
Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Apply the same fix in the U-Boot driver.
Tested on a i.MX6 Hummingboard.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Tested-by: Tom Rini <trini@konsulko.com>
- use 'vidconsole' stdout in nitrogen6x upgrade script
- add option for selection of the vidconsole commands
lcdputs and setcurs
- allow building ipuv3 driver with disabled CONFIG_PANEL
- make backlight and panel drivers optional
- remove useless code from ipuv3 driver
- extend existing DM_VIDEO work-around for console name
to support 'vga'
- remove non-DM code in ipuv3
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Merge tag 'video-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-video into next
- migrate remaining imx5/imx6qd boards to DM_VIDEO
- use 'vidconsole' stdout in nitrogen6x upgrade script
- add option for selection of the vidconsole commands
lcdputs and setcurs
- allow building ipuv3 driver with disabled CONFIG_PANEL
- make backlight and panel drivers optional
- remove useless code from ipuv3 driver
- extend existing DM_VIDEO work-around for console name
to support 'vga'
- remove non-DM code in ipuv3
When CONFIG_OF_LIVE is enabled, dev_of_offset() cannot be used and
if used returns an invalid offset. This causes the call to
fdt_stringlist_get() in the psci_probe() to fail to read the 'method'
property from the PSCI node for the device and hence prevents PSCI
from working. Fix this by using the ofnode_read_string() API instead
of the fdt_stringlist_get() because this will handle reading the
property both when CONFIG_OF_LIVE is enabled or disabled.
Due to the above problem and since commit 81ea00838c ("efi_loader:
PSCI reset and shutdown") was added, the EFI system reset has been
broken for Tegra210 and Tegra196 platforms. This also fixes the EFI
system reset for these Tegra platforms.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Add Kconfig entries for the pcnet driver and convert MIPS malta
to use those.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
With all the changes in place, add support for DM into the
pcnet driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Pull the common parts of functions out so they can be reused by both
DM and non-DM code paths. The recv() function had to be reworked to
fit into this scheme and this means it now only receives one packet
at a time instead of spinning in an endless loop.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Instead of using the non-DM-only name and enetaddr in struct eth_device,
add pointers into the private data which can either point to that non-DM
name or a DM one later on.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Instead of using the non-DM-only iobase in struct eth_device, add
one into the private data to make DM and non-DM operation possible.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Get rid of the global point to private data, and rather pass it
thought dev->priv. Also remove the unnecessary check for lp being
non-NULL, since it is always NULL at this point.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Instead of using eth_device priv for this PCI devbusfn, free it
so it could be used for driver private data, and wrap devbusfn
into those driver private data.
Note that using the name dev for the variable is a trick left for
later, when DM support is in place, so dm_pci_virt_to_mem() can be
used with minimal ifdeffery.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Remove those as they are not needed anymore.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Move the function at the end of the driver, so we could drop
various forward declarations later. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The private data allocation does not have to be done every time the
NIC is initialized at run time, move the allocation to initialize
function, which means it will be done only once when the driver
starts.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
This combination of functions can be replaced with calloc(),
make it so.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The current code is horribly complex. Both the RX and TX buffer
descriptors are 16 bytes in size, the init block is 32 bytes in
size, so simplify the code such that the entire private data of
the driver are allocated cache aligned and the RX and TX buffer
descriptors are part of the private data.
This removes multiple malloc calls and cache flushes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Use this macro to fully fill the PCI device ID table. This is mandatory
for the DM PCI support, which checks all the fields.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
All of one PCNET users has this option set, make this default
and drop this config option.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Use struct pcnet_priv all over the place instead.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Split the common code from the non-DM code, so it can be reused by
the DM code later. As always, the recv() function had to be split
into the actual receiving part and free_pkt part to fit with the
DM.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
The RX/TX DMA descriptor rings are per-device-instance private data,
so move them into the private data.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Instead of doing ethernet device lookup by name every time there
is an MDIO access, pass the driver private data via mdiobus priv
to the MDIO bus accessors.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This patch replaces the various uses of struct eth_device for accessing
device private data with struct eepro100_priv, which is compatible both
with DM and non-DM operation.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This is a trick in preparation for adding DM support. By passing in
the PCI BDF into the bus_to_phys()/phys_to_bus() macros and calling
that dev, we can substitute dev with udevice when DM support lands
and do minor adjustment to the macros to support both DM and non-DM
operation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Drop the inline keyword from the static functions, the compiler has a
much better overview and can decide how to inline those functions much
better.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Those macros depended on specific variable names to be declared
at their usage sites, fix this by adding an argument to those
macros and also protect the argument with braces.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Pull the MII registration code into a separate function. Moreover,
properly free memory in case any of the registration or allocation
functions fail, so this fixes an existing memleak.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Use this macro to fully fill the PCI device ID table. This is mandatory
for the DM PCI support, which checks all the fields.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Move the functions around in the driver to prepare it for DM conversion.
Drop forward declarations which are not necessary anymore. No functional
change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Remove all the remaining use of the 'volatile' keyword, as this is
no longer required. All the accesses which might have needed this
use of 'volatile' have been repaired properly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Add cache invalidation and flushes wherever the DMA descriptors are
written or read, otherwise this driver cannot work reliably on any
systems where caches are enabled.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This code is replicated in the driver thrice almost verbatim, factor
it out into a separate function and clean it up. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
The current eepro100 driver accesses its memory mapped registers directly
instead of using the standard I/O accessors. This can cause problems on
some systems as the accesses can get out of order. So convert the direct
volatile dereferences to use the normal in/out macros.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This is automated cleanup via checkpatch, no functional change.
./scripts/checkpatch.pl --show-types -f drivers/net/eepro100.c
./scripts/checkpatch.pl --types INDENTED_LABEL -f --fix --fix-inplace drivers/net/eepro100.c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This is automated cleanup via checkpatch, no functional change.
./scripts/checkpatch.pl --show-types -f drivers/net/eepro100.c
./scripts/checkpatch.pl -f --fix --fix-inplace drivers/net/eepro100.c
This fixes all the remaining errors except a couple of comments which
are longer than 80 characters, all the volatile misuse and all the
camelcase, that needs a separate patch.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This is automated cleanup via checkpatch, no functional change.
./scripts/checkpatch.pl --show-types -f drivers/net/eepro100.c
./scripts/checkpatch.pl --types INDENTED_LABEL -f --fix --fix-inplace drivers/net/eepro100.c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This is automated cleanup via checkpatch, no functional change.
./scripts/checkpatch.pl --show-types -f drivers/net/eepro100.c
./scripts/checkpatch.pl --types POINTER_LOCATION -f --fix --fix-inplace drivers/net/eepro100.c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This is automated cleanup via checkpatch, no functional change.
./scripts/checkpatch.pl --show-types -f drivers/net/eepro100.c
./scripts/checkpatch.pl --types PARENTHESIS_ALIGNMENT -f --fix --fix-inplace drivers/net/eepro100.c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This is automated cleanup via checkpatch, no functional change.
./scripts/checkpatch.pl --show-types -f drivers/net/eepro100.c
./scripts/checkpatch.pl --types BRACES -f --fix --fix-inplace drivers/net/eepro100.c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This is automated cleanup via checkpatch, no functional change.
./scripts/checkpatch.pl --show-types -f drivers/net/eepro100.c
./scripts/checkpatch.pl --types SPACING -f --fix --fix-inplace drivers/net/eepro100.c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This code is never enabled, last board that used it was ELPPC which
was removed some 5 years ago, so just remove this code altogether.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
cfb_console driver uses 'vga' console name and we still have board
environments defining this name. Re-use existing DM_VIDEO work-
around for console name to support 'vga' name in stdout environment.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Soeren Moch <smoch@web.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
To enable DM_VIDEO we must decrease binary size to fix build
breakage for some boards, so drop not needed code. Also add
!DM_VIDEO guards which can be later removed when last non DM
users will be converted.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Not all boards use these drivers, so allow to disable them to fix
building boards with U-Boot binary image size restrictions.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Converting some boards to DM_VIDEO results in build breakage due
to increased code size. Make video console specific commands
optional to reduce binary size.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Modify the Freescale ESPI driver to support the driver model.
Also resolved the following problems:
===================== WARNING ======================
This board does not use CONFIG_DM_SPI. Please update
the board before v2019.04 for no dm conversion
and v2019.07 for partially dm converted drivers.
Failure to update can lead to driver/board removal
See doc/driver-model/MIGRATION.txt for more info.
====================================================
===================== WARNING ======================
This board does not use CONFIG_DM_SPI_FLASH. Please update
the board to use CONFIG_SPI_FLASH before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
We generate a number of helper inline functions to make accesses easier.
However not all permutations of each function will be used and clang
will warn about unused ones. Decorate all of them with __maybe_unused
because of this.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
We only call the function omap_hsmmc_get_cfg in the case of OMAP34XX or
when we have to iodelay recalibration. Add guards for these checks as
clang will otherwise warn.
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
In the case of non-DM_GPIO the function get_gpio_index() will never be
called, and clang will warn about this. Move this to be with the other
non-DM code for easier removal later.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
AM654x PG1.0 has a silicon bug that D+ is pulled high after POR, which
could cause enumeration failure with some USB hubs. Disabling the
USB2_PHY Charger Detect function will put D+ into the normal state.
Using property "ti,dis-chg-det-quirk" in the DT usb2-phy node to
enable this workaround for AM654x PG1.0.
Signed-off-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
The fix in commit b7adcdd073 has the side-effect that the regulator
will be disabled when requesting the relevant gpio in
regulator_common_ofdata_to_platdata() and enabled in
regulator_pre_probe() when the regulator was already enabled.
This leads to a short interruption in the 3.3V power to the PCIe
slot on the firefly-rk3399 which makes an ADATA SX8000NP NVMe SSD
unhappy.
Fix this by setting the GPIOD_IS_OUT_ACTIVE flag again when the
'regulator-boot-on' property is set, but check for this property
explicitly instead of relying on the "boot_on" member of
the uclass platdata.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Unsupported voltage on voltage switch is not an error, do not
print error message in such a case. This happens e.g. if the
eMMC is already in 1V8 mode or when testing 1V2 mode operation
on systems which only do 3V3/1V8 switching.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The 3V3/1V8 switching could never have worked on any of the iMXes
ever since 51313b49f2 ("mmc: fsl_esdhc: support SDR104 and HS200"),
because that commit uses priv->vqmmc_dev when switching voltages on
mode switch, while local vqmmc_dev in probe to store the regulator
pointer. Those are two different variables with the same name. So
the priv->vqmmc_dev was always NULL and thus voltage switch between
modes never really suceeded.
Fix this by assigning priv->vqmmc_dev with value of the vqmmc_dev
in probe.
Fixes: 51313b49f2 ("mmc: fsl_esdhc: support SDR104 and HS200")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
- Rename DT compatible name
- Remove uneccessary if-statement to support 8-bit buswidth
- Remove redundant error msg
- Use symbolic constants in switch statement
Signed-off-by: Arthur Li <arthur.li@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Tom Rini <trini@konsulko.com>
When eSDHC operates at 3.3v, damage can accumulate in an internal
level shifter at a higher than expected rate. The faster the interface
runs, the more damage accumulates. This issue now is found on LX2160A
eSDHC1 for only SD card.
The hardware workaround is recommended to use an on-board level shifter
that is 1.8v on SoC side and 3.3v on SD card side.
For boards without hardware workaround, this option could be enabled,
ensuring 1.8v IO voltage and disabling eSDHC if no card.
This option assumes no hotplug, and u-boot has to make all the way to
to linux to use 1.8v UHS-I speed mode if has card.
If you do not want the workaround for better user experience, of course
you can choose to not select it running eSDHC in unsafe mode.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Update the firmware to improve compatibility for none-intel USB
host controller. The more information is as following.
The device has auto-installed driver feature - via switch CD-ROM/NIC
mode. But in some corner cases, it would switch to CD-ROM unexpected.
This issue results in Lan Function Disabled.
While USB PHY transits to P3 from P0 due to the absent of transmitter
control, it would issues undefined signal to its link partner.
Some Down Stream Port misidentify the undefined signal as wakeup
signal. So the link state will not keep in suspend even the system
is idle.
Signed-off-by: Hayes Wang <hayeswang@realtek.com>
Cleanup this driver to use dt in U-boot and static platdata in SPL.
This requires the following steps:
1. Move all platdata assignment from probe() to ofdata_to_platdata().
This function is only called in U-boot.
2. Replicate all the platdata assignment being done in
ofdata_to_platdata() in the omapl138 board file. This data is used in
the SPL case where SPL_OF_CONTROL is not enabled.
3. Remove SPL_OF_CONTROL and related configs from omapl138_lcdk_defconfig
This cleanup effectively reverts 3ef94715cc ('mmc: davinci: fix mmc boot in SPL')
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
change to how sequence numbers are assigned to devices
minor fixes and improvements
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Merge tag 'dm-pull-12jun20' of git://git.denx.de/u-boot-dm into next
patman improvements to allow it to work with Zephyr
change to how sequence numbers are assigned to devices
minor fixes and improvements
Do not re-read the HW address from the EEPROM on every start of
transfer, otherwise the user will not be able to adjust ethaddr
as needed. Read the address only once, when the card is detected.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Use this macro to fully fill the PCI device ID table. This is mandatory
for the DM PCI support, which checks all the fields.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Split the driver into common and non-DM functionality, so that the
DM support can later re-use the common code, while we retain the
non-DM code until all the platforms are converted.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Instead of always calling rtl8139_eeprom_delay() with priv->ioaddr,
call it with priv and let the function access priv->ioaddr. This
reduces code duplication and has no impact, since the compiler will
inline this as needed anyway.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Introduce rtl8139_pdata, which is a super-structure around eth_device
and tracks per-device state, here the device IO address, PCI BDF, RX
and TX ring position. Pass this structure around instead of the old
non-DM eth_device in preparation for DM conversion.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
These macros depended on the dev variable being declared wherever
they were used. This is wrong and will not work with DM anyway, so
pass only the PCI BFD into these macros, which fixes the dependency
and prepares them for DM support as well.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Replace the use of custom static ioaddr variable with common dev->iobase,
no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Replace malloc()+memset() combination with calloc(), no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Pull the device name setting into a separate function, as this
will be shared between DM/non-DM variants.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Add the DP8382X generic PHY registration to the TI PHY init file.
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
ti_phy_init function was allocated to the DP83867 PHY. This function
name is to generic for a specific PHY. The function can be moved to a
TI specific file that can register all TI PHYs that are defined in the
defconfig. The ti_phy_init file will contain all TI PHYs initialization
so that only phy_ti_init can be called from the framework.
In addition to the above the config flag for the DP83867 needs to be changed
in the Kconfig and dependent defconfig files. The config flag that was
used for the DP83867 was also generic in nature so a more specific
config flag for the DP83867 was created.
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
There are devices accesible through mdio clause-45, such as
retimers, that do not have PMA or PCS blocks.
This patch adds MDIO_MMD_VEND1 on the list of device addresses
where phyid is searched. Previous order of devices was kept.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
This is a WAR for DHCP failure after rebooting from the L4T kernel. The
r8169.c kernel driver is setting bit 19 of the rt816x HW register 0xF0,
which goes by FuncEvent and MISC in various driver source/datasheets.
That bit is called RxDv_Gated_En in the r8169.c kernel driver. Clear it
here at the end of probe to ensure that U-Boot can get an IP assigned
via DHCP.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Linux commit 232ba3a51cc2 ('net: phy: Micrel KSZ8061: link failure after
cable connect') implements a fix for the above errata.
This patch replicates that errata fix in an ksz8061 specific init routine.
Signed-off-by: Bryan O'Donoghue <bod@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If there are aliases for an uclass, set the base for the "dynamically"
allocated numbers next to the highest alias.
Please note, that this might lead to holes in the sequences, depending
on the device tree. For example if there is only an alias "ethernet1",
the next device seq number would be 2.
In particular this fixes a problem with boards which are using ethernet
aliases but also might have network add-in cards like the E1000. If the
board is started with the add-in card and depending on the order of the
drivers, the E1000 might occupy the first ethernet device and mess up
all the hardware addresses, because the devices are now shifted by one.
Also adapt the test cases to the new handling and add test cases
checking the holes in the seq numbers.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Tested-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Michal Simek <michal.simek@xilinx.com> [on zcu102-revA]
It is possible to specify a device tree node for an USB device. This is
useful if you have a static USB setup and want to use aliases which
point to these nodes, like on the Raspberry Pi.
The nodes are matched against their hub port number, the compatible
strings are not matched for now.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
In regmap_raw_{read,write}_range(), offsets are checked to make sure
they aren't out of range. But this check happens _after_ the address is
mapped from physical memory. Input should be sanity-checked before using
it. Mapping the address before validating it leaves the door open to
passing an invalid address to map_physmem(). So check for out of range
offsets _before_ mapping them.
This fixes a segmentation fault in sandbox when -1 is used as an offset
to regmap_{read,write}().
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Now all boards which are using davinci SPI driver
have moved to SPL_DM so drop the unneeded non-dm code.
Cc: Adam Ford <aford173@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
atmel_spi.h has register offsets, and atmel_spi_slave
structure, move it into .c file for better readability
and drop atmel_spi.h
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
atmel spi driver now accessible only when DM_SPI enabled.
So, remove nondm code.
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
- Deadline for DM migration already passed by months.
- Sent couple of zap patches and
- No response on dm conversation
hence removed the driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Order the macros, private structures and simple functions
in a proper way to have more code readability.
No functionality changed.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Deadline for DM migration already passed by months
and no response on full dm conversation hence removed
the nondm code.
Note: Look like there is no user for nondm code
for this driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add the missing Kconfig dependency and let VIRTIO_RNG default to yes.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Debug console is the part of serial driver in the same file. It means to be
able to enable debug console you also need to enable driver itself.
That's why add all dependecies and list only debug consoles which are
enabled based on driver selection to avoid compilation error when user
asks for certain debug console but driver is not enable for it.
Error:
aarch64-linux-gnu-ld.bfd: common/built-in.o: in function `putc':
/home/monstr/data/disk/u-boot/common/console.c:513: undefined reference to `printch'
aarch64-linux-gnu-ld.bfd: common/built-in.o: in function `puts':
/home/monstr/data/disk/u-boot/common/console.c:563: undefined reference to `printch'
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Fix ns16550 dependency, add ZYNQ_SERIAL, change S5P]
Signed-off-by: Tom Rini <trini@konsulko.com>
The symbol "CONFIG_ARM_DCC" is used to control building
drivers/serial/arm_dcc.c. Provide a simple Kconfig entry for this.
Cc: Luca Ceresoli <luca@lucaceresoli.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Tom McLeod <tom.mcleod@opalkelly.com>
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
When an eTSEC is configured to use TBI, configuration of the
TBI is done through the MIIM registers for that eTSEC.
For example, if a TBI interface is required on eTSEC2, then
the MIIM registers starting at offset 0x2_5520 are used to
configure it.
Fixes: 9a1d6af55e ("net: tsec: Add driver model ethernet support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The current code accesses eTSEC registers using physical
address directly, it's not correct, though no problem on
current platforms. It won't work on platforms, which does
not support 1:1 virtual-physical address map.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Allow the MDIO devices to be probed based on the device tree.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
U-Boot ethernet works with FSBL flow where releasing ethernet clock
reset is part of FSBL itself but with the SPL, We need to release
ethernet clock reset explicitly for U-Boot proper. With this change
Release ethernet clock reset code in FSBL might not be needed or
unaffected.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Release ddr clock reset once clock is initialized
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Added clock enable and disable functions in prci ops
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Added a misc driver to handle OTP memory in SiFive SoCs.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
A compilation error appears when QE is compiled with DM_ETH
enabled:
drivers/qe/uec.c: In function 'init_phy':
drivers/qe/uec.c:425:28: error: dereferencing pointer to incomplete type 'struct eth_device'
uec = (uec_private_t *)dev->priv;
^~
drivers/qe/uec.c: In function 'uec_initialize':
drivers/qe/uec.c:1357:43: error: invalid application of 'sizeof' to incomplete type 'struct eth_device'
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
^~~~~~
The patch disables CONFIG_QE when CONFIG_DM_ETH is set.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This config option depends on EXT4 support.
If Ext4 write capability is not selected, it generate write error messages
and is unable to maintain boot counter.
Signed-off-by: Frédéric Danis <frederic.danis@collabora.com>
This is defined in the asm/cache.h header file. Update this header file to
include it so it gets the same value consistently across U-Boot.
This fixes 'usb host' on omapl138_lcdk.
Fixes: 90526e9fba ("common: Drop net.h from common header")
Reported-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present this logic does not work on link and samus, since their SPI
controller is not a PCI device, but a child of the PCH.
Unfortunately, fixing this involves a lot of extra logic. Still, this was
requested in the review of the fix-up patch, so here it is.
Fixes: 92842147c3 ("spi: ich: Add support for get_mmap() method")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)
The H6 EMAC is very similar to the H3 variant, except that it uses the
same pinmux as R40. Add support for it.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
While the R40 uses a different register for EMAC clock configuration
than other chips, the register has a very similar layout. Reuse the
existing bitfield definitions in this file, since they match.
This allows the driver to compile on the H6 platform, where the
CCM_GMAC_CTRL definitions are not present.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
dm_spi_slave_platdata used in sf_probe for printing
plat->cs value and there is no relevant usage apart
from this.
We have enough debug messages available in SPI and SF
areas so drop this plat get and associated bug statement.
Cc: Simon Glass <sjg@chromium.org>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Currently spi-nor code is assigning _write ops for SST
and other flashes separately.
Just call the sst_write from generic write ops and return
if SST flash found, this way it avoids the confusion of
multiple write ops assignment during the scan and makes
it more feasible for code readability.
No functionality changes.
Cc: Simon Glass <sjg@chromium.org>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The get_sw_write_prot API is used to get the write-protected
bits of flash by reading the status register and other wards
it's API for reading register bits.
1) This kind of requirement can be achieved using existing
flash operations and flash locking API calls instead of
making a separate flash API.
2) Technically there is no real hardware user for this API to
use in the source tree.
3) Having a flash operations API for simple register read bits
also make difficult to extend the flash operations.
4) Instead of touching generic code, it is possible to have
this functionality inside spinor operations in the form of
flash hooks or fixups for associated flash chips.
Considering all these points, this patch drops the get_sw_write_prot
and associated code bases.
Cc: Simon Glass <sjg@chromium.org>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Use CONFIG_IS_ENABLED to prevent ifdef in sf_probe.c
Cc: Simon Glass <sjg@chromium.org>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
sh_spi driver is deprecated, no active updates and
no board user, hence dropped the same.
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
CF_SPI kconfig option defined twice with DM_SPI
and non DM_SPI.
Drop the non DM_SPI side kconfig definition.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
- Fix mmc of path after syncfrom kernel dts;
- Add dwc3 host support with DM for rk3399;
- Add usb2phy and typec phy for rockchip platform;
- Migrate board list doc to rockchip.rst;
- Add rk3399 Pinebook Pro board support;
- Update dram_init in board_init and add memory node in SPL;
Including the assembler headers before including common.h etc leads to
compilation errors upon MIPS64 based platforms using OF_LIVE. This
patch reorders the include files to the "correct" oder.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Print the error code if the regulator enable fails, otherwise the error
message is rather useless and confusing.
Signed-off-by: Marek Vasut <marex@denx.de>
The regulator-fixed would return -ENOSYS when enabled/disabled,
because this operation is not supported, but this is not an error
e.g. on systems where the VBUS cannot be controlled, so if this
is the error code reported by the regulator core, consider it a
success and continue.
Signed-off-by: Marek Vasut <marex@denx.de>
Although I think it never occurs, the code doesn't make sense, because
it may allow to assign an IN endpoint to ss->ep_out.
Signed-off-by: Hayes Wang <hayeswang@realtek.com>
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).
Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with Retry=1 and Nump != 0.
Doing so will give controller a chance to recover from transient error
conditions.
Reference from below Linux commit,
commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature
in the controller")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.
When use this quirk, the controller implements a fixed 40-bit
TxEndDelay after the packet is given on UTMI and ignores the
linestate during the transmit of a token (during token-to-token
and token-to-data IPGAP).
On some rockchip platforms (e.g. rk3399), it requires to disable
the u2mac linestate check to decrease the SSPLIT token to SETUP
token inter-packet delay from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.
Reference from below Linux commit,
commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate
check quirk")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Add USB TYPEC PHY driver for rockchip platform.
Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable/Disable TCPHY clock for rk3399 platform.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
So, mark them as empty in clock otherwise device probe on
those typec phy driver would fail.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The vpcie*-supply properties are optional and these are absent on
boards like the ROCKPro64 and Firefly RK3399 where the voltage is
supplied by always-on regulators that are already enabled upon
boot. Make these regulators optional and properly check their
presence before attempting to enable them.
Makes PCIe work on un U-Boot on the boards mentioned above.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Actual eMMC get_clk register is clksel_con22 instead of
clksel_con21.
Fix it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Because of this commit :
5ae84860b0 ("misc: i2c_eeprom: verify that the chip is functional at probe()")
at probe time, each eeprom is tested for read at offset 0.
The Atmel AT24MAC402 eeprom has different mapping. One i2c slave address is
used for the lower 0x80 bytes and another i2c slave address is used for the
upper 0x80 bytes. Because of this basically the i2c master sees 2 different
slaves. We need the upper bytes because we read the unique MAC address from
this EEPROM area.
However this implies that our slave address will return error on reads
from address 0x0 to 0x80.
To solve this, implemented an offset field inside platform data that is by
default 0 (as it is used now), but can be changed in the compatible table.
The probe function will now read at this offset and use it, instead of blindly
checking offset 0.
This will fix the regression noticed on these EEPROMs since the commit
abovementioned that introduces the probe failed issue.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
When compiling with -Wtype-limits we see this error:
drivers/i2c/i2c-uclass.c: In function ‘i2c_deblock_gpio_loop’:
drivers/i2c/i2c-uclass.c:517:21: error: comparison of
unsigned expression >= 0 is always true [-Werror=type-limits]
517 | while (scl_count-- >= 0) {
|
Don't loop forever.
Fixes: 1f746a2c82 ("i2c: Make deblock delay and SCL clock configurable")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
If the device doesn't return a version that means the device is
non-functional.
The dw_i2c_regs had invalid offsets for the version field. I got the
correct value from the DesignWare databook. It also matches what the
Picasso PPR says.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested on chromebook_coral:
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we still have pre-driver-model code in this driver and it makes
things a bit confusing. In particular calc_bus_speed() is called with priv
as NULL if not using driver model.
This results in spk_cnt and comp_param1 being read from an invalid address
if not using driver model. For comp_param1 this may not cause problems if
reading from addresses close to 0 happens to be allowed, as high speed is
only supported by DM code. But spk_cnt is subsequently used to calculate
the bus periods and so this may cause problems (e.g. on spear600 board
which has not been migrated yet).
Add a new parameter regs parameter to calc_bus_speed() and add more
comments to this function and to _dw_i2c_set_bus_speed(), which calls it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add support for new Kioxia products.
The new Kioxia products support program load x4 command, and have
HOLD_D bit which is equivalent to QE bit.
Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The suffix was changed from "G" to "J" to classify between 1st generation
and 2nd generation serial NAND devices (which now belong to the Kioxia
brand).
As reference that's
1st generation device of 1Gbit product is "TC58CVG0S3HRAIG"
2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ".
The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and
the prefix was changed from "TC58" to "TH58".
Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*().
Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
It is possible that users of generic_phy_*() APIs may pass a valid
struct phy pointer but phy->dev can be NULL, leading to NULL pointer
deference in phy_dev_ops().
So call generic_phy_valid() to verify that phy and phy->dev are both
valid.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Convert CONFIG_KS8851_MLL and CONFIG_KS8851_MLL_BASEADDR to Kconfig
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Add support for U-Boot DM and DT probing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Instead of reading out the entire FIFO and possibly overwriting U-Boot
memory, read out one packet per recv call, pass it to U-Boot network
stack, and repeat. It is however necessary to cache RXFC value, because
reading that one out clears it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Split network handling functions into non-DM specific parts and
common code in preparation for conversion to DM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Introduce a private data structure for this driver with embedded
struct eth_device and pass it around. This prepares the driver to
work with both DM and non-DM systems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Fix various checkpatch complaints.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
There is only one chip ID in the table of chip IDs for this chip.
Read out the chip ID instead and mask off the last "revision" bit
to check the chip ID, this works for all chips in the family. Then
drop the chip ID passing around.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The packet status and length information should be extracted from the
FIFO per-packet. Adjust the code such that it reads the packet meta
data and then the packet afterward, if applicable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Most of the entries in the structure are useless, remove them. Inline
the rest of uses where applicable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Per KS8851-16MLL, the RXQCR is a 16bit register. Use 16bit accessors
to it consistently and drop the ks_wrreg8() function altogether, as
it is not used anymore.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The cached RXQCR value is never updated, remove the cache and just use
the bits in the cache directly in the code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Replace combination of malloc()+memset() with calloc() as the behavior
is exactly the same and the amount of code is reduced. Moreover, remove
printf() in the fail path, as it is useless, and return proper -ENOMEM
return code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
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Merge tag 'imx8qxp-fixes' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- Fix i.MX8QXP boot hang when getting CPU temperature
The phy_bulk pointer *usb_phys is used before allocated,
fix it by using a phy_bulk variable instead in
xhci_dwc3_platdata struct
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
The omap3.dtsi file shows the usbhshost node with two sub-nodes
for ohci and ehci. This patch file creates the usbhshost, and
pulls the portX-mode information. It then locates the EHCI
sub-node, and initializes the EHCI controller with the info
pulled from the usbhshost node.
There is still more to do since there isn't an actual link
between the 'phys' reference and the corresponding phy driver,
and there is no nop-xceiv driver yet.
In the meantime, the older style reference to
CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull
the phy out of reset until the phy driver is completed and the
phandle reference is made.
Signed-off-by: Adam Ford <aford173@gmail.com>
Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.
The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.
Say if we try to get the PCIe PHY then the phy-uclass
will look for PHY in the first instance if it is not
in the root node it will try to probe the parent by
assuming that the actual PHY is inside the parent PHY
of UCLASS_PHY. But, in rk3399 hardware representation
PHY like emmc, usb and pcie are part of syscon which
is completely a different of UCLASS_SYSCON.
Example:
grf: syscon@ff770000 {
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
pcie_phy: pcie-phy {
compatible = "rockchip,rk3399-pcie-phy";
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
#phy-cells = <1>;
resets = <&cru SRST_PCIEPHY>;
drive-impedance-ohm = <50>;
reset-names = "phy";
status = "disabled";
};
};
Due to this limitation, this patch adds a separate PHY
driver for Rockchip PCIe. This might be removed in future
once Generic PHY supports this limitation.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Enable/Disable the PCIEPHY clk for rk3399.
CLK is clear in both enable and disable functionality.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yes, most of the high speed peripheral clocks
in rk3399 enabled by default.
But it would be better to handle them via clk
enable/disable API for handling proper reset
conditions like 'usb reset' over command line.
So, enable USB, GMAC clock via enable/disable ops.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil.m@amarulasolutions.com> # roc-rk3399-pc
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Should initialization of pdata values have failed for some reason,
we end up in endless loop when getting the CPU temperature value
and can not boot. Check alert value in pdata and only retry reading
temperature if alert value is not zero. Also shorten the temperature
info string.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This fixes getting DT alert and critical pdata values in imx_scu_thermal
driver. On i.MX8QXP using not initialized alert pdata value resulted in
boot hang and endless loop outputting:
CPU Temperature (47200C) has beyond alert (0C), close to critical (0C) waiting...
While at it, preset CPU type values once to avoid multiple calls
of device_is_compatible() for same property.
Fixes: 3ee6ea443e ("cpu: imx_cpu: Print the CPU temperature for iMX8QM A72")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
CPU type and rate detection is broken, for A35 cpu we get A53:
...
sc_pm_get_clock_rate: resource:0 clk:2: res:3
Could not read CPU frequency: -22
CPU: NXP i.MX8QXP RevB A53 at 0 MHz at 47C
Fixes: 55bc96f3b6 ("cpu: imx8: fix get core name and rate")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
[ Linux commit 9afbe7c0140f663586edb6e823b616bd7076c00a ]
If the write protect signal from this IP is connected to the NAND
device, this IP can handle the WP# pin via the WRITE_PROTECT
register.
The Denali NAND Flash Memory Controller User's Guide describes
this register like follows:
When the controller is in reset, the WP# pin is always asserted
to the device. Once the reset is removed, the WP# is de-asserted.
The software will then have to come and program this bit to
assert/de-assert the same.
1 - Write protect de-assert
0 - Write protect assert
The default value is 1, so the write protect is de-asserted after
the reset is removed. The driver can write to the device unless
someone has explicitly cleared register before booting the kernel.
The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the
case; the boot ROM clears the WRITE_PROTECT register when the system
is booting from the NAND device, so the NAND device becomes read-only.
Set it to 1 in the driver in order to allow the write access to the
device.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This CONFIG option is only used in denali_spl.c
Move it close to SPL_NAND_DENALI, and make it depend on SPL_NAND_DENALI.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
- Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds
- QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based
platforms
- Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
This driver is safe to use in SPL without relocation. Denying
DM_FLAG_PRE_RELOC prevents its usability for verifying the main U-Boot
or other artifacts from the SPL unless needless enabling the full driver
set (SPL_OF_PLATDATA).
Fixes: 17e1174085 ("drivers: crypto: rsa_mod_exp: avoid DM_FLAG_PRE_RELOC")
CC: Heinrich Schuchardt <xypron.glpk@gmx.de>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
The DPC fixup for MAC address and enet_if is not made if
/board/ports node is missing in DPC file.
Add /board/ports or /ports nodes if them are missing.
Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Reviewed-by: Ioana Ciornei <Ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Similarly to iommu-map, the msi-map property must also be fixed up
in the device tree, in order for the icid -> streamid translation
be possible in the MSI case as well.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Diana Craciun <diana.craciun@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bus callback functions for read/write/reset need to be set only for
DM_ETH, moving endif a bit lower.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.
Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.
This requires quite a few header-file additions.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should not be using typedefs and these make it harder to use
forward declarations (to reduce header file inclusions). Drop the typedef.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.
Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is bad practice to include common.h in other header files since it can
bring in any number of superfluous definitions. It implies that some C
files don't include it and thus may be missing CONFIG options that are set
up by that file. The C files should include these themselves.
Update some header files in arch/arm to drop this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move this uncommon header out of the common header.
Fix up some style problems in flash.h while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Virtually all callers of this function do the rounding on their own.
Some do it right, some don't. Instead of doing this in each caller,
do the rounding in efi_add_memory_map(). Change the size parameter
to bytes instead of pages and remove aligning and size calculation in
all callers.
There is no more need to make the original efi_add_memory_map() (which
takes pages as size) available outside the module. Thus rename it to
efi_add_memory_map_pg() and make it static to prevent further misuse
outside the module.
Signed-off-by: Michael Walle <michael@walle.cc>
Add missing comma in sunxi_display.c.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Have this symbol follow the pattern of all other such symbols.
This patch also removes a TODO from the code.
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Have this symbol follow the pattern of all other such symbols.
This patch removes a TODO from the code.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
- stm32mp1: add command stm32prog
- stm32mp1: several board and arch updates
- stm32mp1: activate data cache in SPL and before relocation
- Many improvment for AV96 board and DHCOR SoM
(add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM
Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM)
- clk: stm32mp1: fix CK_MPU calculation
- DT alignment of stm32mp1 device tree with Linux 5.7-rc2
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Merge tag 'u-boot-stm32-20200514' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- stm32mp1: migrate MTD and DFU configuration in Kconfig
- stm32mp1: add command stm32prog
- stm32mp1: several board and arch updates
- stm32mp1: activate data cache in SPL and before relocation
- Many improvment for AV96 board and DHCOR SoM
(add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM
Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM)
- clk: stm32mp1: fix CK_MPU calculation
- DT alignment of stm32mp1 device tree with Linux 5.7-rc2
- sync RPi4's env size with other RPi configs
- add kconfig option to reserver more pages in the EFI mem map
- add support for SDMA which is used by RPi4
- fix corner case boot bug for RPi3 32-bit
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Merge tag 'rpi-next-2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi
- fix phy configuration for RPi4's bcmgenet
- sync RPi4's env size with other RPi configs
- add kconfig option to reserver more pages in the EFI mem map
- add support for SDMA which is used by RPi4
- fix corner case boot bug for RPi3 32-bit
When the CK_MPU used PLL1_MPUDIV, the current rate is
wrong. The clock must use stm32mp1_mpu_div as a shift
value. Fix the check value used to enter PLL_MPUDIV.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change the mmc displayed name in U-Boot for stm32_sdmmc2 driver to
“STM32 SD/MMC”.
This stm32_sdmmc2 driver is for version 2 of the ST HW IP SDMMC but the
displayed name "STM32 SDMMC2" is confusing for user, between the
instance of SDMMC and the device identifier of MMC.
For example on EV1 board, we have:
STM32MP1> mmc list
STM32 SDMMC2: 0 (SD)
STM32 SDMMC2: 1 (eMMC)
Changed to more clear:
STM32MP1> mmc list
STM32 SD/MMC: 0 (SD)
STM32 SD/MMC: 1 (eMMC)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
The GPIO support is needed in SPL to managed the SD cart detect
used on stm32mp157c-ev1 and dk2 board.
So this patch activates the associated code in stm32_gpio.c.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add a function g_dnl_set_product to change the Product string used in USB
enumeration in any command based on download gadget.
If the function is called with NULL pointer, the product string is set to
the default value (product[] = "USB download gadget").
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add support for multiple DRAM configuration subnodes, while retaining
the support for a single flat DRAM configuration node. This is useful
on systems which can be manufactured in multiple configurations and
where the DRAM configuration can be determined at runtime.
The code is augmented by a function which can be overridden on board
level, allowing a match on the configuration node name, very much like
the fitImage configuration node name matching works. The default match
is on the single top-level DRAM configuration, if matching on subnodes
is required, then this board_stm32mp1_ddr_config_name_match() must be
overridden.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
HSDK and HSDK-4xD clock trees are slightly different.
commit 1dfb2ec0d7 ("ARC: HSDK: CGU: add support for timer clock")
introduce regression for HSDK board cause crash when setting
tunnel clock. Fix that.
Fixes: 1dfb2ec0d7 ("ARC: HSDK: CGU: add support for timer clock")
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We don't want to allow change some clocks, i.e. DDR clock.
So allow to have set_clock to be unset in clock map.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
The clock trees of HSDK and HSDK-4xD vary so we need to prepare
CGU driver for multiple clock maps support.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* constify clocks config data where is possible
* use more appropriate data types for clocks config
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Drop creg_div_oft offset as it doesn't vary (due to it is used for
CPU PLL only).
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
hsdk_axi_clk_cfg and hsdk_tun_clk_cfg clock divider structures
and functions for their processing are almost the same so
merge them to avoid code duplication.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
If CONFIG_MMC_SDHCI_SDMA is enabled but the HW could not support it,
we no longer error out. Instead we do not enable it in the host.
Change the output from printf to debug as this isn't an error but only
additional information now.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
If Host controller doesn't support SDMA, it doesn't need to return
error. Because it can be worked with PIO mode.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Use phys2bus macro when dma address is accessed.
Some targets need to use pyhs2bus macro. (e.g, RPI4)
After applied it, SDMA mode can be used.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
We cannot rely on a parent bus that needs to be probed, until we know that
it is probed. That means that code in the ofdata_to_platdata() method
cannot rely on the parent bus being probed.
Move the ofdata code in the two serial drivers into a probe() method.
This fixes serial output on rpi_3b_32b with the following config.txt
options:
enable_uart=1
gpu_freq=250
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
As per Linux's driver, ID_MODE_DIS is only set when the PHY interface is
RGMII. Don't enable it for the rest of setups.
This has been seen to misconfigure RPi4's PHY when booting Linux.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Xilinx Versal platform uses dwc3 and hence its compatible string
needs to be added to dwc3 glue ids.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Reference from below Linux commit,
commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Handle the GPIOD_OPEN_DRAIN & GPIOD_OPEN_SOURCE flags to emulate open drain
and open source by setting the GPIO line as input depending on the
requested value.
The behaviour is taken from the Linux gpiolib.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On i.mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters
and IDs to flash parameter array. Otherwise, the flash probe will fails.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Probably the non-use of the device parameter by the print routines did
not generate compilation errors.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Board gets reset when performing burst read/write operations. On the
other hand, no such behaviour is observed on small size operations.
In Linux, readl_poll_timeout API already adds delay of 1us which is
further skipped in U-boot. Hence, use new "readl_poll_sleep_timeout" API
which adds delay alongwith timeout functionality.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Clients that are requesting some of uclass API's
without a device (with ofnode) usually have _nodev
naming convention.
- clk_get_by_index_nodev
- clk_get_by_name_nodev
- reset_get_by_index_nodev
- gpio_request_by_name_nodev
So, update the same naming convention PHY framework.
This doesn't change the existing functionality.
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
lpc32xx_ssp driver is deprecated, no active updates
and no board user, hence dropped the same.
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.aribaud@3adev.fr>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Make sure that all devices that are powered up by SPL are powered down
before entering into the u-boot. Otherwise the subsystem/device will
never be powered down by SCFW, due to SPL and u-boot are in different
partitions.
Benefiting from power domain driver, this patch implements the function
"imx8_power_off_pd_devices" to power off all active devices.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add more BCH setting mode and remove the unnecessary platform constrain
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.
The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.
Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When fspi is assigned to M4, we have to let the fspi probe failed when
its power domain is failed to power up. Because not all devices have power
domain (for example, external devices on the board). Current checking
resource owner in power domain probe is not good, change to check it in
power on.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
For all the devices used and set ACTIVE in U-Boot, U-Boot needs
to power off all of them without the check of resource owner.
When we create software partition before booting Linux, the resource
own checkw will return false, and cause the power domain not powered
off. If without the check of resource owner, the power domain in
the other software partition could be powered off with parent
partition could access child partition resources.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
If without this flag, calling dev_power_domain_ctrl will iteratively remove
the power domain device will causes iteratively power off parent PD. This is
not expected by imx8-power-domain-legacy driver. Power off parent PD is
controlled by the driver internally.
So set DM_FLAG_DEFAULT_PD_CTRL_OFF to avoid such issue
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add power_domain_lookup_name interface to power domain uclass to find
a power domain device by its DTB node name, not using its associated
client device.
Through this interface, we can operate the power domain devices directly.
This is needed for non-DM drivers.
Modified from Ye's NXP downstream patch
only for legacy imx8 power domain driver, since we have not migrated
to use new power domain driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To enable the Randomizer module, set GPMI_ECCCTRL[RANDOMIZER_ENABLE] to
1, then set GPMI_ECCCOUNT[RANDOMIZER_PAGE] to select randomizer page
number needed to be randomized.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
