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https://github.com/AsahiLinux/u-boot
synced 2024-11-29 16:10:58 +00:00
net: eepro100: Pass device private data around
This patch replaces the various uses of struct eth_device for accessing device private data with struct eepro100_priv, which is compatible both with DM and non-DM operation. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
parent
bd159c6185
commit
389da9743c
1 changed files with 140 additions and 124 deletions
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@ -203,6 +203,10 @@ static const char i82558_config_cmd[] = {
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struct eepro100_priv {
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struct eth_device dev;
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pci_dev_t devno;
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char *name;
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void __iomem *iobase;
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u8 *enetaddr;
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};
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#if defined(CONFIG_E500)
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@ -213,40 +217,40 @@ struct eepro100_priv {
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#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
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#endif
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static int INW(struct eth_device *dev, u_long addr)
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static int INW(struct eepro100_priv *priv, u_long addr)
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{
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return le16_to_cpu(readw(addr + (void *)dev->iobase));
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return le16_to_cpu(readw(addr + priv->iobase));
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}
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static void OUTW(struct eth_device *dev, int command, u_long addr)
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static void OUTW(struct eepro100_priv *priv, int command, u_long addr)
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{
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writew(cpu_to_le16(command), addr + (void *)dev->iobase);
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writew(cpu_to_le16(command), addr + priv->iobase);
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}
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static void OUTL(struct eth_device *dev, int command, u_long addr)
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static void OUTL(struct eepro100_priv *priv, int command, u_long addr)
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{
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writel(cpu_to_le32(command), addr + (void *)dev->iobase);
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writel(cpu_to_le32(command), addr + priv->iobase);
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}
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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static int INL(struct eth_device *dev, u_long addr)
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static int INL(struct eepro100_priv *priv, u_long addr)
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{
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return le32_to_cpu(readl(addr + (void *)dev->iobase));
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return le32_to_cpu(readl(addr + priv->iobase));
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}
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static int get_phyreg(struct eth_device *dev, unsigned char addr,
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static int get_phyreg(struct eepro100_priv *priv, unsigned char addr,
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unsigned char reg, unsigned short *value)
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{
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int cmd;
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int timeout = 50;
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int cmd;
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/* read requested data */
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cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
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OUTL(dev, cmd, SCB_CTRL_MDI);
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OUTL(priv, cmd, SCB_CTRL_MDI);
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do {
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udelay(1000);
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cmd = INL(dev, SCB_CTRL_MDI);
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cmd = INL(priv, SCB_CTRL_MDI);
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} while (!(cmd & (1 << 28)) && (--timeout));
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if (timeout == 0)
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@ -257,17 +261,17 @@ static int get_phyreg(struct eth_device *dev, unsigned char addr,
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return 0;
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}
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static int set_phyreg(struct eth_device *dev, unsigned char addr,
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static int set_phyreg(struct eepro100_priv *priv, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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int cmd;
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int timeout = 50;
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int cmd;
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/* write requested data */
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cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
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OUTL(dev, cmd | value, SCB_CTRL_MDI);
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OUTL(priv, cmd | value, SCB_CTRL_MDI);
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while (!(INL(dev, SCB_CTRL_MDI) & (1 << 28)) && (--timeout))
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while (!(INL(priv, SCB_CTRL_MDI) & (1 << 28)) && (--timeout))
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udelay(1000);
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if (timeout == 0)
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@ -280,49 +284,45 @@ static int set_phyreg(struct eth_device *dev, unsigned char addr,
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* Check if given phyaddr is valid, i.e. there is a PHY connected.
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* Do this by checking model value field from ID2 register.
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*/
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static struct eth_device *verify_phyaddr(const char *devname,
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unsigned char addr)
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static int verify_phyaddr(struct eepro100_priv *priv, unsigned char addr)
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{
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struct eth_device *dev;
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unsigned short value;
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unsigned char model;
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dev = eth_get_dev_by_name(devname);
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if (!dev) {
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printf("%s: no such device\n", devname);
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return NULL;
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}
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unsigned short value, model;
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int ret;
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/* read id2 register */
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if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
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printf("%s: mii read timeout!\n", devname);
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return NULL;
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ret = get_phyreg(priv, addr, MII_PHYSID2, &value);
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if (ret) {
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printf("%s: mii read timeout!\n", priv->name);
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return ret;
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}
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/* get model */
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model = (unsigned char)((value >> 4) & 0x003f);
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if (model == 0) {
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printf("%s: no PHY at address %d\n", devname, addr);
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return NULL;
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model = (value >> 4) & 0x003f;
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if (!model) {
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printf("%s: no PHY at address %d\n", priv->name, addr);
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return -EINVAL;
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}
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return dev;
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return 0;
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}
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static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
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int reg)
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{
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struct eth_device *dev = eth_get_dev_by_name(bus->name);
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struct eepro100_priv *priv =
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container_of(dev, struct eepro100_priv, dev);
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unsigned short value = 0;
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struct eth_device *dev;
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int ret;
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dev = verify_phyaddr(bus->name, addr);
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if (!dev)
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return -1;
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ret = verify_phyaddr(priv, addr);
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if (ret)
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return ret;
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if (get_phyreg(dev, addr, reg, &value) != 0) {
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ret = get_phyreg(priv, addr, reg, &value);
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if (ret) {
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printf("%s: mii read timeout!\n", bus->name);
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return -1;
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return ret;
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}
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return value;
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@ -331,23 +331,26 @@ static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
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static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
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int reg, u16 value)
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{
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struct eth_device *dev;
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struct eth_device *dev = eth_get_dev_by_name(bus->name);
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struct eepro100_priv *priv =
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container_of(dev, struct eepro100_priv, dev);
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int ret;
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dev = verify_phyaddr(bus->name, addr);
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if (!dev)
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return -1;
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ret = verify_phyaddr(priv, addr);
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if (ret)
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return ret;
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if (set_phyreg(dev, addr, reg, value) != 0) {
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ret = set_phyreg(priv, addr, reg, value);
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if (ret) {
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printf("%s: mii write timeout!\n", bus->name);
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return -1;
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return ret;
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}
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return 0;
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}
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#endif
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static void init_rx_ring(struct eth_device *dev)
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static void init_rx_ring(struct eepro100_priv *priv)
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{
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int i;
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@ -356,7 +359,7 @@ static void init_rx_ring(struct eth_device *dev)
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rx_ring[i].control = (i == NUM_RX_DESC - 1) ?
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cpu_to_le16 (RFD_CONTROL_S) : 0;
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rx_ring[i].link =
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cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
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cpu_to_le32(phys_to_bus(priv->devno,
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(u32)&rx_ring[(i + 1) %
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NUM_RX_DESC]));
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rx_ring[i].rx_buf_addr = 0xffffffff;
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@ -370,7 +373,7 @@ static void init_rx_ring(struct eth_device *dev)
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rx_next = 0;
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}
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static void purge_tx_ring(struct eth_device *dev)
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static void purge_tx_ring(struct eepro100_priv *priv)
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{
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tx_next = 0;
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tx_threshold = 0x01208000;
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}
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/* Wait for the chip get the command. */
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static int wait_for_eepro100(struct eth_device *dev)
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static int wait_for_eepro100(struct eepro100_priv *priv)
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{
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int i;
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for (i = 0; INW(dev, SCB_CMD) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
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for (i = 0; INW(priv, SCB_CMD) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
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if (i >= TOUT_LOOP)
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return 0;
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}
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@ -394,7 +397,7 @@ static int wait_for_eepro100(struct eth_device *dev)
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return 1;
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}
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static int eepro100_txcmd_send(struct eth_device *dev,
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static int eepro100_txcmd_send(struct eepro100_priv *priv,
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struct eepro100_txfd *desc)
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{
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u16 rstat;
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@ -403,11 +406,11 @@ static int eepro100_txcmd_send(struct eth_device *dev,
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flush_dcache_range((unsigned long)desc,
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(unsigned long)desc + sizeof(*desc));
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if (!wait_for_eepro100(dev))
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if (!wait_for_eepro100(priv))
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return -ETIMEDOUT;
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OUTL(dev, phys_to_bus((pci_dev_t)dev->priv, (u32)desc), SCB_POINTER);
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OUTW(dev, SCB_M | CU_START, SCB_CMD);
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OUTL(priv, phys_to_bus(priv->devno, (u32)desc), SCB_POINTER);
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OUTW(priv, SCB_M | CU_START, SCB_CMD);
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while (true) {
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invalidate_dcache_range((unsigned long)desc,
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break;
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if (i++ >= TOUT_LOOP) {
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printf("%s: Tx error buffer not ready\n", dev->name);
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printf("%s: Tx error buffer not ready\n", priv->name);
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return -EINVAL;
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}
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}
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}
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/* SROM Read. */
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static int read_eeprom(struct eth_device *dev, int location, int addr_len)
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static int read_eeprom(struct eepro100_priv *priv, int location, int addr_len)
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{
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unsigned short retval = 0;
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int read_cmd = location | EE_READ_CMD(addr_len);
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int i;
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OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
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OUTW(dev, EE_ENB, SCB_EEPROM);
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OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
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OUTW(priv, EE_ENB, SCB_EEPROM);
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/* Shift the read command bits out. */
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for (i = 12; i >= 0; i--) {
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short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
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OUTW(dev, EE_ENB | dataval, SCB_EEPROM);
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OUTW(priv, EE_ENB | dataval, SCB_EEPROM);
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udelay(1);
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OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
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OUTW(priv, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
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udelay(1);
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}
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OUTW(dev, EE_ENB, SCB_EEPROM);
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OUTW(priv, EE_ENB, SCB_EEPROM);
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for (i = 15; i >= 0; i--) {
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OUTW(dev, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
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OUTW(priv, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
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udelay(1);
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retval = (retval << 1) |
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((INW(dev, SCB_EEPROM) & EE_DATA_READ) ? 1 : 0);
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OUTW(dev, EE_ENB, SCB_EEPROM);
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!!(INW(priv, SCB_EEPROM) & EE_DATA_READ);
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OUTW(priv, EE_ENB, SCB_EEPROM);
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udelay(1);
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}
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/* Terminate the EEPROM access. */
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OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
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OUTW(priv, EE_ENB & ~EE_CS, SCB_EEPROM);
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return retval;
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}
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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static int eepro100_initialize_mii(struct eth_device *dev)
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static int eepro100_initialize_mii(struct eepro100_priv *priv)
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{
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/* register mii command access routines */
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struct mii_dev *mdiodev;
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@ -480,7 +483,7 @@ static int eepro100_initialize_mii(struct eth_device *dev)
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
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strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
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mdiodev->read = eepro100_miiphy_read;
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mdiodev->write = eepro100_miiphy_write;
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@ -493,7 +496,7 @@ static int eepro100_initialize_mii(struct eth_device *dev)
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return 0;
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}
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#else
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static int eepro100_initialize_mii(struct eth_device *dev)
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static int eepro100_initialize_mii(struct eepro100_priv *priv)
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{
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return 0;
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}
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@ -506,70 +509,72 @@ static struct pci_device_id supported[] = {
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{ }
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};
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static void read_hw_addr(struct eth_device *dev, bd_t *bis)
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static void read_hw_addr(struct eepro100_priv *priv, bd_t *bis)
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{
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u16 sum = 0;
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int i, j;
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int addr_len = read_eeprom(dev, 0, 6) == 0xffff ? 8 : 6;
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int addr_len = read_eeprom(priv, 0, 6) == 0xffff ? 8 : 6;
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for (j = 0, i = 0; i < 0x40; i++) {
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u16 value = read_eeprom(dev, i, addr_len);
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u16 value = read_eeprom(priv, i, addr_len);
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sum += value;
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if (i < 3) {
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dev->enetaddr[j++] = value;
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dev->enetaddr[j++] = value >> 8;
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priv->enetaddr[j++] = value;
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priv->enetaddr[j++] = value >> 8;
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}
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}
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if (sum != 0xBABA) {
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memset(dev->enetaddr, 0, ETH_ALEN);
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memset(priv->enetaddr, 0, ETH_ALEN);
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debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n",
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dev->name, sum);
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priv->name, sum);
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}
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}
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static int eepro100_init(struct eth_device *dev, bd_t *bis)
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{
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struct eepro100_priv *priv =
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container_of(dev, struct eepro100_priv, dev);
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struct eepro100_txfd *ias_cmd, *cfg_cmd;
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int ret, status = -1;
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int tx_cur;
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/* Reset the ethernet controller */
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OUTL(dev, I82559_SELECTIVE_RESET, SCB_PORT);
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OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
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udelay(20);
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OUTL(dev, I82559_RESET, SCB_PORT);
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OUTL(priv, I82559_RESET, SCB_PORT);
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udelay(20);
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if (!wait_for_eepro100(dev)) {
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if (!wait_for_eepro100(priv)) {
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printf("Error: Can not reset ethernet controller.\n");
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goto done;
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}
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OUTL(dev, 0, SCB_POINTER);
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OUTW(dev, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
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OUTL(priv, 0, SCB_POINTER);
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OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
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if (!wait_for_eepro100(dev)) {
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if (!wait_for_eepro100(priv)) {
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printf("Error: Can not reset ethernet controller.\n");
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goto done;
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}
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OUTL(dev, 0, SCB_POINTER);
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OUTW(dev, SCB_M | CU_ADDR_LOAD, SCB_CMD);
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OUTL(priv, 0, SCB_POINTER);
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OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
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/* Initialize Rx and Tx rings. */
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init_rx_ring(dev);
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purge_tx_ring(dev);
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init_rx_ring(priv);
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purge_tx_ring(priv);
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/* Tell the adapter where the RX ring is located. */
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if (!wait_for_eepro100(dev)) {
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if (!wait_for_eepro100(priv)) {
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printf("Error: Can not reset ethernet controller.\n");
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goto done;
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}
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/* RX ring cache was already flushed in init_rx_ring() */
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OUTL(dev, phys_to_bus((pci_dev_t)dev->priv, (u32)&rx_ring[rx_next]),
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OUTL(priv, phys_to_bus(priv->devno, (u32)&rx_ring[rx_next]),
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SCB_POINTER);
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OUTW(dev, SCB_M | RUC_START, SCB_CMD);
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OUTW(priv, SCB_M | RUC_START, SCB_CMD);
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/* Send the Configure frame */
|
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tx_cur = tx_next;
|
||||
|
@ -579,13 +584,13 @@ static int eepro100_init(struct eth_device *dev, bd_t *bis)
|
|||
cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
|
||||
CONFIG_SYS_CMD_CONFIGURE);
|
||||
cfg_cmd->status = 0;
|
||||
cfg_cmd->link = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
|
||||
cfg_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
|
||||
(u32)&tx_ring[tx_next]));
|
||||
|
||||
memcpy(((struct descriptor *)cfg_cmd)->params, i82558_config_cmd,
|
||||
sizeof(i82558_config_cmd));
|
||||
|
||||
ret = eepro100_txcmd_send(dev, cfg_cmd);
|
||||
ret = eepro100_txcmd_send(priv, cfg_cmd);
|
||||
if (ret) {
|
||||
if (ret == -ETIMEDOUT)
|
||||
printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
|
||||
|
@ -600,12 +605,12 @@ static int eepro100_init(struct eth_device *dev, bd_t *bis)
|
|||
ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
|
||||
CONFIG_SYS_CMD_IAS);
|
||||
ias_cmd->status = 0;
|
||||
ias_cmd->link = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
|
||||
ias_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
|
||||
(u32)&tx_ring[tx_next]));
|
||||
|
||||
memcpy(((struct descriptor *)ias_cmd)->params, dev->enetaddr, 6);
|
||||
memcpy(((struct descriptor *)ias_cmd)->params, priv->enetaddr, 6);
|
||||
|
||||
ret = eepro100_txcmd_send(dev, ias_cmd);
|
||||
ret = eepro100_txcmd_send(priv, ias_cmd);
|
||||
if (ret) {
|
||||
if (ret == -ETIMEDOUT)
|
||||
printf("Error: Can not reset ethernet controller.\n");
|
||||
|
@ -620,12 +625,14 @@ done:
|
|||
|
||||
static int eepro100_send(struct eth_device *dev, void *packet, int length)
|
||||
{
|
||||
struct eepro100_priv *priv =
|
||||
container_of(dev, struct eepro100_priv, dev);
|
||||
struct eepro100_txfd *desc;
|
||||
int ret, status = -1;
|
||||
int tx_cur;
|
||||
|
||||
if (length <= 0) {
|
||||
printf("%s: bad packet size: %d\n", dev->name, length);
|
||||
printf("%s: bad packet size: %d\n", priv->name, length);
|
||||
goto done;
|
||||
}
|
||||
|
||||
|
@ -637,19 +644,19 @@ static int eepro100_send(struct eth_device *dev, void *packet, int length)
|
|||
TXCB_CMD_S | TXCB_CMD_EL);
|
||||
desc->status = 0;
|
||||
desc->count = cpu_to_le32(tx_threshold);
|
||||
desc->link = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
|
||||
(u32)&tx_ring[tx_next]));
|
||||
desc->tx_desc_addr = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
|
||||
desc->link = cpu_to_le32(phys_to_bus(priv->devno,
|
||||
(u32)&tx_ring[tx_next]));
|
||||
desc->tx_desc_addr = cpu_to_le32(phys_to_bus(priv->devno,
|
||||
(u32)&desc->tx_buf_addr0));
|
||||
desc->tx_buf_addr0 = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
|
||||
desc->tx_buf_addr0 = cpu_to_le32(phys_to_bus(priv->devno,
|
||||
(u_long)packet));
|
||||
desc->tx_buf_size0 = cpu_to_le32(length);
|
||||
|
||||
ret = eepro100_txcmd_send(dev, &tx_ring[tx_cur]);
|
||||
ret = eepro100_txcmd_send(priv, &tx_ring[tx_cur]);
|
||||
if (ret) {
|
||||
if (ret == -ETIMEDOUT)
|
||||
printf("%s: Tx error ethernet controller not ready.\n",
|
||||
dev->name);
|
||||
priv->name);
|
||||
goto done;
|
||||
}
|
||||
|
||||
|
@ -661,12 +668,14 @@ done:
|
|||
|
||||
static int eepro100_recv(struct eth_device *dev)
|
||||
{
|
||||
struct eepro100_priv *priv =
|
||||
container_of(dev, struct eepro100_priv, dev);
|
||||
struct eepro100_rxfd *desc;
|
||||
int rx_prev, length = 0;
|
||||
u16 status, stat;
|
||||
|
||||
stat = INW(dev, SCB_STATUS);
|
||||
OUTW(dev, stat & SCB_STATUS_RNR, SCB_STATUS);
|
||||
stat = INW(priv, SCB_STATUS);
|
||||
OUTW(priv, stat & SCB_STATUS_RNR, SCB_STATUS);
|
||||
|
||||
for (;;) {
|
||||
desc = &rx_ring[rx_next];
|
||||
|
@ -706,20 +715,20 @@ static int eepro100_recv(struct eth_device *dev)
|
|||
}
|
||||
|
||||
if (stat & SCB_STATUS_RNR) {
|
||||
printf("%s: Receiver is not ready, restart it !\n", dev->name);
|
||||
printf("%s: Receiver is not ready, restart it !\n", priv->name);
|
||||
|
||||
/* Reinitialize Rx ring. */
|
||||
init_rx_ring(dev);
|
||||
init_rx_ring(priv);
|
||||
|
||||
if (!wait_for_eepro100(dev)) {
|
||||
if (!wait_for_eepro100(priv)) {
|
||||
printf("Error: Can not restart ethernet controller.\n");
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* RX ring cache was already flushed in init_rx_ring() */
|
||||
OUTL(dev, phys_to_bus((pci_dev_t)dev->priv,
|
||||
(u32)&rx_ring[rx_next]), SCB_POINTER);
|
||||
OUTW(dev, SCB_M | RUC_START, SCB_CMD);
|
||||
OUTL(priv, phys_to_bus(priv->devno,
|
||||
(u32)&rx_ring[rx_next]), SCB_POINTER);
|
||||
OUTW(priv, SCB_M | RUC_START, SCB_CMD);
|
||||
}
|
||||
|
||||
done:
|
||||
|
@ -728,26 +737,29 @@ done:
|
|||
|
||||
static void eepro100_halt(struct eth_device *dev)
|
||||
{
|
||||
struct eepro100_priv *priv =
|
||||
container_of(dev, struct eepro100_priv, dev);
|
||||
|
||||
/* Reset the ethernet controller */
|
||||
OUTL(dev, I82559_SELECTIVE_RESET, SCB_PORT);
|
||||
OUTL(priv, I82559_SELECTIVE_RESET, SCB_PORT);
|
||||
udelay(20);
|
||||
|
||||
OUTL(dev, I82559_RESET, SCB_PORT);
|
||||
OUTL(priv, I82559_RESET, SCB_PORT);
|
||||
udelay(20);
|
||||
|
||||
if (!wait_for_eepro100(dev)) {
|
||||
if (!wait_for_eepro100(priv)) {
|
||||
printf("Error: Can not reset ethernet controller.\n");
|
||||
goto done;
|
||||
}
|
||||
OUTL(dev, 0, SCB_POINTER);
|
||||
OUTW(dev, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
|
||||
OUTL(priv, 0, SCB_POINTER);
|
||||
OUTW(priv, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
|
||||
|
||||
if (!wait_for_eepro100(dev)) {
|
||||
if (!wait_for_eepro100(priv)) {
|
||||
printf("Error: Can not reset ethernet controller.\n");
|
||||
goto done;
|
||||
}
|
||||
OUTL(dev, 0, SCB_POINTER);
|
||||
OUTW(dev, SCB_M | CU_ADDR_LOAD, SCB_CMD);
|
||||
OUTL(priv, 0, SCB_POINTER);
|
||||
OUTW(priv, SCB_M | CU_ADDR_LOAD, SCB_CMD);
|
||||
|
||||
done:
|
||||
return;
|
||||
|
@ -798,8 +810,12 @@ int eepro100_initialize(bd_t *bis)
|
|||
dev = &priv->dev;
|
||||
|
||||
sprintf(dev->name, "i82559#%d", card_number);
|
||||
dev->priv = (void *)devno; /* this have to come before bus_to_phys() */
|
||||
dev->iobase = bus_to_phys(devno, iobase);
|
||||
priv->name = dev->name;
|
||||
/* this have to come before bus_to_phys() */
|
||||
priv->devno = devno;
|
||||
priv->iobase = (void __iomem *)bus_to_phys(devno, iobase);
|
||||
priv->enetaddr = dev->enetaddr;
|
||||
|
||||
dev->init = eepro100_init;
|
||||
dev->halt = eepro100_halt;
|
||||
dev->send = eepro100_send;
|
||||
|
@ -807,7 +823,7 @@ int eepro100_initialize(bd_t *bis)
|
|||
|
||||
eth_register(dev);
|
||||
|
||||
ret = eepro100_initialize_mii(dev);
|
||||
ret = eepro100_initialize_mii(priv);
|
||||
if (ret) {
|
||||
eth_unregister(dev);
|
||||
free(priv);
|
||||
|
@ -821,7 +837,7 @@ int eepro100_initialize(bd_t *bis)
|
|||
|
||||
udelay(10 * 1000);
|
||||
|
||||
read_hw_addr(dev, bis);
|
||||
read_hw_addr(priv, bis);
|
||||
}
|
||||
|
||||
return card_number;
|
||||
|
|
Loading…
Reference in a new issue